2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
36 enum pl330_cachectrl {
37 CCTRL0, /* Noncacheable and nonbufferable */
38 CCTRL1, /* Bufferable only */
39 CCTRL2, /* Cacheable, but do not allocate */
40 CCTRL3, /* Cacheable and bufferable, but do not allocate */
41 INVALID1, /* AWCACHE = 0x1000 */
43 CCTRL6, /* Cacheable write-through, allocate on writes only */
44 CCTRL7, /* Cacheable write-back, allocate on writes only */
55 /* Register and Bit field Definitions */
57 #define DS_ST_STOP 0x0
58 #define DS_ST_EXEC 0x1
59 #define DS_ST_CMISS 0x2
60 #define DS_ST_UPDTPC 0x3
62 #define DS_ST_ATBRR 0x5
63 #define DS_ST_QBUSY 0x6
65 #define DS_ST_KILL 0x8
66 #define DS_ST_CMPLT 0x9
67 #define DS_ST_FLTCMP 0xe
68 #define DS_ST_FAULT 0xf
73 #define INTSTATUS 0x28
80 #define FTC(n) (_FTC + (n)*0x4)
83 #define CS(n) (_CS + (n)*0x8)
84 #define CS_CNS (1 << 21)
87 #define CPC(n) (_CPC + (n)*0x8)
90 #define SA(n) (_SA + (n)*0x20)
93 #define DA(n) (_DA + (n)*0x20)
96 #define CC(n) (_CC + (n)*0x20)
98 #define CC_SRCINC (1 << 0)
99 #define CC_DSTINC (1 << 14)
100 #define CC_SRCPRI (1 << 8)
101 #define CC_DSTPRI (1 << 22)
102 #define CC_SRCNS (1 << 9)
103 #define CC_DSTNS (1 << 23)
104 #define CC_SRCIA (1 << 10)
105 #define CC_DSTIA (1 << 24)
106 #define CC_SRCBRSTLEN_SHFT 4
107 #define CC_DSTBRSTLEN_SHFT 18
108 #define CC_SRCBRSTSIZE_SHFT 1
109 #define CC_DSTBRSTSIZE_SHFT 15
110 #define CC_SRCCCTRL_SHFT 11
111 #define CC_SRCCCTRL_MASK 0x7
112 #define CC_DSTCCTRL_SHFT 25
113 #define CC_DRCCCTRL_MASK 0x7
114 #define CC_SWAP_SHFT 28
117 #define LC0(n) (_LC0 + (n)*0x20)
120 #define LC1(n) (_LC1 + (n)*0x20)
122 #define DBGSTATUS 0xd00
123 #define DBG_BUSY (1 << 0)
126 #define DBGINST0 0xd08
127 #define DBGINST1 0xd0c
136 #define PERIPH_ID 0xfe0
137 #define PERIPH_REV_SHIFT 20
138 #define PERIPH_REV_MASK 0xf
139 #define PERIPH_REV_R0P0 0
140 #define PERIPH_REV_R1P0 1
141 #define PERIPH_REV_R1P1 2
143 #define CR0_PERIPH_REQ_SET (1 << 0)
144 #define CR0_BOOT_EN_SET (1 << 1)
145 #define CR0_BOOT_MAN_NS (1 << 2)
146 #define CR0_NUM_CHANS_SHIFT 4
147 #define CR0_NUM_CHANS_MASK 0x7
148 #define CR0_NUM_PERIPH_SHIFT 12
149 #define CR0_NUM_PERIPH_MASK 0x1f
150 #define CR0_NUM_EVENTS_SHIFT 17
151 #define CR0_NUM_EVENTS_MASK 0x1f
153 #define CR1_ICACHE_LEN_SHIFT 0
154 #define CR1_ICACHE_LEN_MASK 0x7
155 #define CR1_NUM_ICACHELINES_SHIFT 4
156 #define CR1_NUM_ICACHELINES_MASK 0xf
158 #define CRD_DATA_WIDTH_SHIFT 0
159 #define CRD_DATA_WIDTH_MASK 0x7
160 #define CRD_WR_CAP_SHIFT 4
161 #define CRD_WR_CAP_MASK 0x7
162 #define CRD_WR_Q_DEP_SHIFT 8
163 #define CRD_WR_Q_DEP_MASK 0xf
164 #define CRD_RD_CAP_SHIFT 12
165 #define CRD_RD_CAP_MASK 0x7
166 #define CRD_RD_Q_DEP_SHIFT 16
167 #define CRD_RD_Q_DEP_MASK 0xf
168 #define CRD_DATA_BUFF_SHIFT 20
169 #define CRD_DATA_BUFF_MASK 0x3ff
172 #define DESIGNER 0x41
174 #define INTEG_CFG 0x0
175 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177 #define PL330_STATE_STOPPED (1 << 0)
178 #define PL330_STATE_EXECUTING (1 << 1)
179 #define PL330_STATE_WFE (1 << 2)
180 #define PL330_STATE_FAULTING (1 << 3)
181 #define PL330_STATE_COMPLETING (1 << 4)
182 #define PL330_STATE_WFP (1 << 5)
183 #define PL330_STATE_KILLING (1 << 6)
184 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
185 #define PL330_STATE_CACHEMISS (1 << 8)
186 #define PL330_STATE_UPDTPC (1 << 9)
187 #define PL330_STATE_ATBARRIER (1 << 10)
188 #define PL330_STATE_QUEUEBUSY (1 << 11)
189 #define PL330_STATE_INVALID (1 << 15)
191 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
192 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194 #define CMD_DMAADDH 0x54
195 #define CMD_DMAEND 0x00
196 #define CMD_DMAFLUSHP 0x35
197 #define CMD_DMAGO 0xa0
198 #define CMD_DMALD 0x04
199 #define CMD_DMALDP 0x25
200 #define CMD_DMALP 0x20
201 #define CMD_DMALPEND 0x28
202 #define CMD_DMAKILL 0x01
203 #define CMD_DMAMOV 0xbc
204 #define CMD_DMANOP 0x18
205 #define CMD_DMARMB 0x12
206 #define CMD_DMASEV 0x34
207 #define CMD_DMAST 0x08
208 #define CMD_DMASTP 0x29
209 #define CMD_DMASTZ 0x0c
210 #define CMD_DMAWFE 0x36
211 #define CMD_DMAWFP 0x30
212 #define CMD_DMAWMB 0x13
216 #define SZ_DMAFLUSHP 2
220 #define SZ_DMALPEND 2
234 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
235 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
238 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
241 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
242 * at 1byte/burst for P<->M and M<->M respectively.
243 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
244 * should be enough for P<->M and M<->M respectively.
246 #define MCODE_BUFF_PER_REQ 256
248 /* If the _pl330_req is available to the client */
249 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
251 /* Use this _only_ to wait on transient states */
252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254 #ifdef PL330_DEBUG_MCGEN
255 static unsigned cmd_line;
256 #define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
261 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264 #define PL330_DBGMC_START(addr) do {} while (0)
267 /* The number of default descriptors */
269 #define NR_DEFAULT_DESC 16
271 /* Populated by the PL330 core driver for DMA API driver's info */
272 struct pl330_config {
274 #define DMAC_MODE_NS (1 << 0)
276 unsigned int data_bus_width:10; /* In number of bits */
277 unsigned int data_buf_dep:10;
278 unsigned int num_chan:4;
279 unsigned int num_peri:6;
281 unsigned int num_events:6;
285 /* Handle to the DMAC provided to the PL330 core */
289 /* Size of MicroCode buffers for each channel. */
291 /* ioremap'ed address of PL330 registers. */
293 /* Client can freely use it. */
295 /* PL330 core data, Client must not touch it. */
297 /* Populated by the PL330 core driver during pl330_add */
298 struct pl330_config pcfg;
300 * If the DMAC has some reset mechanism, then the
301 * client may want to provide pointer to the method.
303 void (*dmac_reset)(struct pl330_info *pi);
307 * Request Configuration.
308 * The PL330 core does not modify this and uses the last
309 * working configuration if the request doesn't provide any.
311 * The Client may want to provide this info only for the
312 * first request and a request with new settings.
314 struct pl330_reqcfg {
315 /* Address Incrementing */
320 * For now, the SRC & DST protection levels
321 * and burst size/length are assumed same.
327 unsigned brst_size:3; /* in power of 2 */
329 enum pl330_cachectrl dcctl;
330 enum pl330_cachectrl scctl;
331 enum pl330_byteswap swap;
332 struct pl330_config *pcfg;
336 * One cycle of DMAC operation.
337 * There may be more than one xfer in a request.
345 * Pointer to next xfer in the list.
346 * The last xfer in the req must point to NULL.
348 struct pl330_xfer *next;
351 /* The xfer callbacks are made with one of these arguments. */
353 /* The all xfers in the request were success. */
355 /* If req aborted due to global error. */
357 /* If req failed due to problem with Channel. */
361 /* A request defining Scatter-Gather List ending with NULL xfer. */
363 enum dma_transfer_direction rqtype;
364 /* Index of peripheral for the xfer. */
366 /* Unique token for this xfer, set by the client. */
368 /* Callback to be called after xfer. */
369 void (*xfer_cb)(void *token, enum pl330_op_err err);
370 /* If NULL, req will be done at last set parameters. */
371 struct pl330_reqcfg *cfg;
372 /* Pointer to first xfer in the request. */
373 struct pl330_xfer *x;
374 /* Hook to attach to DMAC's list of reqs with due callback */
375 struct list_head rqd;
379 * To know the status of the channel and DMAC, the client
380 * provides a pointer to this structure. The PL330 core
381 * fills it with current information.
383 struct pl330_chanstatus {
385 * If the DMAC engine halted due to some error,
386 * the client should remove-add DMAC.
390 * If channel is halted due to some error,
391 * the client should ABORT/FLUSH and START the channel.
394 /* Location of last load */
396 /* Location of last store */
399 * Pointer to the currently active req, NULL if channel is
400 * inactive, even though the requests may be present.
402 struct pl330_req *top_req;
403 /* Pointer to req waiting second in the queue if any. */
404 struct pl330_req *wait_req;
408 /* Start the channel */
410 /* Abort the active xfer */
412 /* Stop xfer and flush queue */
419 struct pl330_xfer *x;
442 /* Number of bytes taken to setup MC for the req */
447 /* ToBeDone for tasklet */
455 struct pl330_thread {
458 /* If the channel is not yet acquired by any client */
461 struct pl330_dmac *dmac;
462 /* Only two at a time */
463 struct _pl330_req req[2];
464 /* Index of the last enqueued request */
466 /* Index of the last submitted request or -1 if the DMA is stopped */
470 enum pl330_dmac_state {
479 /* Holds list of reqs with due callbacks */
480 struct list_head req_done;
481 /* Pointer to platform specific stuff */
482 struct pl330_info *pinfo;
483 /* Maximum possible events/irqs */
485 /* BUS address of MicroCode buffer */
486 dma_addr_t mcode_bus;
487 /* CPU address of MicroCode buffer */
489 /* List of all Channel threads */
490 struct pl330_thread *channels;
491 /* Pointer to the MANAGER thread */
492 struct pl330_thread *manager;
493 /* To handle bad news in interrupt */
494 struct tasklet_struct tasks;
495 struct _pl330_tbd dmac_tbd;
496 /* State of DMAC operation */
497 enum pl330_dmac_state state;
501 /* In the DMAC pool */
504 * Allocated to some channel during prep_xxx
505 * Also may be sitting on the work_list.
509 * Sitting on the work_list and already submitted
510 * to the PL330 core. Not more than two descriptors
511 * of a channel can be BUSY at any time.
515 * Sitting on the channel work_list but xfer done
521 struct dma_pl330_chan {
522 /* Schedule desc completion */
523 struct tasklet_struct task;
525 /* DMA-Engine Channel */
526 struct dma_chan chan;
528 /* List of submitted descriptors */
529 struct list_head submitted_list;
530 /* List of issued descriptors */
531 struct list_head work_list;
532 /* List of completed descriptors */
533 struct list_head completed_list;
535 /* Pointer to the DMAC that manages this channel,
536 * NULL if the channel is available to be acquired.
537 * As the parent, this DMAC also provides descriptors
540 struct dma_pl330_dmac *dmac;
542 /* To protect channel manipulation */
545 /* Token of a hardware channel thread of PL330 DMAC
546 * NULL if the channel is available to be acquired.
550 /* For D-to-M and M-to-D channels */
551 int burst_sz; /* the peripheral fifo width */
552 int burst_len; /* the number of burst */
553 dma_addr_t fifo_addr;
555 /* for cyclic capability */
559 struct dma_pl330_dmac {
560 struct pl330_info pif;
562 /* DMA-Engine Device */
563 struct dma_device ddma;
565 /* Holds info about sg limitations */
566 struct device_dma_parameters dma_parms;
568 /* Pool of descriptors available for the DMAC's channels */
569 struct list_head desc_pool;
570 /* To protect desc_pool manipulation */
571 spinlock_t pool_lock;
573 /* Peripheral channels connected to this DMAC */
574 unsigned int num_peripherals;
575 struct dma_pl330_chan *peripherals; /* keep at end */
578 struct dma_pl330_desc {
579 /* To attach to a queue as child */
580 struct list_head node;
582 /* Descriptor for the DMA Engine API */
583 struct dma_async_tx_descriptor txd;
585 /* Xfer for PL330 core */
586 struct pl330_xfer px;
588 struct pl330_reqcfg rqcfg;
589 struct pl330_req req;
591 enum desc_status status;
593 /* The channel which currently holds this desc */
594 struct dma_pl330_chan *pchan;
597 static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
600 r->xfer_cb(r->token, err);
603 static inline bool _queue_empty(struct pl330_thread *thrd)
605 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
609 static inline bool _queue_full(struct pl330_thread *thrd)
611 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
615 static inline bool is_manager(struct pl330_thread *thrd)
617 struct pl330_dmac *pl330 = thrd->dmac;
619 /* MANAGER is indexed at the end */
620 if (thrd->id == pl330->pinfo->pcfg.num_chan)
626 /* If manager of the thread is in Non-Secure mode */
627 static inline bool _manager_ns(struct pl330_thread *thrd)
629 struct pl330_dmac *pl330 = thrd->dmac;
631 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
634 static inline u32 get_revision(u32 periph_id)
636 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
639 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
640 enum pl330_dst da, u16 val)
645 buf[0] = CMD_DMAADDH;
647 *((u16 *)&buf[1]) = val;
649 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
650 da == 1 ? "DA" : "SA", val);
655 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
662 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
667 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
672 buf[0] = CMD_DMAFLUSHP;
678 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
683 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
691 buf[0] |= (0 << 1) | (1 << 0);
692 else if (cond == BURST)
693 buf[0] |= (1 << 1) | (1 << 0);
695 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
696 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
701 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
702 enum pl330_cond cond, u8 peri)
716 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
717 cond == SINGLE ? 'S' : 'B', peri >> 3);
722 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
723 unsigned loop, u8 cnt)
733 cnt--; /* DMAC increments by 1 internally */
736 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
742 enum pl330_cond cond;
748 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
749 const struct _arg_LPEND *arg)
751 enum pl330_cond cond = arg->cond;
752 bool forever = arg->forever;
753 unsigned loop = arg->loop;
754 u8 bjump = arg->bjump;
759 buf[0] = CMD_DMALPEND;
768 buf[0] |= (0 << 1) | (1 << 0);
769 else if (cond == BURST)
770 buf[0] |= (1 << 1) | (1 << 0);
774 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
775 forever ? "FE" : "END",
776 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
783 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
788 buf[0] = CMD_DMAKILL;
793 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
794 enum dmamov_dst dst, u32 val)
801 *((u32 *)&buf[2]) = val;
803 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
804 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
809 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
816 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
821 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
828 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
833 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
844 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
849 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
857 buf[0] |= (0 << 1) | (1 << 0);
858 else if (cond == BURST)
859 buf[0] |= (1 << 1) | (1 << 0);
861 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
862 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
867 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
868 enum pl330_cond cond, u8 peri)
882 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
883 cond == SINGLE ? 'S' : 'B', peri >> 3);
888 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
895 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
900 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
915 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
916 ev >> 3, invalidate ? ", I" : "");
921 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
922 enum pl330_cond cond, u8 peri)
930 buf[0] |= (0 << 1) | (0 << 0);
931 else if (cond == BURST)
932 buf[0] |= (1 << 1) | (0 << 0);
934 buf[0] |= (0 << 1) | (1 << 0);
940 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
941 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
946 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
953 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
964 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
965 const struct _arg_GO *arg)
968 u32 addr = arg->addr;
969 unsigned ns = arg->ns;
979 *((u32 *)&buf[2]) = addr;
984 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
986 /* Returns Time-Out */
987 static bool _until_dmac_idle(struct pl330_thread *thrd)
989 void __iomem *regs = thrd->dmac->pinfo->base;
990 unsigned long loops = msecs_to_loops(5);
993 /* Until Manager is Idle */
994 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
1006 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
1007 u8 insn[], bool as_manager)
1009 void __iomem *regs = thrd->dmac->pinfo->base;
1012 val = (insn[0] << 16) | (insn[1] << 24);
1015 val |= (thrd->id << 8); /* Channel Number */
1017 writel(val, regs + DBGINST0);
1019 val = *((u32 *)&insn[2]);
1020 writel(val, regs + DBGINST1);
1022 /* If timed out due to halted state-machine */
1023 if (_until_dmac_idle(thrd)) {
1024 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
1029 writel(0, regs + DBGCMD);
1033 * Mark a _pl330_req as free.
1034 * We do it by writing DMAEND as the first instruction
1035 * because no valid request is going to have DMAEND as
1036 * its first instruction to execute.
1038 static void mark_free(struct pl330_thread *thrd, int idx)
1040 struct _pl330_req *req = &thrd->req[idx];
1042 _emit_END(0, req->mc_cpu);
1045 thrd->req_running = -1;
1048 static inline u32 _state(struct pl330_thread *thrd)
1050 void __iomem *regs = thrd->dmac->pinfo->base;
1053 if (is_manager(thrd))
1054 val = readl(regs + DS) & 0xf;
1056 val = readl(regs + CS(thrd->id)) & 0xf;
1060 return PL330_STATE_STOPPED;
1062 return PL330_STATE_EXECUTING;
1064 return PL330_STATE_CACHEMISS;
1066 return PL330_STATE_UPDTPC;
1068 return PL330_STATE_WFE;
1070 return PL330_STATE_FAULTING;
1072 if (is_manager(thrd))
1073 return PL330_STATE_INVALID;
1075 return PL330_STATE_ATBARRIER;
1077 if (is_manager(thrd))
1078 return PL330_STATE_INVALID;
1080 return PL330_STATE_QUEUEBUSY;
1082 if (is_manager(thrd))
1083 return PL330_STATE_INVALID;
1085 return PL330_STATE_WFP;
1087 if (is_manager(thrd))
1088 return PL330_STATE_INVALID;
1090 return PL330_STATE_KILLING;
1092 if (is_manager(thrd))
1093 return PL330_STATE_INVALID;
1095 return PL330_STATE_COMPLETING;
1097 if (is_manager(thrd))
1098 return PL330_STATE_INVALID;
1100 return PL330_STATE_FAULT_COMPLETING;
1102 return PL330_STATE_INVALID;
1106 static void _stop(struct pl330_thread *thrd)
1108 void __iomem *regs = thrd->dmac->pinfo->base;
1109 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1111 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1112 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1114 /* Return if nothing needs to be done */
1115 if (_state(thrd) == PL330_STATE_COMPLETING
1116 || _state(thrd) == PL330_STATE_KILLING
1117 || _state(thrd) == PL330_STATE_STOPPED)
1120 _emit_KILL(0, insn);
1122 /* Stop generating interrupts for SEV */
1123 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1125 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1128 /* Start doing req 'idx' of thread 'thrd' */
1129 static bool _trigger(struct pl330_thread *thrd)
1131 void __iomem *regs = thrd->dmac->pinfo->base;
1132 struct _pl330_req *req;
1133 struct pl330_req *r;
1136 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1139 /* Return if already ACTIVE */
1140 if (_state(thrd) != PL330_STATE_STOPPED)
1143 idx = 1 - thrd->lstenq;
1144 if (!IS_FREE(&thrd->req[idx]))
1145 req = &thrd->req[idx];
1148 if (!IS_FREE(&thrd->req[idx]))
1149 req = &thrd->req[idx];
1154 /* Return if no request */
1155 if (!req || !req->r)
1161 ns = r->cfg->nonsecure ? 1 : 0;
1162 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1167 /* See 'Abort Sources' point-4 at Page 2-25 */
1168 if (_manager_ns(thrd) && !ns)
1169 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1170 __func__, __LINE__);
1173 go.addr = req->mc_bus;
1175 _emit_GO(0, insn, &go);
1177 /* Set to generate interrupts for SEV */
1178 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1180 /* Only manager can execute GO */
1181 _execute_DBGINSN(thrd, insn, true);
1183 thrd->req_running = idx;
1188 static bool _start(struct pl330_thread *thrd)
1190 switch (_state(thrd)) {
1191 case PL330_STATE_FAULT_COMPLETING:
1192 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1194 if (_state(thrd) == PL330_STATE_KILLING)
1195 UNTIL(thrd, PL330_STATE_STOPPED)
1197 case PL330_STATE_FAULTING:
1200 case PL330_STATE_KILLING:
1201 case PL330_STATE_COMPLETING:
1202 UNTIL(thrd, PL330_STATE_STOPPED)
1204 case PL330_STATE_STOPPED:
1205 return _trigger(thrd);
1207 case PL330_STATE_WFP:
1208 case PL330_STATE_QUEUEBUSY:
1209 case PL330_STATE_ATBARRIER:
1210 case PL330_STATE_UPDTPC:
1211 case PL330_STATE_CACHEMISS:
1212 case PL330_STATE_EXECUTING:
1215 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1221 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1222 const struct _xfer_spec *pxs, int cyc)
1225 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
1227 /* check lock-up free version */
1228 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1230 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1231 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1235 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1236 off += _emit_RMB(dry_run, &buf[off]);
1237 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1238 off += _emit_WMB(dry_run, &buf[off]);
1245 static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1246 const struct _xfer_spec *pxs, int cyc)
1251 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1252 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1253 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1254 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1260 static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1261 const struct _xfer_spec *pxs, int cyc)
1266 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1267 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1268 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1269 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1275 static int _bursts(unsigned dry_run, u8 buf[],
1276 const struct _xfer_spec *pxs, int cyc)
1280 switch (pxs->r->rqtype) {
1281 case DMA_MEM_TO_DEV:
1282 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1284 case DMA_DEV_TO_MEM:
1285 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1287 case DMA_MEM_TO_MEM:
1288 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1291 off += 0x40000000; /* Scare off the Client */
1298 /* Returns bytes consumed and updates bursts */
1299 static inline int _loop(unsigned dry_run, u8 buf[],
1300 unsigned long *bursts, const struct _xfer_spec *pxs)
1302 int cyc, cycmax, szlp, szlpend, szbrst, off;
1303 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1304 struct _arg_LPEND lpend;
1306 /* Max iterations possible in DMALP is 256 */
1307 if (*bursts >= 256*256) {
1310 cyc = *bursts / lcnt1 / lcnt0;
1311 } else if (*bursts > 256) {
1313 lcnt0 = *bursts / lcnt1;
1321 szlp = _emit_LP(1, buf, 0, 0);
1322 szbrst = _bursts(1, buf, pxs, 1);
1324 lpend.cond = ALWAYS;
1325 lpend.forever = false;
1328 szlpend = _emit_LPEND(1, buf, &lpend);
1336 * Max bursts that we can unroll due to limit on the
1337 * size of backward jump that can be encoded in DMALPEND
1338 * which is 8-bits and hence 255
1340 cycmax = (255 - (szlp + szlpend)) / szbrst;
1342 cyc = (cycmax < cyc) ? cycmax : cyc;
1347 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1351 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1354 off += _bursts(dry_run, &buf[off], pxs, cyc);
1356 lpend.cond = ALWAYS;
1357 lpend.forever = false;
1359 lpend.bjump = off - ljmp1;
1360 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1363 lpend.cond = ALWAYS;
1364 lpend.forever = false;
1366 lpend.bjump = off - ljmp0;
1367 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1370 *bursts = lcnt1 * cyc;
1377 static inline int _setup_loops(unsigned dry_run, u8 buf[],
1378 const struct _xfer_spec *pxs)
1380 struct pl330_xfer *x = pxs->x;
1382 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1387 off += _loop(dry_run, &buf[off], &c, pxs);
1394 static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1395 const struct _xfer_spec *pxs)
1397 struct pl330_xfer *x = pxs->x;
1400 /* DMAMOV SAR, x->src_addr */
1401 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1402 /* DMAMOV DAR, x->dst_addr */
1403 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1406 off += _setup_loops(dry_run, &buf[off], pxs);
1412 * A req is a sequence of one or more xfer units.
1413 * Returns the number of bytes taken to setup the MC for the req.
1415 static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1416 unsigned index, struct _xfer_spec *pxs)
1418 struct _pl330_req *req = &thrd->req[index];
1419 struct pl330_xfer *x;
1420 u8 *buf = req->mc_cpu;
1423 PL330_DBGMC_START(req->mc_bus);
1425 /* DMAMOV CCR, ccr */
1426 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1430 /* Error if xfer length is not aligned at burst size */
1431 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1435 off += _setup_xfer(dry_run, &buf[off], pxs);
1440 /* DMASEV peripheral/event */
1441 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1443 off += _emit_END(dry_run, &buf[off]);
1448 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1458 /* We set same protection levels for Src and DST for now */
1459 if (rqc->privileged)
1460 ccr |= CC_SRCPRI | CC_DSTPRI;
1462 ccr |= CC_SRCNS | CC_DSTNS;
1463 if (rqc->insnaccess)
1464 ccr |= CC_SRCIA | CC_DSTIA;
1466 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1467 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1469 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1470 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1472 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1473 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1475 ccr |= (rqc->swap << CC_SWAP_SHFT);
1480 static inline bool _is_valid(u32 ccr)
1482 enum pl330_cachectrl dcctl;
1483 enum pl330_cachectrl scctl;
1485 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1486 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1488 if (dcctl == INVALID1 || dcctl == INVALID2
1489 || scctl == INVALID1 || scctl == INVALID2)
1496 * Submit a list of xfers after which the client wants notification.
1497 * Client is not notified after each xfer unit, just once after all
1498 * xfer units are done or some error occurs.
1500 static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1502 struct pl330_thread *thrd = ch_id;
1503 struct pl330_dmac *pl330;
1504 struct pl330_info *pi;
1505 struct _xfer_spec xs;
1506 unsigned long flags;
1512 /* No Req or Unacquired Channel or DMAC */
1513 if (!r || !thrd || thrd->free)
1520 if (pl330->state == DYING
1521 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1522 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1523 __func__, __LINE__);
1527 /* If request for non-existing peripheral */
1528 if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pi->pcfg.num_peri) {
1529 dev_info(thrd->dmac->pinfo->dev,
1530 "%s:%d Invalid peripheral(%u)!\n",
1531 __func__, __LINE__, r->peri);
1535 spin_lock_irqsave(&pl330->lock, flags);
1537 if (_queue_full(thrd)) {
1543 /* Use last settings, if not provided */
1545 /* Prefer Secure Channel */
1546 if (!_manager_ns(thrd))
1547 r->cfg->nonsecure = 0;
1549 r->cfg->nonsecure = 1;
1551 ccr = _prepare_ccr(r->cfg);
1553 ccr = readl(regs + CC(thrd->id));
1556 /* If this req doesn't have valid xfer settings */
1557 if (!_is_valid(ccr)) {
1559 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1560 __func__, __LINE__, ccr);
1564 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1569 /* First dry run to check if req is acceptable */
1570 ret = _setup_req(1, thrd, idx, &xs);
1574 if (ret > pi->mcbufsz / 2) {
1575 dev_info(thrd->dmac->pinfo->dev,
1576 "%s:%d Trying increasing mcbufsz\n",
1577 __func__, __LINE__);
1582 /* Hook the request */
1584 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1585 thrd->req[idx].r = r;
1590 spin_unlock_irqrestore(&pl330->lock, flags);
1595 static void pl330_dotask(unsigned long data)
1597 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1598 struct pl330_info *pi = pl330->pinfo;
1599 unsigned long flags;
1602 spin_lock_irqsave(&pl330->lock, flags);
1604 /* The DMAC itself gone nuts */
1605 if (pl330->dmac_tbd.reset_dmac) {
1606 pl330->state = DYING;
1607 /* Reset the manager too */
1608 pl330->dmac_tbd.reset_mngr = true;
1609 /* Clear the reset flag */
1610 pl330->dmac_tbd.reset_dmac = false;
1613 if (pl330->dmac_tbd.reset_mngr) {
1614 _stop(pl330->manager);
1615 /* Reset all channels */
1616 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1617 /* Clear the reset flag */
1618 pl330->dmac_tbd.reset_mngr = false;
1621 for (i = 0; i < pi->pcfg.num_chan; i++) {
1623 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1624 struct pl330_thread *thrd = &pl330->channels[i];
1625 void __iomem *regs = pi->base;
1626 enum pl330_op_err err;
1630 if (readl(regs + FSC) & (1 << thrd->id))
1631 err = PL330_ERR_FAIL;
1633 err = PL330_ERR_ABORT;
1635 spin_unlock_irqrestore(&pl330->lock, flags);
1637 _callback(thrd->req[1 - thrd->lstenq].r, err);
1638 _callback(thrd->req[thrd->lstenq].r, err);
1640 spin_lock_irqsave(&pl330->lock, flags);
1642 thrd->req[0].r = NULL;
1643 thrd->req[1].r = NULL;
1647 /* Clear the reset flag */
1648 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1652 spin_unlock_irqrestore(&pl330->lock, flags);
1657 /* Returns 1 if state was updated, 0 otherwise */
1658 static int pl330_update(const struct pl330_info *pi)
1660 struct pl330_req *rqdone, *tmp;
1661 struct pl330_dmac *pl330;
1662 unsigned long flags;
1665 int id, ev, ret = 0;
1667 if (!pi || !pi->pl330_data)
1671 pl330 = pi->pl330_data;
1673 spin_lock_irqsave(&pl330->lock, flags);
1675 val = readl(regs + FSM) & 0x1;
1677 pl330->dmac_tbd.reset_mngr = true;
1679 pl330->dmac_tbd.reset_mngr = false;
1681 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1682 pl330->dmac_tbd.reset_chan |= val;
1685 while (i < pi->pcfg.num_chan) {
1686 if (val & (1 << i)) {
1688 "Reset Channel-%d\t CS-%x FTC-%x\n",
1689 i, readl(regs + CS(i)),
1690 readl(regs + FTC(i)));
1691 _stop(&pl330->channels[i]);
1697 /* Check which event happened i.e, thread notified */
1698 val = readl(regs + ES);
1699 if (pi->pcfg.num_events < 32
1700 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1701 pl330->dmac_tbd.reset_dmac = true;
1702 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1707 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1708 if (val & (1 << ev)) { /* Event occurred */
1709 struct pl330_thread *thrd;
1710 u32 inten = readl(regs + INTEN);
1713 /* Clear the event */
1714 if (inten & (1 << ev))
1715 writel(1 << ev, regs + INTCLR);
1719 id = pl330->events[ev];
1721 thrd = &pl330->channels[id];
1723 active = thrd->req_running;
1724 if (active == -1) /* Aborted */
1727 /* Detach the req */
1728 rqdone = thrd->req[active].r;
1729 thrd->req[active].r = NULL;
1731 mark_free(thrd, active);
1733 /* Get going again ASAP */
1736 /* For now, just make a list of callbacks to be done */
1737 list_add_tail(&rqdone->rqd, &pl330->req_done);
1741 /* Now that we are in no hurry, do the callbacks */
1742 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1743 list_del(&rqdone->rqd);
1745 spin_unlock_irqrestore(&pl330->lock, flags);
1746 _callback(rqdone, PL330_ERR_NONE);
1747 spin_lock_irqsave(&pl330->lock, flags);
1751 spin_unlock_irqrestore(&pl330->lock, flags);
1753 if (pl330->dmac_tbd.reset_dmac
1754 || pl330->dmac_tbd.reset_mngr
1755 || pl330->dmac_tbd.reset_chan) {
1757 tasklet_schedule(&pl330->tasks);
1763 static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1765 struct pl330_thread *thrd = ch_id;
1766 struct pl330_dmac *pl330;
1767 unsigned long flags;
1768 int ret = 0, active;
1770 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1774 active = thrd->req_running;
1776 spin_lock_irqsave(&pl330->lock, flags);
1779 case PL330_OP_FLUSH:
1780 /* Make sure the channel is stopped */
1783 thrd->req[0].r = NULL;
1784 thrd->req[1].r = NULL;
1789 case PL330_OP_ABORT:
1790 /* Make sure the channel is stopped */
1793 /* ABORT is only for the active req */
1797 thrd->req[active].r = NULL;
1798 mark_free(thrd, active);
1800 /* Start the next */
1801 case PL330_OP_START:
1802 if ((active == -1) && !_start(thrd))
1810 spin_unlock_irqrestore(&pl330->lock, flags);
1814 /* Reserve an event */
1815 static inline int _alloc_event(struct pl330_thread *thrd)
1817 struct pl330_dmac *pl330 = thrd->dmac;
1818 struct pl330_info *pi = pl330->pinfo;
1821 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1822 if (pl330->events[ev] == -1) {
1823 pl330->events[ev] = thrd->id;
1830 static bool _chan_ns(const struct pl330_info *pi, int i)
1832 return pi->pcfg.irq_ns & (1 << i);
1835 /* Upon success, returns IdentityToken for the
1836 * allocated channel, NULL otherwise.
1838 static void *pl330_request_channel(const struct pl330_info *pi)
1840 struct pl330_thread *thrd = NULL;
1841 struct pl330_dmac *pl330;
1842 unsigned long flags;
1845 if (!pi || !pi->pl330_data)
1848 pl330 = pi->pl330_data;
1850 if (pl330->state == DYING)
1853 chans = pi->pcfg.num_chan;
1855 spin_lock_irqsave(&pl330->lock, flags);
1857 for (i = 0; i < chans; i++) {
1858 thrd = &pl330->channels[i];
1859 if ((thrd->free) && (!_manager_ns(thrd) ||
1861 thrd->ev = _alloc_event(thrd);
1862 if (thrd->ev >= 0) {
1865 thrd->req[0].r = NULL;
1867 thrd->req[1].r = NULL;
1875 spin_unlock_irqrestore(&pl330->lock, flags);
1880 /* Release an event */
1881 static inline void _free_event(struct pl330_thread *thrd, int ev)
1883 struct pl330_dmac *pl330 = thrd->dmac;
1884 struct pl330_info *pi = pl330->pinfo;
1886 /* If the event is valid and was held by the thread */
1887 if (ev >= 0 && ev < pi->pcfg.num_events
1888 && pl330->events[ev] == thrd->id)
1889 pl330->events[ev] = -1;
1892 static void pl330_release_channel(void *ch_id)
1894 struct pl330_thread *thrd = ch_id;
1895 struct pl330_dmac *pl330;
1896 unsigned long flags;
1898 if (!thrd || thrd->free)
1903 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1904 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1908 spin_lock_irqsave(&pl330->lock, flags);
1909 _free_event(thrd, thrd->ev);
1911 spin_unlock_irqrestore(&pl330->lock, flags);
1914 /* Initialize the structure for PL330 configuration, that can be used
1915 * by the client driver the make best use of the DMAC
1917 static void read_dmac_config(struct pl330_info *pi)
1919 void __iomem *regs = pi->base;
1922 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1923 val &= CRD_DATA_WIDTH_MASK;
1924 pi->pcfg.data_bus_width = 8 * (1 << val);
1926 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1927 val &= CRD_DATA_BUFF_MASK;
1928 pi->pcfg.data_buf_dep = val + 1;
1930 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1931 val &= CR0_NUM_CHANS_MASK;
1933 pi->pcfg.num_chan = val;
1935 val = readl(regs + CR0);
1936 if (val & CR0_PERIPH_REQ_SET) {
1937 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1939 pi->pcfg.num_peri = val;
1940 pi->pcfg.peri_ns = readl(regs + CR4);
1942 pi->pcfg.num_peri = 0;
1945 val = readl(regs + CR0);
1946 if (val & CR0_BOOT_MAN_NS)
1947 pi->pcfg.mode |= DMAC_MODE_NS;
1949 pi->pcfg.mode &= ~DMAC_MODE_NS;
1951 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1952 val &= CR0_NUM_EVENTS_MASK;
1954 pi->pcfg.num_events = val;
1956 pi->pcfg.irq_ns = readl(regs + CR3);
1959 static inline void _reset_thread(struct pl330_thread *thrd)
1961 struct pl330_dmac *pl330 = thrd->dmac;
1962 struct pl330_info *pi = pl330->pinfo;
1964 thrd->req[0].mc_cpu = pl330->mcode_cpu
1965 + (thrd->id * pi->mcbufsz);
1966 thrd->req[0].mc_bus = pl330->mcode_bus
1967 + (thrd->id * pi->mcbufsz);
1968 thrd->req[0].r = NULL;
1971 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1973 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1975 thrd->req[1].r = NULL;
1979 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1981 struct pl330_info *pi = pl330->pinfo;
1982 int chans = pi->pcfg.num_chan;
1983 struct pl330_thread *thrd;
1986 /* Allocate 1 Manager and 'chans' Channel threads */
1987 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1989 if (!pl330->channels)
1992 /* Init Channel threads */
1993 for (i = 0; i < chans; i++) {
1994 thrd = &pl330->channels[i];
1997 _reset_thread(thrd);
2001 /* MANAGER is indexed at the end */
2002 thrd = &pl330->channels[chans];
2006 pl330->manager = thrd;
2011 static int dmac_alloc_resources(struct pl330_dmac *pl330)
2013 struct pl330_info *pi = pl330->pinfo;
2014 int chans = pi->pcfg.num_chan;
2018 * Alloc MicroCode buffer for 'chans' Channel threads.
2019 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2021 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
2022 chans * pi->mcbufsz,
2023 &pl330->mcode_bus, GFP_KERNEL);
2024 if (!pl330->mcode_cpu) {
2025 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2026 __func__, __LINE__);
2030 ret = dmac_alloc_threads(pl330);
2032 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
2033 __func__, __LINE__);
2034 dma_free_coherent(pi->dev,
2035 chans * pi->mcbufsz,
2036 pl330->mcode_cpu, pl330->mcode_bus);
2043 static int pl330_add(struct pl330_info *pi)
2045 struct pl330_dmac *pl330;
2049 if (!pi || !pi->dev)
2052 /* If already added */
2057 * If the SoC can perform reset on the DMAC, then do it
2058 * before reading its configuration.
2065 /* Check if we can handle this DMAC */
2066 if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
2067 dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id);
2071 /* Read the configuration of the DMAC */
2072 read_dmac_config(pi);
2074 if (pi->pcfg.num_events == 0) {
2075 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2076 __func__, __LINE__);
2080 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2082 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2083 __func__, __LINE__);
2087 /* Assign the info structure and private data */
2089 pi->pl330_data = pl330;
2091 spin_lock_init(&pl330->lock);
2093 INIT_LIST_HEAD(&pl330->req_done);
2095 /* Use default MC buffer size if not provided */
2097 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2099 /* Mark all events as free */
2100 for (i = 0; i < pi->pcfg.num_events; i++)
2101 pl330->events[i] = -1;
2103 /* Allocate resources needed by the DMAC */
2104 ret = dmac_alloc_resources(pl330);
2106 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2111 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2113 pl330->state = INIT;
2118 static int dmac_free_threads(struct pl330_dmac *pl330)
2120 struct pl330_info *pi = pl330->pinfo;
2121 int chans = pi->pcfg.num_chan;
2122 struct pl330_thread *thrd;
2125 /* Release Channel threads */
2126 for (i = 0; i < chans; i++) {
2127 thrd = &pl330->channels[i];
2128 pl330_release_channel((void *)thrd);
2132 kfree(pl330->channels);
2137 static void dmac_free_resources(struct pl330_dmac *pl330)
2139 struct pl330_info *pi = pl330->pinfo;
2140 int chans = pi->pcfg.num_chan;
2142 dmac_free_threads(pl330);
2144 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2145 pl330->mcode_cpu, pl330->mcode_bus);
2148 static void pl330_del(struct pl330_info *pi)
2150 struct pl330_dmac *pl330;
2152 if (!pi || !pi->pl330_data)
2155 pl330 = pi->pl330_data;
2157 pl330->state = UNINIT;
2159 tasklet_kill(&pl330->tasks);
2161 /* Free DMAC resources */
2162 dmac_free_resources(pl330);
2165 pi->pl330_data = NULL;
2168 /* forward declaration */
2169 static struct amba_driver pl330_driver;
2171 static inline struct dma_pl330_chan *
2172 to_pchan(struct dma_chan *ch)
2177 return container_of(ch, struct dma_pl330_chan, chan);
2180 static inline struct dma_pl330_desc *
2181 to_desc(struct dma_async_tx_descriptor *tx)
2183 return container_of(tx, struct dma_pl330_desc, txd);
2186 static inline void fill_queue(struct dma_pl330_chan *pch)
2188 struct dma_pl330_desc *desc;
2191 list_for_each_entry(desc, &pch->work_list, node) {
2193 /* If already submitted */
2194 if (desc->status == BUSY)
2197 ret = pl330_submit_req(pch->pl330_chid,
2200 desc->status = BUSY;
2201 } else if (ret == -EAGAIN) {
2202 /* QFull or DMAC Dying */
2205 /* Unacceptable request */
2206 desc->status = DONE;
2207 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2208 __func__, __LINE__, desc->txd.cookie);
2209 tasklet_schedule(&pch->task);
2214 static void pl330_tasklet(unsigned long data)
2216 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2217 struct dma_pl330_desc *desc, *_dt;
2218 unsigned long flags;
2220 spin_lock_irqsave(&pch->lock, flags);
2222 /* Pick up ripe tomatoes */
2223 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2224 if (desc->status == DONE) {
2226 dma_cookie_complete(&desc->txd);
2227 list_move_tail(&desc->node, &pch->completed_list);
2230 /* Try to submit a req imm. next to the last completed cookie */
2233 /* Make sure the PL330 Channel thread is active */
2234 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2236 while (!list_empty(&pch->completed_list)) {
2237 dma_async_tx_callback callback;
2238 void *callback_param;
2240 desc = list_first_entry(&pch->completed_list,
2241 struct dma_pl330_desc, node);
2243 callback = desc->txd.callback;
2244 callback_param = desc->txd.callback_param;
2247 desc->status = PREP;
2248 list_move_tail(&desc->node, &pch->work_list);
2250 desc->status = FREE;
2251 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2254 dma_descriptor_unmap(&desc->txd);
2257 spin_unlock_irqrestore(&pch->lock, flags);
2258 callback(callback_param);
2259 spin_lock_irqsave(&pch->lock, flags);
2262 spin_unlock_irqrestore(&pch->lock, flags);
2265 static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2267 struct dma_pl330_desc *desc = token;
2268 struct dma_pl330_chan *pch = desc->pchan;
2269 unsigned long flags;
2271 /* If desc aborted */
2275 spin_lock_irqsave(&pch->lock, flags);
2277 desc->status = DONE;
2279 spin_unlock_irqrestore(&pch->lock, flags);
2281 tasklet_schedule(&pch->task);
2284 bool pl330_filter(struct dma_chan *chan, void *param)
2288 if (chan->device->dev->driver != &pl330_driver.drv)
2291 peri_id = chan->private;
2292 return *peri_id == (unsigned long)param;
2294 EXPORT_SYMBOL(pl330_filter);
2296 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2297 struct of_dma *ofdma)
2299 int count = dma_spec->args_count;
2300 struct dma_pl330_dmac *pdmac = ofdma->of_dma_data;
2301 unsigned int chan_id;
2306 chan_id = dma_spec->args[0];
2307 if (chan_id >= pdmac->num_peripherals)
2310 return dma_get_slave_channel(&pdmac->peripherals[chan_id].chan);
2313 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2315 struct dma_pl330_chan *pch = to_pchan(chan);
2316 struct dma_pl330_dmac *pdmac = pch->dmac;
2317 unsigned long flags;
2319 spin_lock_irqsave(&pch->lock, flags);
2321 dma_cookie_init(chan);
2322 pch->cyclic = false;
2324 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2325 if (!pch->pl330_chid) {
2326 spin_unlock_irqrestore(&pch->lock, flags);
2330 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2332 spin_unlock_irqrestore(&pch->lock, flags);
2337 static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2339 struct dma_pl330_chan *pch = to_pchan(chan);
2340 struct dma_pl330_desc *desc;
2341 unsigned long flags;
2342 struct dma_pl330_dmac *pdmac = pch->dmac;
2343 struct dma_slave_config *slave_config;
2347 case DMA_TERMINATE_ALL:
2348 spin_lock_irqsave(&pch->lock, flags);
2350 /* FLUSH the PL330 Channel thread */
2351 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2353 /* Mark all desc done */
2354 list_for_each_entry(desc, &pch->submitted_list, node) {
2355 desc->status = FREE;
2356 dma_cookie_complete(&desc->txd);
2359 list_for_each_entry(desc, &pch->work_list , node) {
2360 desc->status = FREE;
2361 dma_cookie_complete(&desc->txd);
2364 list_for_each_entry(desc, &pch->completed_list , node) {
2365 desc->status = FREE;
2366 dma_cookie_complete(&desc->txd);
2369 list_splice_tail_init(&pch->submitted_list, &pdmac->desc_pool);
2370 list_splice_tail_init(&pch->work_list, &pdmac->desc_pool);
2371 list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool);
2372 spin_unlock_irqrestore(&pch->lock, flags);
2374 case DMA_SLAVE_CONFIG:
2375 slave_config = (struct dma_slave_config *)arg;
2377 if (slave_config->direction == DMA_MEM_TO_DEV) {
2378 if (slave_config->dst_addr)
2379 pch->fifo_addr = slave_config->dst_addr;
2380 if (slave_config->dst_addr_width)
2381 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2382 if (slave_config->dst_maxburst)
2383 pch->burst_len = slave_config->dst_maxburst;
2384 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2385 if (slave_config->src_addr)
2386 pch->fifo_addr = slave_config->src_addr;
2387 if (slave_config->src_addr_width)
2388 pch->burst_sz = __ffs(slave_config->src_addr_width);
2389 if (slave_config->src_maxburst)
2390 pch->burst_len = slave_config->src_maxburst;
2394 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
2401 static void pl330_free_chan_resources(struct dma_chan *chan)
2403 struct dma_pl330_chan *pch = to_pchan(chan);
2404 unsigned long flags;
2406 tasklet_kill(&pch->task);
2408 spin_lock_irqsave(&pch->lock, flags);
2410 pl330_release_channel(pch->pl330_chid);
2411 pch->pl330_chid = NULL;
2414 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2416 spin_unlock_irqrestore(&pch->lock, flags);
2419 static enum dma_status
2420 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2421 struct dma_tx_state *txstate)
2423 return dma_cookie_status(chan, cookie, txstate);
2426 static void pl330_issue_pending(struct dma_chan *chan)
2428 struct dma_pl330_chan *pch = to_pchan(chan);
2429 unsigned long flags;
2431 spin_lock_irqsave(&pch->lock, flags);
2432 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2433 spin_unlock_irqrestore(&pch->lock, flags);
2435 pl330_tasklet((unsigned long)pch);
2439 * We returned the last one of the circular list of descriptor(s)
2440 * from prep_xxx, so the argument to submit corresponds to the last
2441 * descriptor of the list.
2443 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2445 struct dma_pl330_desc *desc, *last = to_desc(tx);
2446 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2447 dma_cookie_t cookie;
2448 unsigned long flags;
2450 spin_lock_irqsave(&pch->lock, flags);
2452 /* Assign cookies to all nodes */
2453 while (!list_empty(&last->node)) {
2454 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2456 desc->txd.callback = last->txd.callback;
2457 desc->txd.callback_param = last->txd.callback_param;
2460 dma_cookie_assign(&desc->txd);
2462 list_move_tail(&desc->node, &pch->submitted_list);
2465 cookie = dma_cookie_assign(&last->txd);
2466 list_add_tail(&last->node, &pch->submitted_list);
2467 spin_unlock_irqrestore(&pch->lock, flags);
2472 static inline void _init_desc(struct dma_pl330_desc *desc)
2474 desc->req.x = &desc->px;
2475 desc->req.token = desc;
2476 desc->rqcfg.swap = SWAP_NO;
2477 desc->rqcfg.scctl = CCTRL0;
2478 desc->rqcfg.dcctl = CCTRL0;
2479 desc->req.cfg = &desc->rqcfg;
2480 desc->req.xfer_cb = dma_pl330_rqcb;
2481 desc->txd.tx_submit = pl330_tx_submit;
2483 INIT_LIST_HEAD(&desc->node);
2486 /* Returns the number of descriptors added to the DMAC pool */
2487 static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
2489 struct dma_pl330_desc *desc;
2490 unsigned long flags;
2496 desc = kcalloc(count, sizeof(*desc), flg);
2500 spin_lock_irqsave(&pdmac->pool_lock, flags);
2502 for (i = 0; i < count; i++) {
2503 _init_desc(&desc[i]);
2504 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2507 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2512 static struct dma_pl330_desc *
2513 pluck_desc(struct dma_pl330_dmac *pdmac)
2515 struct dma_pl330_desc *desc = NULL;
2516 unsigned long flags;
2521 spin_lock_irqsave(&pdmac->pool_lock, flags);
2523 if (!list_empty(&pdmac->desc_pool)) {
2524 desc = list_entry(pdmac->desc_pool.next,
2525 struct dma_pl330_desc, node);
2527 list_del_init(&desc->node);
2529 desc->status = PREP;
2530 desc->txd.callback = NULL;
2533 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2538 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2540 struct dma_pl330_dmac *pdmac = pch->dmac;
2541 u8 *peri_id = pch->chan.private;
2542 struct dma_pl330_desc *desc;
2544 /* Pluck one desc from the pool of DMAC */
2545 desc = pluck_desc(pdmac);
2547 /* If the DMAC pool is empty, alloc new */
2549 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2553 desc = pluck_desc(pdmac);
2555 dev_err(pch->dmac->pif.dev,
2556 "%s:%d ALERT!\n", __func__, __LINE__);
2561 /* Initialize the descriptor */
2563 desc->txd.cookie = 0;
2564 async_tx_ack(&desc->txd);
2566 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
2567 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
2569 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2574 static inline void fill_px(struct pl330_xfer *px,
2575 dma_addr_t dst, dma_addr_t src, size_t len)
2583 static struct dma_pl330_desc *
2584 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2585 dma_addr_t src, size_t len)
2587 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2590 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2591 __func__, __LINE__);
2596 * Ideally we should lookout for reqs bigger than
2597 * those that can be programmed with 256 bytes of
2598 * MC buffer, but considering a req size is seldom
2599 * going to be word-unaligned and more than 200MB,
2601 * Also, should the limit is reached we'd rather
2602 * have the platform increase MC buffer size than
2603 * complicating this API driver.
2605 fill_px(&desc->px, dst, src, len);
2610 /* Call after fixing burst size */
2611 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2613 struct dma_pl330_chan *pch = desc->pchan;
2614 struct pl330_info *pi = &pch->dmac->pif;
2617 burst_len = pi->pcfg.data_bus_width / 8;
2618 burst_len *= pi->pcfg.data_buf_dep;
2619 burst_len >>= desc->rqcfg.brst_size;
2621 /* src/dst_burst_len can't be more than 16 */
2625 while (burst_len > 1) {
2626 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2634 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2635 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2636 size_t period_len, enum dma_transfer_direction direction,
2637 unsigned long flags, void *context)
2639 struct dma_pl330_desc *desc = NULL, *first = NULL;
2640 struct dma_pl330_chan *pch = to_pchan(chan);
2641 struct dma_pl330_dmac *pdmac = pch->dmac;
2646 if (len % period_len != 0)
2649 if (!is_slave_direction(direction)) {
2650 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2651 __func__, __LINE__);
2655 for (i = 0; i < len / period_len; i++) {
2656 desc = pl330_get_desc(pch);
2658 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2659 __func__, __LINE__);
2664 spin_lock_irqsave(&pdmac->pool_lock, flags);
2666 while (!list_empty(&first->node)) {
2667 desc = list_entry(first->node.next,
2668 struct dma_pl330_desc, node);
2669 list_move_tail(&desc->node, &pdmac->desc_pool);
2672 list_move_tail(&first->node, &pdmac->desc_pool);
2674 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2679 switch (direction) {
2680 case DMA_MEM_TO_DEV:
2681 desc->rqcfg.src_inc = 1;
2682 desc->rqcfg.dst_inc = 0;
2684 dst = pch->fifo_addr;
2686 case DMA_DEV_TO_MEM:
2687 desc->rqcfg.src_inc = 0;
2688 desc->rqcfg.dst_inc = 1;
2689 src = pch->fifo_addr;
2696 desc->req.rqtype = direction;
2697 desc->rqcfg.brst_size = pch->burst_sz;
2698 desc->rqcfg.brst_len = 1;
2699 fill_px(&desc->px, dst, src, period_len);
2704 list_add_tail(&desc->node, &first->node);
2706 dma_addr += period_len;
2713 desc->txd.flags = flags;
2718 static struct dma_async_tx_descriptor *
2719 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2720 dma_addr_t src, size_t len, unsigned long flags)
2722 struct dma_pl330_desc *desc;
2723 struct dma_pl330_chan *pch = to_pchan(chan);
2724 struct pl330_info *pi;
2727 if (unlikely(!pch || !len))
2730 pi = &pch->dmac->pif;
2732 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2736 desc->rqcfg.src_inc = 1;
2737 desc->rqcfg.dst_inc = 1;
2738 desc->req.rqtype = DMA_MEM_TO_MEM;
2740 /* Select max possible burst size */
2741 burst = pi->pcfg.data_bus_width / 8;
2749 desc->rqcfg.brst_size = 0;
2750 while (burst != (1 << desc->rqcfg.brst_size))
2751 desc->rqcfg.brst_size++;
2753 desc->rqcfg.brst_len = get_burst_len(desc, len);
2755 desc->txd.flags = flags;
2760 static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac,
2761 struct dma_pl330_desc *first)
2763 unsigned long flags;
2764 struct dma_pl330_desc *desc;
2769 spin_lock_irqsave(&pdmac->pool_lock, flags);
2771 while (!list_empty(&first->node)) {
2772 desc = list_entry(first->node.next,
2773 struct dma_pl330_desc, node);
2774 list_move_tail(&desc->node, &pdmac->desc_pool);
2777 list_move_tail(&first->node, &pdmac->desc_pool);
2779 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2782 static struct dma_async_tx_descriptor *
2783 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2784 unsigned int sg_len, enum dma_transfer_direction direction,
2785 unsigned long flg, void *context)
2787 struct dma_pl330_desc *first, *desc = NULL;
2788 struct dma_pl330_chan *pch = to_pchan(chan);
2789 struct scatterlist *sg;
2793 if (unlikely(!pch || !sgl || !sg_len))
2796 addr = pch->fifo_addr;
2800 for_each_sg(sgl, sg, sg_len, i) {
2802 desc = pl330_get_desc(pch);
2804 struct dma_pl330_dmac *pdmac = pch->dmac;
2806 dev_err(pch->dmac->pif.dev,
2807 "%s:%d Unable to fetch desc\n",
2808 __func__, __LINE__);
2809 __pl330_giveback_desc(pdmac, first);
2817 list_add_tail(&desc->node, &first->node);
2819 if (direction == DMA_MEM_TO_DEV) {
2820 desc->rqcfg.src_inc = 1;
2821 desc->rqcfg.dst_inc = 0;
2823 addr, sg_dma_address(sg), sg_dma_len(sg));
2825 desc->rqcfg.src_inc = 0;
2826 desc->rqcfg.dst_inc = 1;
2828 sg_dma_address(sg), addr, sg_dma_len(sg));
2831 desc->rqcfg.brst_size = pch->burst_sz;
2832 desc->rqcfg.brst_len = 1;
2833 desc->req.rqtype = direction;
2836 /* Return the last desc in the chain */
2837 desc->txd.flags = flg;
2841 static irqreturn_t pl330_irq_handler(int irq, void *data)
2843 if (pl330_update(data))
2849 #define PL330_DMA_BUSWIDTHS \
2850 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2851 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2852 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2853 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2854 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2856 static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2857 struct dma_slave_caps *caps)
2859 caps->src_addr_widths = PL330_DMA_BUSWIDTHS;
2860 caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS;
2861 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2862 caps->cmd_pause = false;
2863 caps->cmd_terminate = true;
2864 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
2870 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2872 struct dma_pl330_platdata *pdat;
2873 struct dma_pl330_dmac *pdmac;
2874 struct dma_pl330_chan *pch, *_p;
2875 struct pl330_info *pi;
2876 struct dma_device *pd;
2877 struct resource *res;
2881 pdat = dev_get_platdata(&adev->dev);
2883 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2887 /* Allocate a new DMAC and its Channels */
2888 pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL);
2890 dev_err(&adev->dev, "unable to allocate mem\n");
2895 pi->dev = &adev->dev;
2896 pi->pl330_data = NULL;
2897 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2900 pi->base = devm_ioremap_resource(&adev->dev, res);
2901 if (IS_ERR(pi->base))
2902 return PTR_ERR(pi->base);
2904 amba_set_drvdata(adev, pdmac);
2906 for (i = 0; i < AMBA_NR_IRQS; i++) {
2909 ret = devm_request_irq(&adev->dev, irq,
2910 pl330_irq_handler, 0,
2911 dev_name(&adev->dev), pi);
2919 pi->pcfg.periph_id = adev->periphid;
2920 ret = pl330_add(pi);
2924 INIT_LIST_HEAD(&pdmac->desc_pool);
2925 spin_lock_init(&pdmac->pool_lock);
2927 /* Create a descriptor pool of default size */
2928 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
2929 dev_warn(&adev->dev, "unable to allocate desc\n");
2932 INIT_LIST_HEAD(&pd->channels);
2934 /* Initialize channel parameters */
2936 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
2938 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
2940 pdmac->num_peripherals = num_chan;
2942 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2943 if (!pdmac->peripherals) {
2945 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
2949 for (i = 0; i < num_chan; i++) {
2950 pch = &pdmac->peripherals[i];
2951 if (!adev->dev.of_node)
2952 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2954 pch->chan.private = adev->dev.of_node;
2956 INIT_LIST_HEAD(&pch->submitted_list);
2957 INIT_LIST_HEAD(&pch->work_list);
2958 INIT_LIST_HEAD(&pch->completed_list);
2959 spin_lock_init(&pch->lock);
2960 pch->pl330_chid = NULL;
2961 pch->chan.device = pd;
2964 /* Add the channel to the DMAC list */
2965 list_add_tail(&pch->chan.device_node, &pd->channels);
2968 pd->dev = &adev->dev;
2970 pd->cap_mask = pdat->cap_mask;
2972 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2973 if (pi->pcfg.num_peri) {
2974 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2975 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2976 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2980 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2981 pd->device_free_chan_resources = pl330_free_chan_resources;
2982 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2983 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2984 pd->device_tx_status = pl330_tx_status;
2985 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2986 pd->device_control = pl330_control;
2987 pd->device_issue_pending = pl330_issue_pending;
2988 pd->device_slave_caps = pl330_dma_device_slave_caps;
2990 ret = dma_async_device_register(pd);
2992 dev_err(&adev->dev, "unable to register DMAC\n");
2996 if (adev->dev.of_node) {
2997 ret = of_dma_controller_register(adev->dev.of_node,
2998 of_dma_pl330_xlate, pdmac);
3001 "unable to register DMA to the generic DT DMA helpers\n");
3005 adev->dev.dma_parms = &pdmac->dma_parms;
3008 * This is the limit for transfers with a buswidth of 1, larger
3009 * buswidths will have larger limits.
3011 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3013 dev_err(&adev->dev, "unable to set the seg size\n");
3016 dev_info(&adev->dev,
3017 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
3018 dev_info(&adev->dev,
3019 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3020 pi->pcfg.data_buf_dep,
3021 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
3022 pi->pcfg.num_peri, pi->pcfg.num_events);
3027 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3030 /* Remove the channel */
3031 list_del(&pch->chan.device_node);
3033 /* Flush the channel */
3034 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3035 pl330_free_chan_resources(&pch->chan);
3043 static int pl330_remove(struct amba_device *adev)
3045 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
3046 struct dma_pl330_chan *pch, *_p;
3047 struct pl330_info *pi;
3052 if (adev->dev.of_node)
3053 of_dma_controller_free(adev->dev.of_node);
3055 dma_async_device_unregister(&pdmac->ddma);
3058 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3061 /* Remove the channel */
3062 list_del(&pch->chan.device_node);
3064 /* Flush the channel */
3065 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3066 pl330_free_chan_resources(&pch->chan);
3076 static struct amba_id pl330_ids[] = {
3084 MODULE_DEVICE_TABLE(amba, pl330_ids);
3086 static struct amba_driver pl330_driver = {
3088 .owner = THIS_MODULE,
3089 .name = "dma-pl330",
3091 .id_table = pl330_ids,
3092 .probe = pl330_probe,
3093 .remove = pl330_remove,
3096 module_amba_driver(pl330_driver);
3098 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3099 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3100 MODULE_LICENSE("GPL");