drivers/dma/pxa_dma.c

   1 /*
   2  * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/module.h>
  11 #include <linux/init.h>
  12 #include <linux/types.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/slab.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_data/mmp_dma.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/of.h>
  24 #include <linux/dma/pxa-dma.h>
  25
  26 #include "dmaengine.h"
  27 #include "virt-dma.h"
  28
  29 #define DCSR(n)         (0x0000 + ((n) << 2))
  30 #define DALGN(n)        0x00a0
  31 #define DINT            0x00f0
  32 #define DDADR(n)        (0x0200 + ((n) << 4))
  33 #define DSADR(n)        (0x0204 + ((n) << 4))
  34 #define DTADR(n)        (0x0208 + ((n) << 4))
  35 #define DCMD(n)         (0x020c + ((n) << 4))
  36
  37 #define PXA_DCSR_RUN            BIT(31) /* Run Bit (read / write) */
  38 #define PXA_DCSR_NODESC         BIT(30) /* No-Descriptor Fetch (read / write) */
  39 #define PXA_DCSR_STOPIRQEN      BIT(29) /* Stop Interrupt Enable (R/W) */
  40 #define PXA_DCSR_REQPEND        BIT(8)  /* Request Pending (read-only) */
  41 #define PXA_DCSR_STOPSTATE      BIT(3)  /* Stop State (read-only) */
  42 #define PXA_DCSR_ENDINTR        BIT(2)  /* End Interrupt (read / write) */
  43 #define PXA_DCSR_STARTINTR      BIT(1)  /* Start Interrupt (read / write) */
  44 #define PXA_DCSR_BUSERR         BIT(0)  /* Bus Error Interrupt (read / write) */
  45
  46 #define PXA_DCSR_EORIRQEN       BIT(28) /* End of Receive IRQ Enable (R/W) */
  47 #define PXA_DCSR_EORJMPEN       BIT(27) /* Jump to next descriptor on EOR */
  48 #define PXA_DCSR_EORSTOPEN      BIT(26) /* STOP on an EOR */
  49 #define PXA_DCSR_SETCMPST       BIT(25) /* Set Descriptor Compare Status */
  50 #define PXA_DCSR_CLRCMPST       BIT(24) /* Clear Descriptor Compare Status */
  51 #define PXA_DCSR_CMPST          BIT(10) /* The Descriptor Compare Status */
  52 #define PXA_DCSR_EORINTR        BIT(9)  /* The end of Receive */
  53
  54 #define DRCMR_MAPVLD    BIT(7)  /* Map Valid (read / write) */
  55 #define DRCMR_CHLNUM    0x1f    /* mask for Channel Number (read / write) */
  56
  57 #define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
  58 #define DDADR_STOP      BIT(0)  /* Stop (read / write) */
  59
  60 #define PXA_DCMD_INCSRCADDR     BIT(31) /* Source Address Increment Setting. */
  61 #define PXA_DCMD_INCTRGADDR     BIT(30) /* Target Address Increment Setting. */
  62 #define PXA_DCMD_FLOWSRC        BIT(29) /* Flow Control by the source. */
  63 #define PXA_DCMD_FLOWTRG        BIT(28) /* Flow Control by the target. */
  64 #define PXA_DCMD_STARTIRQEN     BIT(22) /* Start Interrupt Enable */
  65 #define PXA_DCMD_ENDIRQEN       BIT(21) /* End Interrupt Enable */
  66 #define PXA_DCMD_ENDIAN         BIT(18) /* Device Endian-ness. */
  67 #define PXA_DCMD_BURST8         (1 << 16)       /* 8 byte burst */
  68 #define PXA_DCMD_BURST16        (2 << 16)       /* 16 byte burst */
  69 #define PXA_DCMD_BURST32        (3 << 16)       /* 32 byte burst */
  70 #define PXA_DCMD_WIDTH1         (1 << 14)       /* 1 byte width */
  71 #define PXA_DCMD_WIDTH2         (2 << 14)       /* 2 byte width (HalfWord) */
  72 #define PXA_DCMD_WIDTH4         (3 << 14)       /* 4 byte width (Word) */
  73 #define PXA_DCMD_LENGTH         0x01fff         /* length mask (max = 8K - 1) */
  74
  75 #define PDMA_ALIGNMENT          3
  76 #define PDMA_MAX_DESC_BYTES     (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
  77
  78 struct pxad_desc_hw {
  79         u32 ddadr;      /* Points to the next descriptor + flags */
  80         u32 dsadr;      /* DSADR value for the current transfer */
  81         u32 dtadr;      /* DTADR value for the current transfer */
  82         u32 dcmd;       /* DCMD value for the current transfer */
  83 } __aligned(16);
  84
  85 struct pxad_desc_sw {
  86         struct virt_dma_desc    vd;             /* Virtual descriptor */
  87         int                     nb_desc;        /* Number of hw. descriptors */
  88         size_t                  len;            /* Number of bytes xfered */
  89         dma_addr_t              first;          /* First descriptor's addr */
  90
  91         /* At least one descriptor has an src/dst address not multiple of 8 */
  92         bool                    misaligned;
  93         bool                    cyclic;
  94         struct dma_pool         *desc_pool;     /* Channel's used allocator */
  95
  96         struct pxad_desc_hw     *hw_desc[];     /* DMA coherent descriptors */
  97 };
  98
  99 struct pxad_phy {
 100         int                     idx;
 101         void __iomem            *base;
 102         struct pxad_chan        *vchan;
 103 };
 104
 105 struct pxad_chan {
 106         struct virt_dma_chan    vc;             /* Virtual channel */
 107         u32                     drcmr;          /* Requestor of the channel */
 108         enum pxad_chan_prio     prio;           /* Required priority of phy */
 109         /*
 110          * At least one desc_sw in submitted or issued transfers on this channel
 111          * has one address such as: addr % 8 != 0. This implies the DALGN
 112          * setting on the phy.
 113          */
 114         bool                    misaligned;
 115         struct dma_slave_config cfg;            /* Runtime config */
 116
 117         /* protected by vc->lock */
 118         struct pxad_phy         *phy;
 119         struct dma_pool         *desc_pool;     /* Descriptors pool */
 120 };
 121
 122 struct pxad_device {
 123         struct dma_device               slave;
 124         int                             nr_chans;
 125         void __iomem                    *base;
 126         struct pxad_phy                 *phys;
 127         spinlock_t                      phy_lock;       /* Phy association */
 128 #ifdef CONFIG_DEBUG_FS
 129         struct dentry                   *dbgfs_root;
 130         struct dentry                   *dbgfs_state;
 131         struct dentry                   **dbgfs_chan;
 132 #endif
 133 };
 134
 135 #define tx_to_pxad_desc(tx)                                     \
 136         container_of(tx, struct pxad_desc_sw, async_tx)
 137 #define to_pxad_chan(dchan)                                     \
 138         container_of(dchan, struct pxad_chan, vc.chan)
 139 #define to_pxad_dev(dmadev)                                     \
 140         container_of(dmadev, struct pxad_device, slave)
 141 #define to_pxad_sw_desc(_vd)                            \
 142         container_of((_vd), struct pxad_desc_sw, vd)
 143
 144 #define _phy_readl_relaxed(phy, _reg)                                   \
 145         readl_relaxed((phy)->base + _reg((phy)->idx))
 146 #define phy_readl_relaxed(phy, _reg)                                    \
 147         ({                                                              \
 148                 u32 _v;                                                 \
 149                 _v = readl_relaxed((phy)->base + _reg((phy)->idx));     \
 150                 dev_vdbg(&phy->vchan->vc.chan.dev->device,              \
 151                          "%s(): readl(%s): 0x%08x\n", __func__, #_reg,  \
 152                           _v);                                          \
 153                 _v;                                                     \
 154         })
 155 #define phy_writel(phy, val, _reg)                                      \
 156         do {                                                            \
 157                 writel((val), (phy)->base + _reg((phy)->idx));          \
 158                 dev_vdbg(&phy->vchan->vc.chan.dev->device,              \
 159                          "%s(): writel(0x%08x, %s)\n",                  \
 160                          __func__, (u32)(val), #_reg);                  \
 161         } while (0)
 162 #define phy_writel_relaxed(phy, val, _reg)                              \
 163         do {                                                            \
 164                 writel_relaxed((val), (phy)->base + _reg((phy)->idx));  \
 165                 dev_vdbg(&phy->vchan->vc.chan.dev->device,              \
 166                          "%s(): writel_relaxed(0x%08x, %s)\n",          \
 167                          __func__, (u32)(val), #_reg);                  \
 168         } while (0)
 169
 170 static unsigned int pxad_drcmr(unsigned int line)
 171 {
 172         if (line < 64)
 173                 return 0x100 + line * 4;
 174         return 0x1000 + line * 4;
 175 }
 176
 177 /*
 178  * Debug fs
 179  */
 180 #ifdef CONFIG_DEBUG_FS
 181 #include <linux/debugfs.h>
 182 #include <linux/uaccess.h>
 183 #include <linux/seq_file.h>
 184
 185 static int dbg_show_requester_chan(struct seq_file *s, void *p)
 186 {
 187         int pos = 0;
 188         struct pxad_phy *phy = s->private;
 189         int i;
 190         u32 drcmr;
 191
 192         pos += seq_printf(s, "DMA channel %d requester :\n", phy->idx);
 193         for (i = 0; i < 70; i++) {
 194                 drcmr = readl_relaxed(phy->base + pxad_drcmr(i));
 195                 if ((drcmr & DRCMR_CHLNUM) == phy->idx)
 196                         pos += seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
 197                                           !!(drcmr & DRCMR_MAPVLD));
 198         }
 199         return pos;
 200 }
 201
 202 static inline int dbg_burst_from_dcmd(u32 dcmd)
 203 {
 204         int burst = (dcmd >> 16) & 0x3;
 205
 206         return burst ? 4 << burst : 0;
 207 }
 208
 209 static int is_phys_valid(unsigned long addr)
 210 {
 211         return pfn_valid(__phys_to_pfn(addr));
 212 }
 213
 214 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")
 215 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")
 216
 217 static int dbg_show_descriptors(struct seq_file *s, void *p)
 218 {
 219         struct pxad_phy *phy = s->private;
 220         int i, max_show = 20, burst, width;
 221         u32 dcmd;
 222         unsigned long phys_desc, ddadr;
 223         struct pxad_desc_hw *desc;
 224
 225         phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);
 226
 227         seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);
 228         seq_printf(s, "[%03d] First descriptor unknown\n", 0);
 229         for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
 230                 desc = phys_to_virt(phys_desc);
 231                 dcmd = desc->dcmd;
 232                 burst = dbg_burst_from_dcmd(dcmd);
 233                 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
 234
 235                 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
 236                            i, phys_desc, desc);
 237                 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
 238                 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
 239                 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
 240                 seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
 241                            dcmd,
 242                            PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
 243                            PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
 244                            PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
 245                            PXA_DCMD_STR(ENDIAN), burst, width,
 246                            dcmd & PXA_DCMD_LENGTH);
 247                 phys_desc = desc->ddadr;
 248         }
 249         if (i == max_show)
 250                 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
 251                            i, phys_desc);
 252         else
 253                 seq_printf(s, "[%03d] Desc at %08lx is %s\n",
 254                            i, phys_desc, phys_desc == DDADR_STOP ?
 255                            "DDADR_STOP" : "invalid");
 256
 257         return 0;
 258 }
 259
 260 static int dbg_show_chan_state(struct seq_file *s, void *p)
 261 {
 262         struct pxad_phy *phy = s->private;
 263         u32 dcsr, dcmd;
 264         int burst, width;
 265         static const char * const str_prio[] = {
 266                 "high", "normal", "low", "invalid"
 267         };
 268
 269         dcsr = _phy_readl_relaxed(phy, DCSR);
 270         dcmd = _phy_readl_relaxed(phy, DCMD);
 271         burst = dbg_burst_from_dcmd(dcmd);
 272         width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
 273
 274         seq_printf(s, "DMA channel %d\n", phy->idx);
 275         seq_printf(s, "\tPriority : %s\n",
 276                           str_prio[(phy->idx & 0xf) / 4]);
 277         seq_printf(s, "\tUnaligned transfer bit: %s\n",
 278                           _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
 279                           "yes" : "no");
 280         seq_printf(s, "\tDCSR  = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
 281                    dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
 282                    PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
 283                    PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),
 284                    PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),
 285                    PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),
 286                    PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),
 287                    PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),
 288                    PXA_DCSR_STR(BUSERR));
 289
 290         seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
 291                    dcmd,
 292                    PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
 293                    PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
 294                    PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
 295                    PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);
 296         seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));
 297         seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));
 298         seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));
 299
 300         return 0;
 301 }
 302
 303 static int dbg_show_state(struct seq_file *s, void *p)
 304 {
 305         struct pxad_device *pdev = s->private;
 306
 307         /* basic device status */
 308         seq_puts(s, "DMA engine status\n");
 309         seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);
 310
 311         return 0;
 312 }
 313
 314 #define DBGFS_FUNC_DECL(name) \
 315 static int dbg_open_##name(struct inode *inode, struct file *file) \
 316 { \
 317         return single_open(file, dbg_show_##name, inode->i_private); \
 318 } \
 319 static const struct file_operations dbg_fops_##name = { \
 320         .owner          = THIS_MODULE, \
 321         .open           = dbg_open_##name, \
 322         .llseek         = seq_lseek, \
 323         .read           = seq_read, \
 324         .release        = single_release, \
 325 }
 326
 327 DBGFS_FUNC_DECL(state);
 328 DBGFS_FUNC_DECL(chan_state);
 329 DBGFS_FUNC_DECL(descriptors);
 330 DBGFS_FUNC_DECL(requester_chan);
 331
 332 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev,
 333                                              int ch, struct dentry *chandir)
 334 {
 335         char chan_name[11];
 336         struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
 337         struct dentry *chan_reqs = NULL;
 338         void *dt;
 339
 340         scnprintf(chan_name, sizeof(chan_name), "%d", ch);
 341         chan = debugfs_create_dir(chan_name, chandir);
 342         dt = (void *)&pdev->phys[ch];
 343
 344         if (chan)
 345                 chan_state = debugfs_create_file("state", 0400, chan, dt,
 346                                                  &dbg_fops_chan_state);
 347         if (chan_state)
 348                 chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
 349                                                  &dbg_fops_descriptors);
 350         if (chan_descr)
 351                 chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
 352                                                 &dbg_fops_requester_chan);
 353         if (!chan_reqs)
 354                 goto err_state;
 355
 356         return chan;
 357
 358 err_state:
 359         debugfs_remove_recursive(chan);
 360         return NULL;
 361 }
 362
 363 static void pxad_init_debugfs(struct pxad_device *pdev)
 364 {
 365         int i;
 366         struct dentry *chandir;
 367
 368         pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);
 369         if (IS_ERR(pdev->dbgfs_root) || !pdev->dbgfs_root)
 370                 goto err_root;
 371
 372         pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root,
 373                                                 pdev, &dbg_fops_state);
 374         if (!pdev->dbgfs_state)
 375                 goto err_state;
 376
 377         pdev->dbgfs_chan =
 378                 kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state),
 379                               GFP_KERNEL);
 380         if (!pdev->dbgfs_chan)
 381                 goto err_alloc;
 382
 383         chandir = debugfs_create_dir("channels", pdev->dbgfs_root);
 384         if (!chandir)
 385                 goto err_chandir;
 386
 387         for (i = 0; i < pdev->nr_chans; i++) {
 388                 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);
 389                 if (!pdev->dbgfs_chan[i])
 390                         goto err_chans;
 391         }
 392
 393         return;
 394 err_chans:
 395 err_chandir:
 396         kfree(pdev->dbgfs_chan);
 397 err_alloc:
 398 err_state:
 399         debugfs_remove_recursive(pdev->dbgfs_root);
 400 err_root:
 401         pr_err("pxad: debugfs is not available\n");
 402 }
 403
 404 static void pxad_cleanup_debugfs(struct pxad_device *pdev)
 405 {
 406         debugfs_remove_recursive(pdev->dbgfs_root);
 407 }
 408 #else
 409 static inline void pxad_init_debugfs(struct pxad_device *pdev) {}
 410 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}
 411 #endif
 412
 413 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan)
 414 {
 415         int prio, i;
 416         struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);
 417         struct pxad_phy *phy, *found = NULL;
 418         unsigned long flags;
 419
 420         /*
 421          * dma channel priorities
 422          * ch 0 - 3,  16 - 19  <--> (0)
 423          * ch 4 - 7,  20 - 23  <--> (1)
 424          * ch 8 - 11, 24 - 27  <--> (2)
 425          * ch 12 - 15, 28 - 31  <--> (3)
 426          */
 427
 428         spin_lock_irqsave(&pdev->phy_lock, flags);
 429         for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {
 430                 for (i = 0; i < pdev->nr_chans; i++) {
 431                         if (prio != (i & 0xf) >> 2)
 432                                 continue;
 433                         phy = &pdev->phys[i];
 434                         if (!phy->vchan) {
 435                                 phy->vchan = pchan;
 436                                 found = phy;
 437                                 goto out_unlock;
 438                         }
 439                 }
 440         }
 441
 442 out_unlock:
 443         spin_unlock_irqrestore(&pdev->phy_lock, flags);
 444         dev_dbg(&pchan->vc.chan.dev->device,
 445                 "%s(): phy=%p(%d)\n", __func__, found,
 446                 found ? found->idx : -1);
 447
 448         return found;
 449 }
 450
 451 static void pxad_free_phy(struct pxad_chan *chan)
 452 {
 453         struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
 454         unsigned long flags;
 455         u32 reg;
 456
 457         dev_dbg(&chan->vc.chan.dev->device,
 458                 "%s(): freeing\n", __func__);
 459         if (!chan->phy)
 460                 return;
 461
 462         /* clear the channel mapping in DRCMR */
 463         reg = pxad_drcmr(chan->drcmr);
 464         writel_relaxed(0, chan->phy->base + reg);
 465
 466         spin_lock_irqsave(&pdev->phy_lock, flags);
 467         chan->phy->vchan = NULL;
 468         chan->phy = NULL;
 469         spin_unlock_irqrestore(&pdev->phy_lock, flags);
 470 }
 471
 472 static bool is_chan_running(struct pxad_chan *chan)
 473 {
 474         u32 dcsr;
 475         struct pxad_phy *phy = chan->phy;
 476
 477         if (!phy)
 478                 return false;
 479         dcsr = phy_readl_relaxed(phy, DCSR);
 480         return dcsr & PXA_DCSR_RUN;
 481 }
 482
 483 static bool is_running_chan_misaligned(struct pxad_chan *chan)
 484 {
 485         u32 dalgn;
 486
 487         BUG_ON(!chan->phy);
 488         dalgn = phy_readl_relaxed(chan->phy, DALGN);
 489         return dalgn & (BIT(chan->phy->idx));
 490 }
 491
 492 static void phy_enable(struct pxad_phy *phy, bool misaligned)
 493 {
 494         u32 reg, dalgn;
 495
 496         if (!phy->vchan)
 497                 return;
 498
 499         dev_dbg(&phy->vchan->vc.chan.dev->device,
 500                 "%s(); phy=%p(%d) misaligned=%d\n", __func__,
 501                 phy, phy->idx, misaligned);
 502
 503         reg = pxad_drcmr(phy->vchan->drcmr);
 504         writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
 505
 506         dalgn = phy_readl_relaxed(phy, DALGN);
 507         if (misaligned)
 508                 dalgn |= BIT(phy->idx);
 509         else
 510                 dalgn &= ~BIT(phy->idx);
 511         phy_writel_relaxed(phy, dalgn, DALGN);
 512
 513         phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR |
 514                    PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR);
 515 }
 516
 517 static void phy_disable(struct pxad_phy *phy)
 518 {
 519         u32 dcsr;
 520
 521         if (!phy)
 522                 return;
 523
 524         dcsr = phy_readl_relaxed(phy, DCSR);
 525         dev_dbg(&phy->vchan->vc.chan.dev->device,
 526                 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx);
 527         phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR);
 528 }
 529
 530 static void pxad_launch_chan(struct pxad_chan *chan,
 531                                  struct pxad_desc_sw *desc)
 532 {
 533         dev_dbg(&chan->vc.chan.dev->device,
 534                 "%s(): desc=%p\n", __func__, desc);
 535         if (!chan->phy) {
 536                 chan->phy = lookup_phy(chan);
 537                 if (!chan->phy) {
 538                         dev_dbg(&chan->vc.chan.dev->device,
 539                                 "%s(): no free dma channel\n", __func__);
 540                         return;
 541                 }
 542         }
 543
 544         /*
 545          * Program the descriptor's address into the DMA controller,
 546          * then start the DMA transaction
 547          */
 548         phy_writel(chan->phy, desc->first, DDADR);
 549         phy_enable(chan->phy, chan->misaligned);
 550 }
 551
 552 static void set_updater_desc(struct pxad_desc_sw *sw_desc,
 553                              unsigned long flags)
 554 {
 555         struct pxad_desc_hw *updater =
 556                 sw_desc->hw_desc[sw_desc->nb_desc - 1];
 557         dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;
 558
 559         updater->ddadr = DDADR_STOP;
 560         updater->dsadr = dma;
 561         updater->dtadr = dma + 8;
 562         updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |
 563                 (PXA_DCMD_LENGTH & sizeof(u32));
 564         if (flags & DMA_PREP_INTERRUPT)
 565                 updater->dcmd |= PXA_DCMD_ENDIRQEN;
 566 }
 567
 568 static bool is_desc_completed(struct virt_dma_desc *vd)
 569 {
 570         struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
 571         struct pxad_desc_hw *updater =
 572                 sw_desc->hw_desc[sw_desc->nb_desc - 1];
 573
 574         return updater->dtadr != (updater->dsadr + 8);
 575 }
 576
 577 static void pxad_desc_chain(struct virt_dma_desc *vd1,
 578                                 struct virt_dma_desc *vd2)
 579 {
 580         struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1);
 581         struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2);
 582         dma_addr_t dma_to_chain;
 583
 584         dma_to_chain = desc2->first;
 585         desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;
 586 }
 587
 588 static bool pxad_try_hotchain(struct virt_dma_chan *vc,
 589                                   struct virt_dma_desc *vd)
 590 {
 591         struct virt_dma_desc *vd_last_issued = NULL;
 592         struct pxad_chan *chan = to_pxad_chan(&vc->chan);
 593
 594         /*
 595          * Attempt to hot chain the tx if the phy is still running. This is
 596          * considered successful only if either the channel is still running
 597          * after the chaining, or if the chained transfer is completed after
 598          * having been hot chained.
 599          * A change of alignment is not allowed, and forbids hotchaining.
 600          */
 601         if (is_chan_running(chan)) {
 602                 BUG_ON(list_empty(&vc->desc_issued));
 603
 604                 if (!is_running_chan_misaligned(chan) &&
 605                     to_pxad_sw_desc(vd)->misaligned)
 606                         return false;
 607
 608                 vd_last_issued = list_entry(vc->desc_issued.prev,
 609                                             struct virt_dma_desc, node);
 610                 pxad_desc_chain(vd_last_issued, vd);
 611                 if (is_chan_running(chan) || is_desc_completed(vd_last_issued))
 612                         return true;
 613         }
 614
 615         return false;
 616 }
 617
 618 static unsigned int clear_chan_irq(struct pxad_phy *phy)
 619 {
 620         u32 dcsr;
 621         u32 dint = readl(phy->base + DINT);
 622
 623         if (!(dint & BIT(phy->idx)))
 624                 return PXA_DCSR_RUN;
 625
 626         /* clear irq */
 627         dcsr = phy_readl_relaxed(phy, DCSR);
 628         phy_writel(phy, dcsr, DCSR);
 629         if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))
 630                 dev_warn(&phy->vchan->vc.chan.dev->device,
 631                          "%s(chan=%p): PXA_DCSR_BUSERR\n",
 632                          __func__, &phy->vchan);
 633
 634         return dcsr & ~PXA_DCSR_RUN;
 635 }
 636
 637 static irqreturn_t pxad_chan_handler(int irq, void *dev_id)
 638 {
 639         struct pxad_phy *phy = dev_id;
 640         struct pxad_chan *chan = phy->vchan;
 641         struct virt_dma_desc *vd, *tmp;
 642         unsigned int dcsr;
 643         unsigned long flags;
 644
 645         BUG_ON(!chan);
 646
 647         dcsr = clear_chan_irq(phy);
 648         if (dcsr & PXA_DCSR_RUN)
 649                 return IRQ_NONE;
 650
 651         spin_lock_irqsave(&chan->vc.lock, flags);
 652         list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {
 653                 dev_dbg(&chan->vc.chan.dev->device,
 654                         "%s(): checking txd %p[%x]: completed=%d\n",
 655                         __func__, vd, vd->tx.cookie, is_desc_completed(vd));
 656                 if (is_desc_completed(vd)) {
 657                         list_del(&vd->node);
 658                         vchan_cookie_complete(vd);
 659                 } else {
 660                         break;
 661                 }
 662         }
 663
 664         if (dcsr & PXA_DCSR_STOPSTATE) {
 665                 dev_dbg(&chan->vc.chan.dev->device,
 666                 "%s(): channel stopped, submitted_empty=%d issued_empty=%d",
 667                         __func__,
 668                         list_empty(&chan->vc.desc_submitted),
 669                         list_empty(&chan->vc.desc_issued));
 670                 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR);
 671
 672                 if (list_empty(&chan->vc.desc_issued)) {
 673                         chan->misaligned =
 674                                 !list_empty(&chan->vc.desc_submitted);
 675                 } else {
 676                         vd = list_first_entry(&chan->vc.desc_issued,
 677                                               struct virt_dma_desc, node);
 678                         pxad_launch_chan(chan, to_pxad_sw_desc(vd));
 679                 }
 680         }
 681         spin_unlock_irqrestore(&chan->vc.lock, flags);
 682
 683         return IRQ_HANDLED;
 684 }
 685
 686 static irqreturn_t pxad_int_handler(int irq, void *dev_id)
 687 {
 688         struct pxad_device *pdev = dev_id;
 689         struct pxad_phy *phy;
 690         u32 dint = readl(pdev->base + DINT);
 691         int i, ret = IRQ_NONE;
 692
 693         while (dint) {
 694                 i = __ffs(dint);
 695                 dint &= (dint - 1);
 696                 phy = &pdev->phys[i];
 697                 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED)
 698                         ret = IRQ_HANDLED;
 699         }
 700
 701         return ret;
 702 }
 703
 704 static int pxad_alloc_chan_resources(struct dma_chan *dchan)
 705 {
 706         struct pxad_chan *chan = to_pxad_chan(dchan);
 707         struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
 708
 709         if (chan->desc_pool)
 710                 return 1;
 711
 712         chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
 713                                           pdev->slave.dev,
 714                                           sizeof(struct pxad_desc_hw),
 715                                           __alignof__(struct pxad_desc_hw),
 716                                           0);
 717         if (!chan->desc_pool) {
 718                 dev_err(&chan->vc.chan.dev->device,
 719                         "%s(): unable to allocate descriptor pool\n",
 720                         __func__);
 721                 return -ENOMEM;
 722         }
 723
 724         return 1;
 725 }
 726
 727 static void pxad_free_chan_resources(struct dma_chan *dchan)
 728 {
 729         struct pxad_chan *chan = to_pxad_chan(dchan);
 730
 731         vchan_free_chan_resources(&chan->vc);
 732         dma_pool_destroy(chan->desc_pool);
 733         chan->desc_pool = NULL;
 734
 735 }
 736
 737 static void pxad_free_desc(struct virt_dma_desc *vd)
 738 {
 739         int i;
 740         dma_addr_t dma;
 741         struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
 742
 743         BUG_ON(sw_desc->nb_desc == 0);
 744         for (i = sw_desc->nb_desc - 1; i >= 0; i--) {
 745                 if (i > 0)
 746                         dma = sw_desc->hw_desc[i - 1]->ddadr;
 747                 else
 748                         dma = sw_desc->first;
 749                 dma_pool_free(sw_desc->desc_pool,
 750                               sw_desc->hw_desc[i], dma);
 751         }
 752         sw_desc->nb_desc = 0;
 753         kfree(sw_desc);
 754 }
 755
 756 static struct pxad_desc_sw *
 757 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc)
 758 {
 759         struct pxad_desc_sw *sw_desc;
 760         dma_addr_t dma;
 761         int i;
 762
 763         sw_desc = kzalloc(sizeof(*sw_desc) +
 764                           nb_hw_desc * sizeof(struct pxad_desc_hw *),
 765                           GFP_NOWAIT);
 766         if (!sw_desc)
 767                 return NULL;
 768         sw_desc->desc_pool = chan->desc_pool;
 769
 770         for (i = 0; i < nb_hw_desc; i++) {
 771                 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool,
 772                                                      GFP_NOWAIT, &dma);
 773                 if (!sw_desc->hw_desc[i]) {
 774                         dev_err(&chan->vc.chan.dev->device,
 775                                 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n",
 776                                 __func__, i, sw_desc->desc_pool);
 777                         goto err;
 778                 }
 779
 780                 if (i == 0)
 781                         sw_desc->first = dma;
 782                 else
 783                         sw_desc->hw_desc[i - 1]->ddadr = dma;
 784                 sw_desc->nb_desc++;
 785         }
 786
 787         return sw_desc;
 788 err:
 789         pxad_free_desc(&sw_desc->vd);
 790         return NULL;
 791 }
 792
 793 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx)
 794 {
 795         struct virt_dma_chan *vc = to_virt_chan(tx->chan);
 796         struct pxad_chan *chan = to_pxad_chan(&vc->chan);
 797         struct virt_dma_desc *vd_chained = NULL,
 798                 *vd = container_of(tx, struct virt_dma_desc, tx);
 799         dma_cookie_t cookie;
 800         unsigned long flags;
 801
 802         set_updater_desc(to_pxad_sw_desc(vd), tx->flags);
 803
 804         spin_lock_irqsave(&vc->lock, flags);
 805         cookie = dma_cookie_assign(tx);
 806
 807         if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {
 808                 list_move_tail(&vd->node, &vc->desc_issued);
 809                 dev_dbg(&chan->vc.chan.dev->device,
 810                         "%s(): txd %p[%x]: submitted (hot linked)\n",
 811                         __func__, vd, cookie);
 812                 goto out;
 813         }
 814
 815         /*
 816          * Fallback to placing the tx in the submitted queue
 817          */
 818         if (!list_empty(&vc->desc_submitted)) {
 819                 vd_chained = list_entry(vc->desc_submitted.prev,
 820                                         struct virt_dma_desc, node);
 821                 /*
 822                  * Only chain the descriptors if no new misalignment is
 823                  * introduced. If a new misalignment is chained, let the channel
 824                  * stop, and be relaunched in misalign mode from the irq
 825                  * handler.
 826                  */
 827                 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)
 828                         pxad_desc_chain(vd_chained, vd);
 829                 else
 830                         vd_chained = NULL;
 831         }
 832         dev_dbg(&chan->vc.chan.dev->device,
 833                 "%s(): txd %p[%x]: submitted (%s linked)\n",
 834                 __func__, vd, cookie, vd_chained ? "cold" : "not");
 835         list_move_tail(&vd->node, &vc->desc_submitted);
 836         chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;
 837
 838 out:
 839         spin_unlock_irqrestore(&vc->lock, flags);
 840         return cookie;
 841 }
 842
 843 static void pxad_issue_pending(struct dma_chan *dchan)
 844 {
 845         struct pxad_chan *chan = to_pxad_chan(dchan);
 846         struct virt_dma_desc *vd_first;
 847         unsigned long flags;
 848
 849         spin_lock_irqsave(&chan->vc.lock, flags);
 850         if (list_empty(&chan->vc.desc_submitted))
 851                 goto out;
 852
 853         vd_first = list_first_entry(&chan->vc.desc_submitted,
 854                                     struct virt_dma_desc, node);
 855         dev_dbg(&chan->vc.chan.dev->device,
 856                 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);
 857
 858         vchan_issue_pending(&chan->vc);
 859         if (!pxad_try_hotchain(&chan->vc, vd_first))
 860                 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first));
 861 out:
 862         spin_unlock_irqrestore(&chan->vc.lock, flags);
 863 }
 864
 865 static inline struct dma_async_tx_descriptor *
 866 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd,
 867                  unsigned long tx_flags)
 868 {
 869         struct dma_async_tx_descriptor *tx;
 870         struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc);
 871
 872         tx = vchan_tx_prep(vc, vd, tx_flags);
 873         tx->tx_submit = pxad_tx_submit;
 874         dev_dbg(&chan->vc.chan.dev->device,
 875                 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__,
 876                 vc, vd, vd->tx.cookie,
 877                 tx_flags);
 878
 879         return tx;
 880 }
 881
 882 static void pxad_get_config(struct pxad_chan *chan,
 883                             enum dma_transfer_direction dir,
 884                             u32 *dcmd, u32 *dev_src, u32 *dev_dst)
 885 {
 886         u32 maxburst = 0, dev_addr = 0;
 887         enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 888
 889         *dcmd = 0;
 890         if (chan->cfg.direction == DMA_DEV_TO_MEM) {
 891                 maxburst = chan->cfg.src_maxburst;
 892                 width = chan->cfg.src_addr_width;
 893                 dev_addr = chan->cfg.src_addr;
 894                 *dev_src = dev_addr;
 895                 *dcmd |= PXA_DCMD_INCTRGADDR | PXA_DCMD_FLOWSRC;
 896         }
 897         if (chan->cfg.direction == DMA_MEM_TO_DEV) {
 898                 maxburst = chan->cfg.dst_maxburst;
 899                 width = chan->cfg.dst_addr_width;
 900                 dev_addr = chan->cfg.dst_addr;
 901                 *dev_dst = dev_addr;
 902                 *dcmd |= PXA_DCMD_INCSRCADDR | PXA_DCMD_FLOWTRG;
 903         }
 904         if (chan->cfg.direction == DMA_MEM_TO_MEM)
 905                 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |
 906                         PXA_DCMD_INCSRCADDR;
 907
 908         dev_dbg(&chan->vc.chan.dev->device,
 909                 "%s(): dev_addr=0x%x maxburst=%d width=%d  dir=%d\n",
 910                 __func__, dev_addr, maxburst, width, dir);
 911
 912         if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
 913                 *dcmd |= PXA_DCMD_WIDTH1;
 914         else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
 915                 *dcmd |= PXA_DCMD_WIDTH2;
 916         else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
 917                 *dcmd |= PXA_DCMD_WIDTH4;
 918
 919         if (maxburst == 8)
 920                 *dcmd |= PXA_DCMD_BURST8;
 921         else if (maxburst == 16)
 922                 *dcmd |= PXA_DCMD_BURST16;
 923         else if (maxburst == 32)
 924                 *dcmd |= PXA_DCMD_BURST32;
 925
 926         /* FIXME: drivers should be ported over to use the filter
 927          * function. Once that's done, the following two lines can
 928          * be removed.
 929          */
 930         if (chan->cfg.slave_id)
 931                 chan->drcmr = chan->cfg.slave_id;
 932 }
 933
 934 static struct dma_async_tx_descriptor *
 935 pxad_prep_memcpy(struct dma_chan *dchan,
 936                  dma_addr_t dma_dst, dma_addr_t dma_src,
 937                  size_t len, unsigned long flags)
 938 {
 939         struct pxad_chan *chan = to_pxad_chan(dchan);
 940         struct pxad_desc_sw *sw_desc;
 941         struct pxad_desc_hw *hw_desc;
 942         u32 dcmd;
 943         unsigned int i, nb_desc = 0;
 944         size_t copy;
 945
 946         if (!dchan || !len)
 947                 return NULL;
 948
 949         dev_dbg(&chan->vc.chan.dev->device,
 950                 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n",
 951                 __func__, (unsigned long)dma_dst, (unsigned long)dma_src,
 952                 len, flags);
 953         pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL);
 954
 955         nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES);
 956         sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
 957         if (!sw_desc)
 958                 return NULL;
 959         sw_desc->len = len;
 960
 961         if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) ||
 962             !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT))
 963                 sw_desc->misaligned = true;
 964
 965         i = 0;
 966         do {
 967                 hw_desc = sw_desc->hw_desc[i++];
 968                 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
 969                 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);
 970                 hw_desc->dsadr = dma_src;
 971                 hw_desc->dtadr = dma_dst;
 972                 len -= copy;
 973                 dma_src += copy;
 974                 dma_dst += copy;
 975         } while (len);
 976         set_updater_desc(sw_desc, flags);
 977
 978         return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
 979 }
 980
 981 static struct dma_async_tx_descriptor *
 982 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
 983                    unsigned int sg_len, enum dma_transfer_direction dir,
 984                    unsigned long flags, void *context)
 985 {
 986         struct pxad_chan *chan = to_pxad_chan(dchan);
 987         struct pxad_desc_sw *sw_desc;
 988         size_t len, avail;
 989         struct scatterlist *sg;
 990         dma_addr_t dma;
 991         u32 dcmd, dsadr = 0, dtadr = 0;
 992         unsigned int nb_desc = 0, i, j = 0;
 993
 994         if ((sgl == NULL) || (sg_len == 0))
 995                 return NULL;
 996
 997         pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
 998         dev_dbg(&chan->vc.chan.dev->device,
 999                 "%s(): dir=%d flags=%lx\n", __func__, dir, flags);
1000
1001         for_each_sg(sgl, sg, sg_len, i)
1002                 nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES);
1003         sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1004         if (!sw_desc)
1005                 return NULL;
1006
1007         for_each_sg(sgl, sg, sg_len, i) {
1008                 dma = sg_dma_address(sg);
1009                 avail = sg_dma_len(sg);
1010                 sw_desc->len += avail;
1011
1012                 do {
1013                         len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
1014                         if (dma & 0x7)
1015                                 sw_desc->misaligned = true;
1016
1017                         sw_desc->hw_desc[j]->dcmd =
1018                                 dcmd | (PXA_DCMD_LENGTH & len);
1019                         sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;
1020                         sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;
1021
1022                         dma += len;
1023                         avail -= len;
1024                 } while (avail);
1025         }
1026         set_updater_desc(sw_desc, flags);
1027
1028         return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1029 }
1030
1031 static struct dma_async_tx_descriptor *
1032 pxad_prep_dma_cyclic(struct dma_chan *dchan,
1033                      dma_addr_t buf_addr, size_t len, size_t period_len,
1034                      enum dma_transfer_direction dir, unsigned long flags)
1035 {
1036         struct pxad_chan *chan = to_pxad_chan(dchan);
1037         struct pxad_desc_sw *sw_desc;
1038         struct pxad_desc_hw **phw_desc;
1039         dma_addr_t dma;
1040         u32 dcmd, dsadr = 0, dtadr = 0;
1041         unsigned int nb_desc = 0;
1042
1043         if (!dchan || !len || !period_len)
1044                 return NULL;
1045         if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) {
1046                 dev_err(&chan->vc.chan.dev->device,
1047                         "Unsupported direction for cyclic DMA\n");
1048                 return NULL;
1049         }
1050         /* the buffer length must be a multiple of period_len */
1051         if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES ||
1052             !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT))
1053                 return NULL;
1054
1055         pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1056         dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH | period_len);
1057         dev_dbg(&chan->vc.chan.dev->device,
1058                 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n",
1059                 __func__, (unsigned long)buf_addr, len, period_len, dir, flags);
1060
1061         nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES);
1062         nb_desc *= DIV_ROUND_UP(len, period_len);
1063         sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1064         if (!sw_desc)
1065                 return NULL;
1066         sw_desc->cyclic = true;
1067         sw_desc->len = len;
1068
1069         phw_desc = sw_desc->hw_desc;
1070         dma = buf_addr;
1071         do {
1072                 phw_desc[0]->dsadr = dsadr ? dsadr : dma;
1073                 phw_desc[0]->dtadr = dtadr ? dtadr : dma;
1074                 phw_desc[0]->dcmd = dcmd;
1075                 phw_desc++;
1076                 dma += period_len;
1077                 len -= period_len;
1078         } while (len);
1079         set_updater_desc(sw_desc, flags);
1080
1081         return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1082 }
1083
1084 static int pxad_config(struct dma_chan *dchan,
1085                        struct dma_slave_config *cfg)
1086 {
1087         struct pxad_chan *chan = to_pxad_chan(dchan);
1088
1089         if (!dchan)
1090                 return -EINVAL;
1091
1092         chan->cfg = *cfg;
1093         return 0;
1094 }
1095
1096 static int pxad_terminate_all(struct dma_chan *dchan)
1097 {
1098         struct pxad_chan *chan = to_pxad_chan(dchan);
1099         struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
1100         struct virt_dma_desc *vd = NULL;
1101         unsigned long flags;
1102         struct pxad_phy *phy;
1103         LIST_HEAD(head);
1104
1105         dev_dbg(&chan->vc.chan.dev->device,
1106                 "%s(): vchan %p: terminate all\n", __func__, &chan->vc);
1107
1108         spin_lock_irqsave(&chan->vc.lock, flags);
1109         vchan_get_all_descriptors(&chan->vc, &head);
1110
1111         list_for_each_entry(vd, &head, node) {
1112                 dev_dbg(&chan->vc.chan.dev->device,
1113                         "%s(): cancelling txd %p[%x] (completed=%d)", __func__,
1114                         vd, vd->tx.cookie, is_desc_completed(vd));
1115         }
1116
1117         phy = chan->phy;
1118         if (phy) {
1119                 phy_disable(chan->phy);
1120                 pxad_free_phy(chan);
1121                 chan->phy = NULL;
1122                 spin_lock(&pdev->phy_lock);
1123                 phy->vchan = NULL;
1124                 spin_unlock(&pdev->phy_lock);
1125         }
1126         spin_unlock_irqrestore(&chan->vc.lock, flags);
1127         vchan_dma_desc_free_list(&chan->vc, &head);
1128
1129         return 0;
1130 }
1131
1132 static unsigned int pxad_residue(struct pxad_chan *chan,
1133                                  dma_cookie_t cookie)
1134 {
1135         struct virt_dma_desc *vd = NULL;
1136         struct pxad_desc_sw *sw_desc = NULL;
1137         struct pxad_desc_hw *hw_desc = NULL;
1138         u32 curr, start, len, end, residue = 0;
1139         unsigned long flags;
1140         bool passed = false;
1141         int i;
1142
1143         /*
1144          * If the channel does not have a phy pointer anymore, it has already
1145          * been completed. Therefore, its residue is 0.
1146          */
1147         if (!chan->phy)
1148                 return 0;
1149
1150         spin_lock_irqsave(&chan->vc.lock, flags);
1151
1152         vd = vchan_find_desc(&chan->vc, cookie);
1153         if (!vd)
1154                 goto out;
1155
1156         sw_desc = to_pxad_sw_desc(vd);
1157         if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1158                 curr = phy_readl_relaxed(chan->phy, DSADR);
1159         else
1160                 curr = phy_readl_relaxed(chan->phy, DTADR);
1161
1162         for (i = 0; i < sw_desc->nb_desc - 1; i++) {
1163                 hw_desc = sw_desc->hw_desc[i];
1164                 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1165                         start = hw_desc->dsadr;
1166                 else
1167                         start = hw_desc->dtadr;
1168                 len = hw_desc->dcmd & PXA_DCMD_LENGTH;
1169                 end = start + len;
1170
1171                 /*
1172                  * 'passed' will be latched once we found the descriptor
1173                  * which lies inside the boundaries of the curr
1174                  * pointer. All descriptors that occur in the list
1175                  * _after_ we found that partially handled descriptor
1176                  * are still to be processed and are hence added to the
1177                  * residual bytes counter.
1178                  */
1179
1180                 if (passed) {
1181                         residue += len;
1182                 } else if (curr >= start && curr <= end) {
1183                         residue += end - curr;
1184                         passed = true;
1185                 }
1186         }
1187         if (!passed)
1188                 residue = sw_desc->len;
1189
1190 out:
1191         spin_unlock_irqrestore(&chan->vc.lock, flags);
1192         dev_dbg(&chan->vc.chan.dev->device,
1193                 "%s(): txd %p[%x] sw_desc=%p: %d\n",
1194                 __func__, vd, cookie, sw_desc, residue);
1195         return residue;
1196 }
1197
1198 static enum dma_status pxad_tx_status(struct dma_chan *dchan,
1199                                       dma_cookie_t cookie,
1200                                       struct dma_tx_state *txstate)
1201 {
1202         struct pxad_chan *chan = to_pxad_chan(dchan);
1203         enum dma_status ret;
1204
1205         ret = dma_cookie_status(dchan, cookie, txstate);
1206         if (likely(txstate && (ret != DMA_ERROR)))
1207                 dma_set_residue(txstate, pxad_residue(chan, cookie));
1208
1209         return ret;
1210 }
1211
1212 static void pxad_free_channels(struct dma_device *dmadev)
1213 {
1214         struct pxad_chan *c, *cn;
1215
1216         list_for_each_entry_safe(c, cn, &dmadev->channels,
1217                                  vc.chan.device_node) {
1218                 list_del(&c->vc.chan.device_node);
1219                 tasklet_kill(&c->vc.task);
1220         }
1221 }
1222
1223 static int pxad_remove(struct platform_device *op)
1224 {
1225         struct pxad_device *pdev = platform_get_drvdata(op);
1226
1227         pxad_cleanup_debugfs(pdev);
1228         pxad_free_channels(&pdev->slave);
1229         dma_async_device_unregister(&pdev->slave);
1230         return 0;
1231 }
1232
1233 static int pxad_init_phys(struct platform_device *op,
1234                           struct pxad_device *pdev,
1235                           unsigned int nb_phy_chans)
1236 {
1237         int irq0, irq, nr_irq = 0, i, ret;
1238         struct pxad_phy *phy;
1239
1240         irq0 = platform_get_irq(op, 0);
1241         if (irq0 < 0)
1242                 return irq0;
1243
1244         pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,
1245                                   sizeof(pdev->phys[0]), GFP_KERNEL);
1246         if (!pdev->phys)
1247                 return -ENOMEM;
1248
1249         for (i = 0; i < nb_phy_chans; i++)
1250                 if (platform_get_irq(op, i) > 0)
1251                         nr_irq++;
1252
1253         for (i = 0; i < nb_phy_chans; i++) {
1254                 phy = &pdev->phys[i];
1255                 phy->base = pdev->base;
1256                 phy->idx = i;
1257                 irq = platform_get_irq(op, i);
1258                 if ((nr_irq > 1) && (irq > 0))
1259                         ret = devm_request_irq(&op->dev, irq,
1260                                                pxad_chan_handler,
1261                                                IRQF_SHARED, "pxa-dma", phy);
1262                 if ((nr_irq == 1) && (i == 0))
1263                         ret = devm_request_irq(&op->dev, irq0,
1264                                                pxad_int_handler,
1265                                                IRQF_SHARED, "pxa-dma", pdev);
1266                 if (ret) {
1267                         dev_err(pdev->slave.dev,
1268                                 "%s(): can't request irq %d:%d\n", __func__,
1269                                 irq, ret);
1270                         return ret;
1271                 }
1272         }
1273
1274         return 0;
1275 }
1276
1277 static const struct of_device_id const pxad_dt_ids[] = {
1278         { .compatible = "marvell,pdma-1.0", },
1279         {}
1280 };
1281 MODULE_DEVICE_TABLE(of, pxad_dt_ids);
1282
1283 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec,
1284                                            struct of_dma *ofdma)
1285 {
1286         struct pxad_device *d = ofdma->of_dma_data;
1287         struct dma_chan *chan;
1288
1289         chan = dma_get_any_slave_channel(&d->slave);
1290         if (!chan)
1291                 return NULL;
1292
1293         to_pxad_chan(chan)->drcmr = dma_spec->args[0];
1294         to_pxad_chan(chan)->prio = dma_spec->args[1];
1295
1296         return chan;
1297 }
1298
1299 static int pxad_init_dmadev(struct platform_device *op,
1300                             struct pxad_device *pdev,
1301                             unsigned int nr_phy_chans)
1302 {
1303         int ret;
1304         unsigned int i;
1305         struct pxad_chan *c;
1306
1307         pdev->nr_chans = nr_phy_chans;
1308         INIT_LIST_HEAD(&pdev->slave.channels);
1309         pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;
1310         pdev->slave.device_free_chan_resources = pxad_free_chan_resources;
1311         pdev->slave.device_tx_status = pxad_tx_status;
1312         pdev->slave.device_issue_pending = pxad_issue_pending;
1313         pdev->slave.device_config = pxad_config;
1314         pdev->slave.device_terminate_all = pxad_terminate_all;
1315
1316         if (op->dev.coherent_dma_mask)
1317                 dma_set_mask(&op->dev, op->dev.coherent_dma_mask);
1318         else
1319                 dma_set_mask(&op->dev, DMA_BIT_MASK(32));
1320
1321         ret = pxad_init_phys(op, pdev, nr_phy_chans);
1322         if (ret)
1323                 return ret;
1324
1325         for (i = 0; i < nr_phy_chans; i++) {
1326                 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);
1327                 if (!c)
1328                         return -ENOMEM;
1329                 c->vc.desc_free = pxad_free_desc;
1330                 vchan_init(&c->vc, &pdev->slave);
1331         }
1332
1333         return dma_async_device_register(&pdev->slave);
1334 }
1335
1336 static int pxad_probe(struct platform_device *op)
1337 {
1338         struct pxad_device *pdev;
1339         const struct of_device_id *of_id;
1340         struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1341         struct resource *iores;
1342         int ret, dma_channels = 0;
1343         const enum dma_slave_buswidth widths =
1344                 DMA_SLAVE_BUSWIDTH_1_BYTE   | DMA_SLAVE_BUSWIDTH_2_BYTES |
1345                 DMA_SLAVE_BUSWIDTH_4_BYTES;
1346
1347         pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
1348         if (!pdev)
1349                 return -ENOMEM;
1350
1351         spin_lock_init(&pdev->phy_lock);
1352
1353         iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1354         pdev->base = devm_ioremap_resource(&op->dev, iores);
1355         if (IS_ERR(pdev->base))
1356                 return PTR_ERR(pdev->base);
1357
1358         of_id = of_match_device(pxad_dt_ids, &op->dev);
1359         if (of_id)
1360                 of_property_read_u32(op->dev.of_node, "#dma-channels",
1361                                      &dma_channels);
1362         else if (pdata && pdata->dma_channels)
1363                 dma_channels = pdata->dma_channels;
1364         else
1365                 dma_channels = 32;      /* default 32 channel */
1366
1367         dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);
1368         dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);
1369         dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);
1370         dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);
1371         pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;
1372         pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;
1373         pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;
1374
1375         pdev->slave.copy_align = PDMA_ALIGNMENT;
1376         pdev->slave.src_addr_widths = widths;
1377         pdev->slave.dst_addr_widths = widths;
1378         pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1379         pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1380
1381         pdev->slave.dev = &op->dev;
1382         ret = pxad_init_dmadev(op, pdev, dma_channels);
1383         if (ret) {
1384                 dev_err(pdev->slave.dev, "unable to register\n");
1385                 return ret;
1386         }
1387
1388         if (op->dev.of_node) {
1389                 /* Device-tree DMA controller registration */
1390                 ret = of_dma_controller_register(op->dev.of_node,
1391                                                  pxad_dma_xlate, pdev);
1392                 if (ret < 0) {
1393                         dev_err(pdev->slave.dev,
1394                                 "of_dma_controller_register failed\n");
1395                         return ret;
1396                 }
1397         }
1398
1399         platform_set_drvdata(op, pdev);
1400         pxad_init_debugfs(pdev);
1401         dev_info(pdev->slave.dev, "initialized %d channels\n", dma_channels);
1402         return 0;
1403 }
1404
1405 static const struct platform_device_id pxad_id_table[] = {
1406         { "pxa-dma", },
1407         { },
1408 };
1409
1410 static struct platform_driver pxad_driver = {
1411         .driver         = {
1412                 .name   = "pxa-dma",
1413                 .of_match_table = pxad_dt_ids,
1414         },
1415         .id_table       = pxad_id_table,
1416         .probe          = pxad_probe,
1417         .remove         = pxad_remove,
1418 };
1419
1420 bool pxad_filter_fn(struct dma_chan *chan, void *param)
1421 {
1422         struct pxad_chan *c = to_pxad_chan(chan);
1423         struct pxad_param *p = param;
1424
1425         if (chan->device->dev->driver != &pxad_driver.driver)
1426                 return false;
1427
1428         c->drcmr = p->drcmr;
1429         c->prio = p->prio;
1430
1431         return true;
1432 }
1433 EXPORT_SYMBOL_GPL(pxad_filter_fn);
1434
1435 module_platform_driver(pxad_driver);
1436
1437 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");
1438 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
1439 MODULE_LICENSE("GPL v2");