drivers/dma/qcom_bam_dma.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14 /*
  15  * QCOM BAM DMA engine driver
  16  *
  17  * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
  18  * peripherals on the MSM 8x74.  The configuration of the channels are dependent
  19  * on the way they are hard wired to that specific peripheral.  The peripheral
  20  * device tree entries specify the configuration of each channel.
  21  *
  22  * The DMA controller requires the use of external memory for storage of the
  23  * hardware descriptors for each channel.  The descriptor FIFO is accessed as a
  24  * circular buffer and operations are managed according to the offset within the
  25  * FIFO.  After pipe/channel reset, all of the pipe registers and internal state
  26  * are back to defaults.
  27  *
  28  * During DMA operations, we write descriptors to the FIFO, being careful to
  29  * handle wrapping and then write the last FIFO offset to that channel's
  30  * P_EVNT_REG register to kick off the transaction.  The P_SW_OFSTS register
  31  * indicates the current FIFO offset that is being processed, so there is some
  32  * indication of where the hardware is currently working.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/io.h>
  37 #include <linux/init.h>
  38 #include <linux/slab.h>
  39 #include <linux/module.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/scatterlist.h>
  43 #include <linux/device.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/of.h>
  46 #include <linux/of_address.h>
  47 #include <linux/of_irq.h>
  48 #include <linux/of_dma.h>
  49 #include <linux/clk.h>
  50 #include <linux/dmaengine.h>
  51
  52 #include "dmaengine.h"
  53 #include "virt-dma.h"
  54
  55 struct bam_desc_hw {
  56         u32 addr;               /* Buffer physical address */
  57         u16 size;               /* Buffer size in bytes */
  58         u16 flags;
  59 };
  60
  61 #define DESC_FLAG_INT BIT(15)
  62 #define DESC_FLAG_EOT BIT(14)
  63 #define DESC_FLAG_EOB BIT(13)
  64 #define DESC_FLAG_NWD BIT(12)
  65
  66 struct bam_async_desc {
  67         struct virt_dma_desc vd;
  68
  69         u32 num_desc;
  70         u32 xfer_len;
  71
  72         /* transaction flags, EOT|EOB|NWD */
  73         u16 flags;
  74
  75         struct bam_desc_hw *curr_desc;
  76
  77         enum dma_transfer_direction dir;
  78         size_t length;
  79         struct bam_desc_hw desc[0];
  80 };
  81
  82 enum bam_reg {
  83         BAM_CTRL,
  84         BAM_REVISION,
  85         BAM_NUM_PIPES,
  86         BAM_DESC_CNT_TRSHLD,
  87         BAM_IRQ_SRCS,
  88         BAM_IRQ_SRCS_MSK,
  89         BAM_IRQ_SRCS_UNMASKED,
  90         BAM_IRQ_STTS,
  91         BAM_IRQ_CLR,
  92         BAM_IRQ_EN,
  93         BAM_CNFG_BITS,
  94         BAM_IRQ_SRCS_EE,
  95         BAM_IRQ_SRCS_MSK_EE,
  96         BAM_P_CTRL,
  97         BAM_P_RST,
  98         BAM_P_HALT,
  99         BAM_P_IRQ_STTS,
 100         BAM_P_IRQ_CLR,
 101         BAM_P_IRQ_EN,
 102         BAM_P_EVNT_DEST_ADDR,
 103         BAM_P_EVNT_REG,
 104         BAM_P_SW_OFSTS,
 105         BAM_P_DATA_FIFO_ADDR,
 106         BAM_P_DESC_FIFO_ADDR,
 107         BAM_P_EVNT_GEN_TRSHLD,
 108         BAM_P_FIFO_SIZES,
 109 };
 110
 111 struct reg_offset_data {
 112         u32 base_offset;
 113         unsigned int pipe_mult, evnt_mult, ee_mult;
 114 };
 115
 116 static const struct reg_offset_data reg_info[] = {
 117         [BAM_CTRL]              = { 0x0000, 0x00, 0x00, 0x00 },
 118         [BAM_REVISION]          = { 0x0004, 0x00, 0x00, 0x00 },
 119         [BAM_NUM_PIPES]         = { 0x003C, 0x00, 0x00, 0x00 },
 120         [BAM_DESC_CNT_TRSHLD]   = { 0x0008, 0x00, 0x00, 0x00 },
 121         [BAM_IRQ_SRCS]          = { 0x000C, 0x00, 0x00, 0x00 },
 122         [BAM_IRQ_SRCS_MSK]      = { 0x0010, 0x00, 0x00, 0x00 },
 123         [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 },
 124         [BAM_IRQ_STTS]          = { 0x0014, 0x00, 0x00, 0x00 },
 125         [BAM_IRQ_CLR]           = { 0x0018, 0x00, 0x00, 0x00 },
 126         [BAM_IRQ_EN]            = { 0x001C, 0x00, 0x00, 0x00 },
 127         [BAM_CNFG_BITS]         = { 0x007C, 0x00, 0x00, 0x00 },
 128         [BAM_IRQ_SRCS_EE]       = { 0x0800, 0x00, 0x00, 0x80 },
 129         [BAM_IRQ_SRCS_MSK_EE]   = { 0x0804, 0x00, 0x00, 0x80 },
 130         [BAM_P_CTRL]            = { 0x1000, 0x1000, 0x00, 0x00 },
 131         [BAM_P_RST]             = { 0x1004, 0x1000, 0x00, 0x00 },
 132         [BAM_P_HALT]            = { 0x1008, 0x1000, 0x00, 0x00 },
 133         [BAM_P_IRQ_STTS]        = { 0x1010, 0x1000, 0x00, 0x00 },
 134         [BAM_P_IRQ_CLR]         = { 0x1014, 0x1000, 0x00, 0x00 },
 135         [BAM_P_IRQ_EN]          = { 0x1018, 0x1000, 0x00, 0x00 },
 136         [BAM_P_EVNT_DEST_ADDR]  = { 0x102C, 0x00, 0x1000, 0x00 },
 137         [BAM_P_EVNT_REG]        = { 0x1018, 0x00, 0x1000, 0x00 },
 138         [BAM_P_SW_OFSTS]        = { 0x1000, 0x00, 0x1000, 0x00 },
 139         [BAM_P_DATA_FIFO_ADDR]  = { 0x1824, 0x00, 0x1000, 0x00 },
 140         [BAM_P_DESC_FIFO_ADDR]  = { 0x181C, 0x00, 0x1000, 0x00 },
 141         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
 142         [BAM_P_FIFO_SIZES]      = { 0x1820, 0x00, 0x1000, 0x00 },
 143 };
 144
 145 /* BAM CTRL */
 146 #define BAM_SW_RST                      BIT(0)
 147 #define BAM_EN                          BIT(1)
 148 #define BAM_EN_ACCUM                    BIT(4)
 149 #define BAM_TESTBUS_SEL_SHIFT           5
 150 #define BAM_TESTBUS_SEL_MASK            0x3F
 151 #define BAM_DESC_CACHE_SEL_SHIFT        13
 152 #define BAM_DESC_CACHE_SEL_MASK         0x3
 153 #define BAM_CACHED_DESC_STORE           BIT(15)
 154 #define IBC_DISABLE                     BIT(16)
 155
 156 /* BAM REVISION */
 157 #define REVISION_SHIFT          0
 158 #define REVISION_MASK           0xFF
 159 #define NUM_EES_SHIFT           8
 160 #define NUM_EES_MASK            0xF
 161 #define CE_BUFFER_SIZE          BIT(13)
 162 #define AXI_ACTIVE              BIT(14)
 163 #define USE_VMIDMT              BIT(15)
 164 #define SECURED                 BIT(16)
 165 #define BAM_HAS_NO_BYPASS       BIT(17)
 166 #define HIGH_FREQUENCY_BAM      BIT(18)
 167 #define INACTIV_TMRS_EXST       BIT(19)
 168 #define NUM_INACTIV_TMRS        BIT(20)
 169 #define DESC_CACHE_DEPTH_SHIFT  21
 170 #define DESC_CACHE_DEPTH_1      (0 << DESC_CACHE_DEPTH_SHIFT)
 171 #define DESC_CACHE_DEPTH_2      (1 << DESC_CACHE_DEPTH_SHIFT)
 172 #define DESC_CACHE_DEPTH_3      (2 << DESC_CACHE_DEPTH_SHIFT)
 173 #define DESC_CACHE_DEPTH_4      (3 << DESC_CACHE_DEPTH_SHIFT)
 174 #define CMD_DESC_EN             BIT(23)
 175 #define INACTIV_TMR_BASE_SHIFT  24
 176 #define INACTIV_TMR_BASE_MASK   0xFF
 177
 178 /* BAM NUM PIPES */
 179 #define BAM_NUM_PIPES_SHIFT             0
 180 #define BAM_NUM_PIPES_MASK              0xFF
 181 #define PERIPH_NON_PIPE_GRP_SHIFT       16
 182 #define PERIPH_NON_PIP_GRP_MASK         0xFF
 183 #define BAM_NON_PIPE_GRP_SHIFT          24
 184 #define BAM_NON_PIPE_GRP_MASK           0xFF
 185
 186 /* BAM CNFG BITS */
 187 #define BAM_PIPE_CNFG           BIT(2)
 188 #define BAM_FULL_PIPE           BIT(11)
 189 #define BAM_NO_EXT_P_RST        BIT(12)
 190 #define BAM_IBC_DISABLE         BIT(13)
 191 #define BAM_SB_CLK_REQ          BIT(14)
 192 #define BAM_PSM_CSW_REQ         BIT(15)
 193 #define BAM_PSM_P_RES           BIT(16)
 194 #define BAM_AU_P_RES            BIT(17)
 195 #define BAM_SI_P_RES            BIT(18)
 196 #define BAM_WB_P_RES            BIT(19)
 197 #define BAM_WB_BLK_CSW          BIT(20)
 198 #define BAM_WB_CSW_ACK_IDL      BIT(21)
 199 #define BAM_WB_RETR_SVPNT       BIT(22)
 200 #define BAM_WB_DSC_AVL_P_RST    BIT(23)
 201 #define BAM_REG_P_EN            BIT(24)
 202 #define BAM_PSM_P_HD_DATA       BIT(25)
 203 #define BAM_AU_ACCUMED          BIT(26)
 204 #define BAM_CMD_ENABLE          BIT(27)
 205
 206 #define BAM_CNFG_BITS_DEFAULT   (BAM_PIPE_CNFG |        \
 207                                  BAM_NO_EXT_P_RST |     \
 208                                  BAM_IBC_DISABLE |      \
 209                                  BAM_SB_CLK_REQ |       \
 210                                  BAM_PSM_CSW_REQ |      \
 211                                  BAM_PSM_P_RES |        \
 212                                  BAM_AU_P_RES |         \
 213                                  BAM_SI_P_RES |         \
 214                                  BAM_WB_P_RES |         \
 215                                  BAM_WB_BLK_CSW |       \
 216                                  BAM_WB_CSW_ACK_IDL |   \
 217                                  BAM_WB_RETR_SVPNT |    \
 218                                  BAM_WB_DSC_AVL_P_RST | \
 219                                  BAM_REG_P_EN |         \
 220                                  BAM_PSM_P_HD_DATA |    \
 221                                  BAM_AU_ACCUMED |       \
 222                                  BAM_CMD_ENABLE)
 223
 224 /* PIPE CTRL */
 225 #define P_EN                    BIT(1)
 226 #define P_DIRECTION             BIT(3)
 227 #define P_SYS_STRM              BIT(4)
 228 #define P_SYS_MODE              BIT(5)
 229 #define P_AUTO_EOB              BIT(6)
 230 #define P_AUTO_EOB_SEL_SHIFT    7
 231 #define P_AUTO_EOB_SEL_512      (0 << P_AUTO_EOB_SEL_SHIFT)
 232 #define P_AUTO_EOB_SEL_256      (1 << P_AUTO_EOB_SEL_SHIFT)
 233 #define P_AUTO_EOB_SEL_128      (2 << P_AUTO_EOB_SEL_SHIFT)
 234 #define P_AUTO_EOB_SEL_64       (3 << P_AUTO_EOB_SEL_SHIFT)
 235 #define P_PREFETCH_LIMIT_SHIFT  9
 236 #define P_PREFETCH_LIMIT_32     (0 << P_PREFETCH_LIMIT_SHIFT)
 237 #define P_PREFETCH_LIMIT_16     (1 << P_PREFETCH_LIMIT_SHIFT)
 238 #define P_PREFETCH_LIMIT_4      (2 << P_PREFETCH_LIMIT_SHIFT)
 239 #define P_WRITE_NWD             BIT(11)
 240 #define P_LOCK_GROUP_SHIFT      16
 241 #define P_LOCK_GROUP_MASK       0x1F
 242
 243 /* BAM_DESC_CNT_TRSHLD */
 244 #define CNT_TRSHLD              0xffff
 245 #define DEFAULT_CNT_THRSHLD     0x4
 246
 247 /* BAM_IRQ_SRCS */
 248 #define BAM_IRQ                 BIT(31)
 249 #define P_IRQ                   0x7fffffff
 250
 251 /* BAM_IRQ_SRCS_MSK */
 252 #define BAM_IRQ_MSK             BAM_IRQ
 253 #define P_IRQ_MSK               P_IRQ
 254
 255 /* BAM_IRQ_STTS */
 256 #define BAM_TIMER_IRQ           BIT(4)
 257 #define BAM_EMPTY_IRQ           BIT(3)
 258 #define BAM_ERROR_IRQ           BIT(2)
 259 #define BAM_HRESP_ERR_IRQ       BIT(1)
 260
 261 /* BAM_IRQ_CLR */
 262 #define BAM_TIMER_CLR           BIT(4)
 263 #define BAM_EMPTY_CLR           BIT(3)
 264 #define BAM_ERROR_CLR           BIT(2)
 265 #define BAM_HRESP_ERR_CLR       BIT(1)
 266
 267 /* BAM_IRQ_EN */
 268 #define BAM_TIMER_EN            BIT(4)
 269 #define BAM_EMPTY_EN            BIT(3)
 270 #define BAM_ERROR_EN            BIT(2)
 271 #define BAM_HRESP_ERR_EN        BIT(1)
 272
 273 /* BAM_P_IRQ_EN */
 274 #define P_PRCSD_DESC_EN         BIT(0)
 275 #define P_TIMER_EN              BIT(1)
 276 #define P_WAKE_EN               BIT(2)
 277 #define P_OUT_OF_DESC_EN        BIT(3)
 278 #define P_ERR_EN                BIT(4)
 279 #define P_TRNSFR_END_EN         BIT(5)
 280 #define P_DEFAULT_IRQS_EN       (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
 281
 282 /* BAM_P_SW_OFSTS */
 283 #define P_SW_OFSTS_MASK         0xffff
 284
 285 #define BAM_DESC_FIFO_SIZE      SZ_32K
 286 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
 287 #define BAM_MAX_DATA_SIZE       (SZ_32K - 8)
 288
 289 struct bam_chan {
 290         struct virt_dma_chan vc;
 291
 292         struct bam_device *bdev;
 293
 294         /* configuration from device tree */
 295         u32 id;
 296
 297         struct bam_async_desc *curr_txd;        /* current running dma */
 298
 299         /* runtime configuration */
 300         struct dma_slave_config slave;
 301
 302         /* fifo storage */
 303         struct bam_desc_hw *fifo_virt;
 304         dma_addr_t fifo_phys;
 305
 306         /* fifo markers */
 307         unsigned short head;            /* start of active descriptor entries */
 308         unsigned short tail;            /* end of active descriptor entries */
 309
 310         unsigned int initialized;       /* is the channel hw initialized? */
 311         unsigned int paused;            /* is the channel paused? */
 312         unsigned int reconfigure;       /* new slave config? */
 313
 314         struct list_head node;
 315 };
 316
 317 static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
 318 {
 319         return container_of(common, struct bam_chan, vc.chan);
 320 }
 321
 322 struct bam_device {
 323         void __iomem *regs;
 324         struct device *dev;
 325         struct dma_device common;
 326         struct device_dma_parameters dma_parms;
 327         struct bam_chan *channels;
 328         u32 num_channels;
 329
 330         /* execution environment ID, from DT */
 331         u32 ee;
 332
 333         struct clk *bamclk;
 334         int irq;
 335
 336         /* dma start transaction tasklet */
 337         struct tasklet_struct task;
 338 };
 339
 340 /**
 341  * bam_addr - returns BAM register address
 342  * @bdev: bam device
 343  * @pipe: pipe instance (ignored when register doesn't have multiple instances)
 344  * @reg:  register enum
 345  */
 346 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
 347                 enum bam_reg reg)
 348 {
 349         const struct reg_offset_data r = reg_info[reg];
 350
 351         return bdev->regs + r.base_offset +
 352                 r.pipe_mult * pipe +
 353                 r.evnt_mult * pipe +
 354                 r.ee_mult * bdev->ee;
 355 }
 356
 357 /**
 358  * bam_reset_channel - Reset individual BAM DMA channel
 359  * @bchan: bam channel
 360  *
 361  * This function resets a specific BAM channel
 362  */
 363 static void bam_reset_channel(struct bam_chan *bchan)
 364 {
 365         struct bam_device *bdev = bchan->bdev;
 366
 367         lockdep_assert_held(&bchan->vc.lock);
 368
 369         /* reset channel */
 370         writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
 371         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
 372
 373         /* don't allow cpu to reorder BAM register accesses done after this */
 374         wmb();
 375
 376         /* make sure hw is initialized when channel is used the first time  */
 377         bchan->initialized = 0;
 378 }
 379
 380 /**
 381  * bam_chan_init_hw - Initialize channel hardware
 382  * @bchan: bam channel
 383  *
 384  * This function resets and initializes the BAM channel
 385  */
 386 static void bam_chan_init_hw(struct bam_chan *bchan,
 387         enum dma_transfer_direction dir)
 388 {
 389         struct bam_device *bdev = bchan->bdev;
 390         u32 val;
 391
 392         /* Reset the channel to clear internal state of the FIFO */
 393         bam_reset_channel(bchan);
 394
 395         /*
 396          * write out 8 byte aligned address.  We have enough space for this
 397          * because we allocated 1 more descriptor (8 bytes) than we can use
 398          */
 399         writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
 400                         bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
 401         writel_relaxed(BAM_DESC_FIFO_SIZE,
 402                         bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
 403
 404         /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
 405         writel_relaxed(P_DEFAULT_IRQS_EN,
 406                         bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 407
 408         /* unmask the specific pipe and EE combo */
 409         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 410         val |= BIT(bchan->id);
 411         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 412
 413         /* don't allow cpu to reorder the channel enable done below */
 414         wmb();
 415
 416         /* set fixed direction and mode, then enable channel */
 417         val = P_EN | P_SYS_MODE;
 418         if (dir == DMA_DEV_TO_MEM)
 419                 val |= P_DIRECTION;
 420
 421         writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
 422
 423         bchan->initialized = 1;
 424
 425         /* init FIFO pointers */
 426         bchan->head = 0;
 427         bchan->tail = 0;
 428 }
 429
 430 /**
 431  * bam_alloc_chan - Allocate channel resources for DMA channel.
 432  * @chan: specified channel
 433  *
 434  * This function allocates the FIFO descriptor memory
 435  */
 436 static int bam_alloc_chan(struct dma_chan *chan)
 437 {
 438         struct bam_chan *bchan = to_bam_chan(chan);
 439         struct bam_device *bdev = bchan->bdev;
 440
 441         if (bchan->fifo_virt)
 442                 return 0;
 443
 444         /* allocate FIFO descriptor space, but only if necessary */
 445         bchan->fifo_virt = dma_alloc_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE,
 446                                 &bchan->fifo_phys, GFP_KERNEL);
 447
 448         if (!bchan->fifo_virt) {
 449                 dev_err(bdev->dev, "Failed to allocate desc fifo\n");
 450                 return -ENOMEM;
 451         }
 452
 453         return 0;
 454 }
 455
 456 /**
 457  * bam_free_chan - Frees dma resources associated with specific channel
 458  * @chan: specified channel
 459  *
 460  * Free the allocated fifo descriptor memory and channel resources
 461  *
 462  */
 463 static void bam_free_chan(struct dma_chan *chan)
 464 {
 465         struct bam_chan *bchan = to_bam_chan(chan);
 466         struct bam_device *bdev = bchan->bdev;
 467         u32 val;
 468         unsigned long flags;
 469
 470         vchan_free_chan_resources(to_virt_chan(chan));
 471
 472         if (bchan->curr_txd) {
 473                 dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
 474                 return;
 475         }
 476
 477         spin_lock_irqsave(&bchan->vc.lock, flags);
 478         bam_reset_channel(bchan);
 479         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 480
 481         dma_free_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
 482                                 bchan->fifo_phys);
 483         bchan->fifo_virt = NULL;
 484
 485         /* mask irq for pipe/channel */
 486         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 487         val &= ~BIT(bchan->id);
 488         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 489
 490         /* disable irq */
 491         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 492 }
 493
 494 /**
 495  * bam_slave_config - set slave configuration for channel
 496  * @chan: dma channel
 497  * @cfg: slave configuration
 498  *
 499  * Sets slave configuration for channel
 500  *
 501  */
 502 static void bam_slave_config(struct bam_chan *bchan,
 503                 struct dma_slave_config *cfg)
 504 {
 505         memcpy(&bchan->slave, cfg, sizeof(*cfg));
 506         bchan->reconfigure = 1;
 507 }
 508
 509 /**
 510  * bam_prep_slave_sg - Prep slave sg transaction
 511  *
 512  * @chan: dma channel
 513  * @sgl: scatter gather list
 514  * @sg_len: length of sg
 515  * @direction: DMA transfer direction
 516  * @flags: DMA flags
 517  * @context: transfer context (unused)
 518  */
 519 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
 520         struct scatterlist *sgl, unsigned int sg_len,
 521         enum dma_transfer_direction direction, unsigned long flags,
 522         void *context)
 523 {
 524         struct bam_chan *bchan = to_bam_chan(chan);
 525         struct bam_device *bdev = bchan->bdev;
 526         struct bam_async_desc *async_desc;
 527         struct scatterlist *sg;
 528         u32 i;
 529         struct bam_desc_hw *desc;
 530         unsigned int num_alloc = 0;
 531
 532
 533         if (!is_slave_direction(direction)) {
 534                 dev_err(bdev->dev, "invalid dma direction\n");
 535                 return NULL;
 536         }
 537
 538         /* calculate number of required entries */
 539         for_each_sg(sgl, sg, sg_len, i)
 540                 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_MAX_DATA_SIZE);
 541
 542         /* allocate enough room to accomodate the number of entries */
 543         async_desc = kzalloc(sizeof(*async_desc) +
 544                         (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
 545
 546         if (!async_desc)
 547                 goto err_out;
 548
 549         if (flags & DMA_PREP_FENCE)
 550                 async_desc->flags |= DESC_FLAG_NWD;
 551
 552         if (flags & DMA_PREP_INTERRUPT)
 553                 async_desc->flags |= DESC_FLAG_EOT;
 554         else
 555                 async_desc->flags |= DESC_FLAG_INT;
 556
 557         async_desc->num_desc = num_alloc;
 558         async_desc->curr_desc = async_desc->desc;
 559         async_desc->dir = direction;
 560
 561         /* fill in temporary descriptors */
 562         desc = async_desc->desc;
 563         for_each_sg(sgl, sg, sg_len, i) {
 564                 unsigned int remainder = sg_dma_len(sg);
 565                 unsigned int curr_offset = 0;
 566
 567                 do {
 568                         desc->addr = sg_dma_address(sg) + curr_offset;
 569
 570                         if (remainder > BAM_MAX_DATA_SIZE) {
 571                                 desc->size = BAM_MAX_DATA_SIZE;
 572                                 remainder -= BAM_MAX_DATA_SIZE;
 573                                 curr_offset += BAM_MAX_DATA_SIZE;
 574                         } else {
 575                                 desc->size = remainder;
 576                                 remainder = 0;
 577                         }
 578
 579                         async_desc->length += desc->size;
 580                         desc++;
 581                 } while (remainder > 0);
 582         }
 583
 584         return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
 585
 586 err_out:
 587         kfree(async_desc);
 588         return NULL;
 589 }
 590
 591 /**
 592  * bam_dma_terminate_all - terminate all transactions on a channel
 593  * @bchan: bam dma channel
 594  *
 595  * Dequeues and frees all transactions
 596  * No callbacks are done
 597  *
 598  */
 599 static void bam_dma_terminate_all(struct bam_chan *bchan)
 600 {
 601         unsigned long flag;
 602         LIST_HEAD(head);
 603
 604         /* remove all transactions, including active transaction */
 605         spin_lock_irqsave(&bchan->vc.lock, flag);
 606         if (bchan->curr_txd) {
 607                 list_add(&bchan->curr_txd->vd.node, &bchan->vc.desc_issued);
 608                 bchan->curr_txd = NULL;
 609         }
 610
 611         vchan_get_all_descriptors(&bchan->vc, &head);
 612         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 613
 614         vchan_dma_desc_free_list(&bchan->vc, &head);
 615 }
 616
 617 /**
 618  * bam_control - DMA device control
 619  * @chan: dma channel
 620  * @cmd: control cmd
 621  * @arg: cmd argument
 622  *
 623  * Perform DMA control command
 624  *
 625  */
 626 static int bam_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 627         unsigned long arg)
 628 {
 629         struct bam_chan *bchan = to_bam_chan(chan);
 630         struct bam_device *bdev = bchan->bdev;
 631         int ret = 0;
 632         unsigned long flag;
 633
 634         switch (cmd) {
 635         case DMA_PAUSE:
 636                 spin_lock_irqsave(&bchan->vc.lock, flag);
 637                 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
 638                 bchan->paused = 1;
 639                 spin_unlock_irqrestore(&bchan->vc.lock, flag);
 640                 break;
 641
 642         case DMA_RESUME:
 643                 spin_lock_irqsave(&bchan->vc.lock, flag);
 644                 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
 645                 bchan->paused = 0;
 646                 spin_unlock_irqrestore(&bchan->vc.lock, flag);
 647                 break;
 648
 649         case DMA_TERMINATE_ALL:
 650                 bam_dma_terminate_all(bchan);
 651                 break;
 652
 653         case DMA_SLAVE_CONFIG:
 654                 spin_lock_irqsave(&bchan->vc.lock, flag);
 655                 bam_slave_config(bchan, (struct dma_slave_config *)arg);
 656                 spin_unlock_irqrestore(&bchan->vc.lock, flag);
 657                 break;
 658
 659         default:
 660                 ret = -ENXIO;
 661                 break;
 662         }
 663
 664         return ret;
 665 }
 666
 667 /**
 668  * process_channel_irqs - processes the channel interrupts
 669  * @bdev: bam controller
 670  *
 671  * This function processes the channel interrupts
 672  *
 673  */
 674 static u32 process_channel_irqs(struct bam_device *bdev)
 675 {
 676         u32 i, srcs, pipe_stts;
 677         unsigned long flags;
 678         struct bam_async_desc *async_desc;
 679
 680         srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
 681
 682         /* return early if no pipe/channel interrupts are present */
 683         if (!(srcs & P_IRQ))
 684                 return srcs;
 685
 686         for (i = 0; i < bdev->num_channels; i++) {
 687                 struct bam_chan *bchan = &bdev->channels[i];
 688
 689                 if (!(srcs & BIT(i)))
 690                         continue;
 691
 692                 /* clear pipe irq */
 693                 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS));
 694
 695                 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
 696
 697                 spin_lock_irqsave(&bchan->vc.lock, flags);
 698                 async_desc = bchan->curr_txd;
 699
 700                 if (async_desc) {
 701                         async_desc->num_desc -= async_desc->xfer_len;
 702                         async_desc->curr_desc += async_desc->xfer_len;
 703                         bchan->curr_txd = NULL;
 704
 705                         /* manage FIFO */
 706                         bchan->head += async_desc->xfer_len;
 707                         bchan->head %= MAX_DESCRIPTORS;
 708
 709                         /*
 710                          * if complete, process cookie.  Otherwise
 711                          * push back to front of desc_issued so that
 712                          * it gets restarted by the tasklet
 713                          */
 714                         if (!async_desc->num_desc)
 715                                 vchan_cookie_complete(&async_desc->vd);
 716                         else
 717                                 list_add(&async_desc->vd.node,
 718                                         &bchan->vc.desc_issued);
 719                 }
 720
 721                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
 722         }
 723
 724         return srcs;
 725 }
 726
 727 /**
 728  * bam_dma_irq - irq handler for bam controller
 729  * @irq: IRQ of interrupt
 730  * @data: callback data
 731  *
 732  * IRQ handler for the bam controller
 733  */
 734 static irqreturn_t bam_dma_irq(int irq, void *data)
 735 {
 736         struct bam_device *bdev = data;
 737         u32 clr_mask = 0, srcs = 0;
 738
 739         srcs |= process_channel_irqs(bdev);
 740
 741         /* kick off tasklet to start next dma transfer */
 742         if (srcs & P_IRQ)
 743                 tasklet_schedule(&bdev->task);
 744
 745         if (srcs & BAM_IRQ)
 746                 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
 747
 748         /* don't allow reorder of the various accesses to the BAM registers */
 749         mb();
 750
 751         writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
 752
 753         return IRQ_HANDLED;
 754 }
 755
 756 /**
 757  * bam_tx_status - returns status of transaction
 758  * @chan: dma channel
 759  * @cookie: transaction cookie
 760  * @txstate: DMA transaction state
 761  *
 762  * Return status of dma transaction
 763  */
 764 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 765                 struct dma_tx_state *txstate)
 766 {
 767         struct bam_chan *bchan = to_bam_chan(chan);
 768         struct virt_dma_desc *vd;
 769         int ret;
 770         size_t residue = 0;
 771         unsigned int i;
 772         unsigned long flags;
 773
 774         ret = dma_cookie_status(chan, cookie, txstate);
 775         if (ret == DMA_COMPLETE)
 776                 return ret;
 777
 778         if (!txstate)
 779                 return bchan->paused ? DMA_PAUSED : ret;
 780
 781         spin_lock_irqsave(&bchan->vc.lock, flags);
 782         vd = vchan_find_desc(&bchan->vc, cookie);
 783         if (vd)
 784                 residue = container_of(vd, struct bam_async_desc, vd)->length;
 785         else if (bchan->curr_txd && bchan->curr_txd->vd.tx.cookie == cookie)
 786                 for (i = 0; i < bchan->curr_txd->num_desc; i++)
 787                         residue += bchan->curr_txd->curr_desc[i].size;
 788
 789         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 790
 791         dma_set_residue(txstate, residue);
 792
 793         if (ret == DMA_IN_PROGRESS && bchan->paused)
 794                 ret = DMA_PAUSED;
 795
 796         return ret;
 797 }
 798
 799 /**
 800  * bam_apply_new_config
 801  * @bchan: bam dma channel
 802  * @dir: DMA direction
 803  */
 804 static void bam_apply_new_config(struct bam_chan *bchan,
 805         enum dma_transfer_direction dir)
 806 {
 807         struct bam_device *bdev = bchan->bdev;
 808         u32 maxburst;
 809
 810         if (dir == DMA_DEV_TO_MEM)
 811                 maxburst = bchan->slave.src_maxburst;
 812         else
 813                 maxburst = bchan->slave.dst_maxburst;
 814
 815         writel_relaxed(maxburst, bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
 816
 817         bchan->reconfigure = 0;
 818 }
 819
 820 /**
 821  * bam_start_dma - start next transaction
 822  * @bchan - bam dma channel
 823  */
 824 static void bam_start_dma(struct bam_chan *bchan)
 825 {
 826         struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
 827         struct bam_device *bdev = bchan->bdev;
 828         struct bam_async_desc *async_desc;
 829         struct bam_desc_hw *desc;
 830         struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
 831                                         sizeof(struct bam_desc_hw));
 832
 833         lockdep_assert_held(&bchan->vc.lock);
 834
 835         if (!vd)
 836                 return;
 837
 838         list_del(&vd->node);
 839
 840         async_desc = container_of(vd, struct bam_async_desc, vd);
 841         bchan->curr_txd = async_desc;
 842
 843         /* on first use, initialize the channel hardware */
 844         if (!bchan->initialized)
 845                 bam_chan_init_hw(bchan, async_desc->dir);
 846
 847         /* apply new slave config changes, if necessary */
 848         if (bchan->reconfigure)
 849                 bam_apply_new_config(bchan, async_desc->dir);
 850
 851         desc = bchan->curr_txd->curr_desc;
 852
 853         if (async_desc->num_desc > MAX_DESCRIPTORS)
 854                 async_desc->xfer_len = MAX_DESCRIPTORS;
 855         else
 856                 async_desc->xfer_len = async_desc->num_desc;
 857
 858         /* set any special flags on the last descriptor */
 859         if (async_desc->num_desc == async_desc->xfer_len)
 860                 desc[async_desc->xfer_len - 1].flags = async_desc->flags;
 861         else
 862                 desc[async_desc->xfer_len - 1].flags |= DESC_FLAG_INT;
 863
 864         if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
 865                 u32 partial = MAX_DESCRIPTORS - bchan->tail;
 866
 867                 memcpy(&fifo[bchan->tail], desc,
 868                                 partial * sizeof(struct bam_desc_hw));
 869                 memcpy(fifo, &desc[partial], (async_desc->xfer_len - partial) *
 870                                 sizeof(struct bam_desc_hw));
 871         } else {
 872                 memcpy(&fifo[bchan->tail], desc,
 873                         async_desc->xfer_len * sizeof(struct bam_desc_hw));
 874         }
 875
 876         bchan->tail += async_desc->xfer_len;
 877         bchan->tail %= MAX_DESCRIPTORS;
 878
 879         /* ensure descriptor writes and dma start not reordered */
 880         wmb();
 881         writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
 882                         bam_addr(bdev, bchan->id, BAM_P_EVNT_REG));
 883 }
 884
 885 /**
 886  * dma_tasklet - DMA IRQ tasklet
 887  * @data: tasklet argument (bam controller structure)
 888  *
 889  * Sets up next DMA operation and then processes all completed transactions
 890  */
 891 static void dma_tasklet(unsigned long data)
 892 {
 893         struct bam_device *bdev = (struct bam_device *)data;
 894         struct bam_chan *bchan;
 895         unsigned long flags;
 896         unsigned int i;
 897
 898         /* go through the channels and kick off transactions */
 899         for (i = 0; i < bdev->num_channels; i++) {
 900                 bchan = &bdev->channels[i];
 901                 spin_lock_irqsave(&bchan->vc.lock, flags);
 902
 903                 if (!list_empty(&bchan->vc.desc_issued) && !bchan->curr_txd)
 904                         bam_start_dma(bchan);
 905                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
 906         }
 907 }
 908
 909 /**
 910  * bam_issue_pending - starts pending transactions
 911  * @chan: dma channel
 912  *
 913  * Calls tasklet directly which in turn starts any pending transactions
 914  */
 915 static void bam_issue_pending(struct dma_chan *chan)
 916 {
 917         struct bam_chan *bchan = to_bam_chan(chan);
 918         unsigned long flags;
 919
 920         spin_lock_irqsave(&bchan->vc.lock, flags);
 921
 922         /* if work pending and idle, start a transaction */
 923         if (vchan_issue_pending(&bchan->vc) && !bchan->curr_txd)
 924                 bam_start_dma(bchan);
 925
 926         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 927 }
 928
 929 /**
 930  * bam_dma_free_desc - free descriptor memory
 931  * @vd: virtual descriptor
 932  *
 933  */
 934 static void bam_dma_free_desc(struct virt_dma_desc *vd)
 935 {
 936         struct bam_async_desc *async_desc = container_of(vd,
 937                         struct bam_async_desc, vd);
 938
 939         kfree(async_desc);
 940 }
 941
 942 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
 943                 struct of_dma *of)
 944 {
 945         struct bam_device *bdev = container_of(of->of_dma_data,
 946                                         struct bam_device, common);
 947         unsigned int request;
 948
 949         if (dma_spec->args_count != 1)
 950                 return NULL;
 951
 952         request = dma_spec->args[0];
 953         if (request >= bdev->num_channels)
 954                 return NULL;
 955
 956         return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
 957 }
 958
 959 /**
 960  * bam_init
 961  * @bdev: bam device
 962  *
 963  * Initialization helper for global bam registers
 964  */
 965 static int bam_init(struct bam_device *bdev)
 966 {
 967         u32 val;
 968
 969         /* read revision and configuration information */
 970         val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)) >> NUM_EES_SHIFT;
 971         val &= NUM_EES_MASK;
 972
 973         /* check that configured EE is within range */
 974         if (bdev->ee >= val)
 975                 return -EINVAL;
 976
 977         val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
 978         bdev->num_channels = val & BAM_NUM_PIPES_MASK;
 979
 980         /* s/w reset bam */
 981         /* after reset all pipes are disabled and idle */
 982         val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
 983         val |= BAM_SW_RST;
 984         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
 985         val &= ~BAM_SW_RST;
 986         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
 987
 988         /* make sure previous stores are visible before enabling BAM */
 989         wmb();
 990
 991         /* enable bam */
 992         val |= BAM_EN;
 993         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
 994
 995         /* set descriptor threshhold, start with 4 bytes */
 996         writel_relaxed(DEFAULT_CNT_THRSHLD,
 997                         bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
 998
 999         /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
1000         writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
1001
1002         /* enable irqs for errors */
1003         writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
1004                         bam_addr(bdev, 0, BAM_IRQ_EN));
1005
1006         /* unmask global bam interrupt */
1007         writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1008
1009         return 0;
1010 }
1011
1012 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1013         u32 index)
1014 {
1015         bchan->id = index;
1016         bchan->bdev = bdev;
1017
1018         vchan_init(&bchan->vc, &bdev->common);
1019         bchan->vc.desc_free = bam_dma_free_desc;
1020 }
1021
1022 static int bam_dma_probe(struct platform_device *pdev)
1023 {
1024         struct bam_device *bdev;
1025         struct resource *iores;
1026         int ret, i;
1027
1028         bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
1029         if (!bdev)
1030                 return -ENOMEM;
1031
1032         bdev->dev = &pdev->dev;
1033
1034         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1035         bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1036         if (IS_ERR(bdev->regs))
1037                 return PTR_ERR(bdev->regs);
1038
1039         bdev->irq = platform_get_irq(pdev, 0);
1040         if (bdev->irq < 0)
1041                 return bdev->irq;
1042
1043         ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
1044         if (ret) {
1045                 dev_err(bdev->dev, "Execution environment unspecified\n");
1046                 return ret;
1047         }
1048
1049         bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
1050         if (IS_ERR(bdev->bamclk))
1051                 return PTR_ERR(bdev->bamclk);
1052
1053         ret = clk_prepare_enable(bdev->bamclk);
1054         if (ret) {
1055                 dev_err(bdev->dev, "failed to prepare/enable clock\n");
1056                 return ret;
1057         }
1058
1059         ret = bam_init(bdev);
1060         if (ret)
1061                 goto err_disable_clk;
1062
1063         tasklet_init(&bdev->task, dma_tasklet, (unsigned long)bdev);
1064
1065         bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
1066                                 sizeof(*bdev->channels), GFP_KERNEL);
1067
1068         if (!bdev->channels) {
1069                 ret = -ENOMEM;
1070                 goto err_disable_clk;
1071         }
1072
1073         /* allocate and initialize channels */
1074         INIT_LIST_HEAD(&bdev->common.channels);
1075
1076         for (i = 0; i < bdev->num_channels; i++)
1077                 bam_channel_init(bdev, &bdev->channels[i], i);
1078
1079         ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
1080                         IRQF_TRIGGER_HIGH, "bam_dma", bdev);
1081         if (ret)
1082                 goto err_disable_clk;
1083
1084         /* set max dma segment size */
1085         bdev->common.dev = bdev->dev;
1086         bdev->common.dev->dma_parms = &bdev->dma_parms;
1087         ret = dma_set_max_seg_size(bdev->common.dev, BAM_MAX_DATA_SIZE);
1088         if (ret) {
1089                 dev_err(bdev->dev, "cannot set maximum segment size\n");
1090                 goto err_disable_clk;
1091         }
1092
1093         platform_set_drvdata(pdev, bdev);
1094
1095         /* set capabilities */
1096         dma_cap_zero(bdev->common.cap_mask);
1097         dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
1098
1099         /* initialize dmaengine apis */
1100         bdev->common.device_alloc_chan_resources = bam_alloc_chan;
1101         bdev->common.device_free_chan_resources = bam_free_chan;
1102         bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
1103         bdev->common.device_control = bam_control;
1104         bdev->common.device_issue_pending = bam_issue_pending;
1105         bdev->common.device_tx_status = bam_tx_status;
1106         bdev->common.dev = bdev->dev;
1107
1108         ret = dma_async_device_register(&bdev->common);
1109         if (ret) {
1110                 dev_err(bdev->dev, "failed to register dma async device\n");
1111                 goto err_disable_clk;
1112         }
1113
1114         ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
1115                                         &bdev->common);
1116         if (ret)
1117                 goto err_unregister_dma;
1118
1119         return 0;
1120
1121 err_unregister_dma:
1122         dma_async_device_unregister(&bdev->common);
1123 err_disable_clk:
1124         clk_disable_unprepare(bdev->bamclk);
1125         return ret;
1126 }
1127
1128 static int bam_dma_remove(struct platform_device *pdev)
1129 {
1130         struct bam_device *bdev = platform_get_drvdata(pdev);
1131         u32 i;
1132
1133         of_dma_controller_free(pdev->dev.of_node);
1134         dma_async_device_unregister(&bdev->common);
1135
1136         /* mask all interrupts for this execution environment */
1137         writel_relaxed(0, bam_addr(bdev, 0,  BAM_IRQ_SRCS_MSK_EE));
1138
1139         devm_free_irq(bdev->dev, bdev->irq, bdev);
1140
1141         for (i = 0; i < bdev->num_channels; i++) {
1142                 bam_dma_terminate_all(&bdev->channels[i]);
1143                 tasklet_kill(&bdev->channels[i].vc.task);
1144
1145                 dma_free_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE,
1146                         bdev->channels[i].fifo_virt,
1147                         bdev->channels[i].fifo_phys);
1148         }
1149
1150         tasklet_kill(&bdev->task);
1151
1152         clk_disable_unprepare(bdev->bamclk);
1153
1154         return 0;
1155 }
1156
1157 static const struct of_device_id bam_of_match[] = {
1158         { .compatible = "qcom,bam-v1.4.0", },
1159         {}
1160 };
1161 MODULE_DEVICE_TABLE(of, bam_of_match);
1162
1163 static struct platform_driver bam_dma_driver = {
1164         .probe = bam_dma_probe,
1165         .remove = bam_dma_remove,
1166         .driver = {
1167                 .name = "bam-dma-engine",
1168                 .of_match_table = bam_of_match,
1169         },
1170 };
1171
1172 module_platform_driver(bam_dma_driver);
1173
1174 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
1175 MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
1176 MODULE_LICENSE("GPL v2");