2 * Renesas SuperH DMA Engine support
4 * base is drivers/dma/flsdma.c
6 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
10 * This is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * - DMA of SuperH does not have Hardware DMA chain mode.
16 * - MAX DMA size is 16MB.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
28 #include <asm/dma-sh.h>
31 /* DMA descriptor control */
32 enum sh_dmae_desc_status {
36 DESC_COMPLETED, /* completed, have to call callback */
37 DESC_WAITING, /* callback called, waiting for ack / re-submit */
40 #define NR_DESCS_PER_CHANNEL 32
42 * Define the default configuration for dual address memory-memory transfer.
43 * The 0x400 value represents auto-request, external->external.
45 * And this driver set 4byte burst mode.
46 * If you want to change mode, you need to change RS_DEFAULT of value.
47 * (ex 1byte burst mode -> (RS_DUAL & ~TS_32)
49 #define RS_DEFAULT (RS_DUAL)
51 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
52 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
54 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
56 #define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id])
57 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
59 ctrl_outl(data, SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
62 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
64 return ctrl_inl(SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
68 * Reset DMA controller
70 * SH7780 has two DMAOR register
72 static void sh_dmae_ctl_stop(int id)
74 unsigned short dmaor = dmaor_read_reg(id);
76 dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
77 dmaor_write_reg(id, dmaor);
80 static int sh_dmae_rst(int id)
85 dmaor = dmaor_read_reg(id) | DMAOR_INIT;
87 dmaor_write_reg(id, dmaor);
88 if (dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF)) {
89 pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
95 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
97 u32 chcr = sh_dmae_readl(sh_chan, CHCR);
99 if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
100 return true; /* working */
102 return false; /* waiting */
105 static unsigned int ts_shift[] = TS_SHIFT;
106 static inline unsigned int calc_xmit_shift(u32 chcr)
108 int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
109 ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
111 return ts_shift[cnt];
114 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
116 sh_dmae_writel(sh_chan, hw->sar, SAR);
117 sh_dmae_writel(sh_chan, hw->dar, DAR);
118 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
121 static void dmae_start(struct sh_dmae_chan *sh_chan)
123 u32 chcr = sh_dmae_readl(sh_chan, CHCR);
125 chcr |= CHCR_DE | CHCR_IE;
126 sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
129 static void dmae_halt(struct sh_dmae_chan *sh_chan)
131 u32 chcr = sh_dmae_readl(sh_chan, CHCR);
133 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
134 sh_dmae_writel(sh_chan, chcr, CHCR);
137 static void dmae_init(struct sh_dmae_chan *sh_chan)
139 u32 chcr = RS_DEFAULT; /* default is DUAL mode */
140 sh_chan->xmit_shift = calc_xmit_shift(chcr);
141 sh_dmae_writel(sh_chan, chcr, CHCR);
144 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
146 /* When DMA was working, can not set data to CHCR */
147 if (dmae_is_busy(sh_chan))
150 sh_chan->xmit_shift = calc_xmit_shift(val);
151 sh_dmae_writel(sh_chan, val, CHCR);
156 #define DMARS_SHIFT 8
157 #define DMARS_CHAN_MSK 0x01
158 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
163 if (dmae_is_busy(sh_chan))
166 if (sh_chan->id & DMARS_CHAN_MSK)
170 /* DMA0RS0 - DMA0RS2 */
171 addr = SH_DMARS_BASE0 + (sh_chan->id / 2) * 4;
172 #ifdef SH_DMARS_BASE1
173 else if (sh_chan->id < 12)
174 /* DMA1RS0 - DMA1RS2 */
175 addr = SH_DMARS_BASE1 + ((sh_chan->id - 6) / 2) * 4;
180 ctrl_outw((val << shift) | (ctrl_inw(addr) & (0xFF00 >> shift)), addr);
185 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
187 struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
188 struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
189 dma_async_tx_callback callback = tx->callback;
192 spin_lock_bh(&sh_chan->desc_lock);
194 cookie = sh_chan->common.cookie;
199 sh_chan->common.cookie = cookie;
202 /* Mark all chunks of this descriptor as submitted, move to the queue */
203 list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
205 * All chunks are on the global ld_free, so, we have to find
206 * the end of the chain ourselves
208 if (chunk != desc && (chunk->mark == DESC_IDLE ||
209 chunk->async_tx.cookie > 0 ||
210 chunk->async_tx.cookie == -EBUSY ||
211 &chunk->node == &sh_chan->ld_free))
213 chunk->mark = DESC_SUBMITTED;
214 /* Callback goes to the last chunk */
215 chunk->async_tx.callback = NULL;
216 chunk->cookie = cookie;
217 list_move_tail(&chunk->node, &sh_chan->ld_queue);
221 last->async_tx.callback = callback;
222 last->async_tx.callback_param = tx->callback_param;
224 dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
225 tx->cookie, &last->async_tx, sh_chan->id,
226 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
228 spin_unlock_bh(&sh_chan->desc_lock);
233 /* Called with desc_lock held */
234 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
236 struct sh_desc *desc;
238 list_for_each_entry(desc, &sh_chan->ld_free, node)
239 if (desc->mark != DESC_PREPARED) {
240 BUG_ON(desc->mark != DESC_IDLE);
241 list_del(&desc->node);
248 static struct sh_dmae_slave_config *sh_dmae_find_slave(
249 struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id)
251 struct dma_device *dma_dev = sh_chan->common.device;
252 struct sh_dmae_device *shdev = container_of(dma_dev,
253 struct sh_dmae_device, common);
254 struct sh_dmae_pdata *pdata = &shdev->pdata;
257 if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
260 for (i = 0; i < pdata->config_num; i++)
261 if (pdata->config[i].slave_id == slave_id)
262 return pdata->config + i;
267 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
269 struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
270 struct sh_desc *desc;
271 struct sh_dmae_slave *param = chan->private;
274 * This relies on the guarantee from dmaengine that alloc_chan_resources
275 * never runs concurrently with itself or free_chan_resources.
278 struct sh_dmae_slave_config *cfg;
280 cfg = sh_dmae_find_slave(sh_chan, param->slave_id);
284 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used))
289 dmae_set_dmars(sh_chan, cfg->mid_rid);
290 dmae_set_chcr(sh_chan, cfg->chcr);
292 if ((sh_dmae_readl(sh_chan, CHCR) & 0x700) != 0x400)
293 dmae_set_chcr(sh_chan, RS_DEFAULT);
296 spin_lock_bh(&sh_chan->desc_lock);
297 while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
298 spin_unlock_bh(&sh_chan->desc_lock);
299 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
301 spin_lock_bh(&sh_chan->desc_lock);
304 dma_async_tx_descriptor_init(&desc->async_tx,
306 desc->async_tx.tx_submit = sh_dmae_tx_submit;
307 desc->mark = DESC_IDLE;
309 spin_lock_bh(&sh_chan->desc_lock);
310 list_add(&desc->node, &sh_chan->ld_free);
311 sh_chan->descs_allocated++;
313 spin_unlock_bh(&sh_chan->desc_lock);
315 return sh_chan->descs_allocated;
319 * sh_dma_free_chan_resources - Free all resources of the channel.
321 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
323 struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
324 struct sh_desc *desc, *_desc;
329 /* Prepared and not submitted descriptors can still be on the queue */
330 if (!list_empty(&sh_chan->ld_queue))
331 sh_dmae_chan_ld_cleanup(sh_chan, true);
334 /* The caller is holding dma_list_mutex */
335 struct sh_dmae_slave *param = chan->private;
336 clear_bit(param->slave_id, sh_dmae_slave_used);
339 spin_lock_bh(&sh_chan->desc_lock);
341 list_splice_init(&sh_chan->ld_free, &list);
342 sh_chan->descs_allocated = 0;
344 spin_unlock_bh(&sh_chan->desc_lock);
346 list_for_each_entry_safe(desc, _desc, &list, node)
351 * sh_dmae_add_desc - get, set up and return one transfer descriptor
352 * @sh_chan: DMA channel
353 * @flags: DMA transfer flags
354 * @dest: destination DMA address, incremented when direction equals
355 * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
356 * @src: source DMA address, incremented when direction equals
357 * DMA_TO_DEVICE or DMA_BIDIRECTIONAL
358 * @len: DMA transfer length
359 * @first: if NULL, set to the current descriptor and cookie set to -EBUSY
360 * @direction: needed for slave DMA to decide which address to keep constant,
361 * equals DMA_BIDIRECTIONAL for MEMCPY
362 * Returns 0 or an error
363 * Locks: called with desc_lock held
365 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
366 unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
367 struct sh_desc **first, enum dma_data_direction direction)
375 /* Allocate the link descriptor from the free list */
376 new = sh_dmae_get_desc(sh_chan);
378 dev_err(sh_chan->dev, "No free link descriptor available\n");
382 copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
386 new->hw.tcr = copy_size;
390 new->async_tx.cookie = -EBUSY;
393 /* Other desc - invisible to the user */
394 new->async_tx.cookie = -EINVAL;
397 dev_dbg(sh_chan->dev,
398 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
399 copy_size, *len, *src, *dest, &new->async_tx,
400 new->async_tx.cookie, sh_chan->xmit_shift);
402 new->mark = DESC_PREPARED;
403 new->async_tx.flags = flags;
404 new->direction = direction;
407 if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
409 if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
416 * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
418 * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
419 * converted to scatter-gather to guarantee consistent locking and a correct
420 * list manipulation. For slave DMA direction carries the usual meaning, and,
421 * logically, the SG list is RAM and the addr variable contains slave address,
422 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
423 * and the SG list contains only one element and points at the source buffer.
425 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
426 struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
427 enum dma_data_direction direction, unsigned long flags)
429 struct scatterlist *sg;
430 struct sh_desc *first = NULL, *new = NULL /* compiler... */;
438 for_each_sg(sgl, sg, sg_len, i)
439 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
440 (SH_DMA_TCR_MAX + 1);
442 /* Have to lock the whole loop to protect against concurrent release */
443 spin_lock_bh(&sh_chan->desc_lock);
447 * first descriptor is what user is dealing with in all API calls, its
448 * cookie is at first set to -EBUSY, at tx-submit to a positive
450 * if more than one chunk is needed further chunks have cookie = -EINVAL
451 * the last chunk, if not equal to the first, has cookie = -ENOSPC
452 * all chunks are linked onto the tx_list head with their .node heads
453 * only during this function, then they are immediately spliced
454 * back onto the free list in form of a chain
456 for_each_sg(sgl, sg, sg_len, i) {
457 dma_addr_t sg_addr = sg_dma_address(sg);
458 size_t len = sg_dma_len(sg);
464 dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
465 i, sg, len, (unsigned long long)sg_addr);
467 if (direction == DMA_FROM_DEVICE)
468 new = sh_dmae_add_desc(sh_chan, flags,
469 &sg_addr, addr, &len, &first,
472 new = sh_dmae_add_desc(sh_chan, flags,
473 addr, &sg_addr, &len, &first,
478 new->chunks = chunks--;
479 list_add_tail(&new->node, &tx_list);
484 new->async_tx.cookie = -ENOSPC;
486 /* Put them back on the free list, so, they don't get lost */
487 list_splice_tail(&tx_list, &sh_chan->ld_free);
489 spin_unlock_bh(&sh_chan->desc_lock);
491 return &first->async_tx;
494 list_for_each_entry(new, &tx_list, node)
495 new->mark = DESC_IDLE;
496 list_splice(&tx_list, &sh_chan->ld_free);
498 spin_unlock_bh(&sh_chan->desc_lock);
503 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
504 struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
505 size_t len, unsigned long flags)
507 struct sh_dmae_chan *sh_chan;
508 struct scatterlist sg;
513 chan->private = NULL;
515 sh_chan = to_sh_chan(chan);
517 sg_init_table(&sg, 1);
518 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
519 offset_in_page(dma_src));
520 sg_dma_address(&sg) = dma_src;
521 sg_dma_len(&sg) = len;
523 return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
527 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
528 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
529 enum dma_data_direction direction, unsigned long flags)
531 struct sh_dmae_slave *param;
532 struct sh_dmae_chan *sh_chan;
537 sh_chan = to_sh_chan(chan);
538 param = chan->private;
540 /* Someone calling slave DMA on a public channel? */
541 if (!param || !sg_len) {
542 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
543 __func__, param, sg_len, param ? param->slave_id : -1);
548 * if (param != NULL), this is a successfully requested slave channel,
549 * therefore param->config != NULL too.
551 return sh_dmae_prep_sg(sh_chan, sgl, sg_len, ¶m->config->addr,
555 static void sh_dmae_terminate_all(struct dma_chan *chan)
557 struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
562 sh_dmae_chan_ld_cleanup(sh_chan, true);
565 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
567 struct sh_desc *desc, *_desc;
568 /* Is the "exposed" head of a chain acked? */
569 bool head_acked = false;
570 dma_cookie_t cookie = 0;
571 dma_async_tx_callback callback = NULL;
574 spin_lock_bh(&sh_chan->desc_lock);
575 list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
576 struct dma_async_tx_descriptor *tx = &desc->async_tx;
578 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
579 BUG_ON(desc->mark != DESC_SUBMITTED &&
580 desc->mark != DESC_COMPLETED &&
581 desc->mark != DESC_WAITING);
584 * queue is ordered, and we use this loop to (1) clean up all
585 * completed descriptors, and to (2) update descriptor flags of
586 * any chunks in a (partially) completed chain
588 if (!all && desc->mark == DESC_SUBMITTED &&
589 desc->cookie != cookie)
595 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
596 if (sh_chan->completed_cookie != desc->cookie - 1)
597 dev_dbg(sh_chan->dev,
598 "Completing cookie %d, expected %d\n",
600 sh_chan->completed_cookie + 1);
601 sh_chan->completed_cookie = desc->cookie;
604 /* Call callback on the last chunk */
605 if (desc->mark == DESC_COMPLETED && tx->callback) {
606 desc->mark = DESC_WAITING;
607 callback = tx->callback;
608 param = tx->callback_param;
609 dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
610 tx->cookie, tx, sh_chan->id);
611 BUG_ON(desc->chunks != 1);
615 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
616 if (desc->mark == DESC_COMPLETED) {
617 BUG_ON(tx->cookie < 0);
618 desc->mark = DESC_WAITING;
620 head_acked = async_tx_test_ack(tx);
622 switch (desc->mark) {
624 desc->mark = DESC_WAITING;
628 async_tx_ack(&desc->async_tx);
632 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
635 if (((desc->mark == DESC_COMPLETED ||
636 desc->mark == DESC_WAITING) &&
637 async_tx_test_ack(&desc->async_tx)) || all) {
638 /* Remove from ld_queue list */
639 desc->mark = DESC_IDLE;
640 list_move(&desc->node, &sh_chan->ld_free);
643 spin_unlock_bh(&sh_chan->desc_lock);
652 * sh_chan_ld_cleanup - Clean up link descriptors
654 * This function cleans up the ld_queue of DMA channel.
656 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
658 while (__ld_cleanup(sh_chan, all))
662 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
666 spin_lock_bh(&sh_chan->desc_lock);
668 if (dmae_is_busy(sh_chan)) {
669 spin_unlock_bh(&sh_chan->desc_lock);
673 /* Find the first not transferred desciptor */
674 list_for_each_entry(sd, &sh_chan->ld_queue, node)
675 if (sd->mark == DESC_SUBMITTED) {
676 /* Get the ld start address from ld_queue */
677 dmae_set_reg(sh_chan, &sd->hw);
682 spin_unlock_bh(&sh_chan->desc_lock);
685 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
687 struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
688 sh_chan_xfer_ld_queue(sh_chan);
691 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
696 struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
697 dma_cookie_t last_used;
698 dma_cookie_t last_complete;
700 sh_dmae_chan_ld_cleanup(sh_chan, false);
702 last_used = chan->cookie;
703 last_complete = sh_chan->completed_cookie;
704 BUG_ON(last_complete < 0);
707 *done = last_complete;
712 return dma_async_is_complete(cookie, last_complete, last_used);
715 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
717 irqreturn_t ret = IRQ_NONE;
718 struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
719 u32 chcr = sh_dmae_readl(sh_chan, CHCR);
721 if (chcr & CHCR_TE) {
726 tasklet_schedule(&sh_chan->tasklet);
732 #if defined(CONFIG_CPU_SH4)
733 static irqreturn_t sh_dmae_err(int irq, void *data)
736 struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
739 if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
740 int __maybe_unused cnt = 0;
742 #if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
747 if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
755 /* reset dma controller */
756 err = sh_dmae_rst(0);
760 if (shdev->pdata.mode & SHDMA_DMAOR1) {
761 err = sh_dmae_rst(1);
772 static void dmae_do_tasklet(unsigned long data)
774 struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
775 struct sh_desc *desc;
776 u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
777 u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
779 spin_lock(&sh_chan->desc_lock);
780 list_for_each_entry(desc, &sh_chan->ld_queue, node) {
781 if (desc->mark == DESC_SUBMITTED &&
782 ((desc->direction == DMA_FROM_DEVICE &&
783 (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
784 (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
785 dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
786 desc->async_tx.cookie, &desc->async_tx,
788 desc->mark = DESC_COMPLETED;
792 spin_unlock(&sh_chan->desc_lock);
795 sh_chan_xfer_ld_queue(sh_chan);
796 sh_dmae_chan_ld_cleanup(sh_chan, false);
799 static unsigned int get_dmae_irq(unsigned int id)
801 unsigned int irq = 0;
802 if (id < ARRAY_SIZE(dmte_irq_map))
803 irq = dmte_irq_map[id];
807 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
810 unsigned int irq = get_dmae_irq(id);
811 unsigned long irqflags = IRQF_DISABLED;
812 struct sh_dmae_chan *new_sh_chan;
815 new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
817 dev_err(shdev->common.dev,
818 "No free memory for allocating dma channels!\n");
822 new_sh_chan->dev = shdev->common.dev;
823 new_sh_chan->id = id;
825 /* Init DMA tasklet */
826 tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
827 (unsigned long)new_sh_chan);
829 /* Init the channel */
830 dmae_init(new_sh_chan);
832 spin_lock_init(&new_sh_chan->desc_lock);
834 /* Init descripter manage list */
835 INIT_LIST_HEAD(&new_sh_chan->ld_queue);
836 INIT_LIST_HEAD(&new_sh_chan->ld_free);
838 /* copy struct dma_device */
839 new_sh_chan->common.device = &shdev->common;
841 /* Add the channel to DMA device channel list */
842 list_add_tail(&new_sh_chan->common.device_node,
843 &shdev->common.channels);
844 shdev->common.chancnt++;
846 if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
847 irqflags = IRQF_SHARED;
848 #if defined(DMTE6_IRQ)
849 if (irq >= DMTE6_IRQ)
856 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
857 "sh-dmae%d", new_sh_chan->id);
859 /* set up channel irq */
860 err = request_irq(irq, &sh_dmae_interrupt, irqflags,
861 new_sh_chan->dev_id, new_sh_chan);
863 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
864 "with return %d\n", id, err);
868 shdev->chan[id] = new_sh_chan;
872 /* remove from dmaengine device node */
873 list_del(&new_sh_chan->common.device_node);
878 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
882 for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
883 if (shdev->chan[i]) {
884 struct sh_dmae_chan *shchan = shdev->chan[i];
885 if (!(shdev->pdata.mode & SHDMA_MIX_IRQ))
886 free_irq(dmte_irq_map[i], shchan);
888 list_del(&shchan->common.device_node);
890 shdev->chan[i] = NULL;
893 shdev->common.chancnt = 0;
896 static int __init sh_dmae_probe(struct platform_device *pdev)
898 int err = 0, cnt, ecnt;
899 unsigned long irqflags = IRQF_DISABLED;
900 #if defined(CONFIG_CPU_SH4)
901 int eirq[] = { DMAE0_IRQ,
902 #if defined(DMAE1_IRQ)
907 struct sh_dmae_device *shdev;
909 /* get platform data */
910 if (!pdev->dev.platform_data)
913 shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
915 dev_err(&pdev->dev, "No enough memory\n");
920 memcpy(&shdev->pdata, pdev->dev.platform_data,
921 sizeof(struct sh_dmae_pdata));
923 /* reset dma controller */
924 err = sh_dmae_rst(0);
928 /* SH7780/85/23 has DMAOR1 */
929 if (shdev->pdata.mode & SHDMA_DMAOR1) {
930 err = sh_dmae_rst(1);
935 INIT_LIST_HEAD(&shdev->common.channels);
937 dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
938 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
940 shdev->common.device_alloc_chan_resources
941 = sh_dmae_alloc_chan_resources;
942 shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
943 shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
944 shdev->common.device_is_tx_complete = sh_dmae_is_complete;
945 shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
947 /* Compulsory for DMA_SLAVE fields */
948 shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
949 shdev->common.device_terminate_all = sh_dmae_terminate_all;
951 shdev->common.dev = &pdev->dev;
952 /* Default transfer size of 32 bytes requires 32-byte alignment */
953 shdev->common.copy_align = 5;
955 #if defined(CONFIG_CPU_SH4)
956 /* Non Mix IRQ mode SH7722/SH7730 etc... */
957 if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
958 irqflags = IRQF_SHARED;
960 #if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
965 for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) {
966 err = request_irq(eirq[ecnt], sh_dmae_err, irqflags,
967 "DMAC Address Error", shdev);
969 dev_err(&pdev->dev, "DMA device request_irq"
970 "error (irq %d) with return %d\n",
975 #endif /* CONFIG_CPU_SH4 */
977 /* Create DMA Channel */
978 for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) {
979 err = sh_dmae_chan_probe(shdev, cnt);
984 platform_set_drvdata(pdev, shdev);
985 dma_async_device_register(&shdev->common);
990 sh_dmae_chan_remove(shdev);
993 for (ecnt-- ; ecnt >= 0; ecnt--)
994 free_irq(eirq[ecnt], shdev);
1002 static int __exit sh_dmae_remove(struct platform_device *pdev)
1004 struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1006 dma_async_device_unregister(&shdev->common);
1008 if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
1009 free_irq(DMTE0_IRQ, shdev);
1010 #if defined(DMTE6_IRQ)
1011 free_irq(DMTE6_IRQ, shdev);
1015 /* channel data remove */
1016 sh_dmae_chan_remove(shdev);
1018 if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) {
1019 free_irq(DMAE0_IRQ, shdev);
1020 #if defined(DMAE1_IRQ)
1021 free_irq(DMAE1_IRQ, shdev);
1029 static void sh_dmae_shutdown(struct platform_device *pdev)
1031 struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1032 sh_dmae_ctl_stop(0);
1033 if (shdev->pdata.mode & SHDMA_DMAOR1)
1034 sh_dmae_ctl_stop(1);
1037 static struct platform_driver sh_dmae_driver = {
1038 .remove = __exit_p(sh_dmae_remove),
1039 .shutdown = sh_dmae_shutdown,
1041 .name = "sh-dma-engine",
1045 static int __init sh_dmae_init(void)
1047 return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1049 module_init(sh_dmae_init);
1051 static void __exit sh_dmae_exit(void)
1053 platform_driver_unregister(&sh_dmae_driver);
1055 module_exit(sh_dmae_exit);
1057 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1058 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1059 MODULE_LICENSE("GPL");