drivers/dma/ste_dma40.c

   1 /*
   2  * Copyright (C) Ericsson AB 2007-2008
   3  * Copyright (C) ST-Ericsson SA 2008-2010
   4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/dma-mapping.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/export.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/err.h>
  20 #include <linux/of.h>
  21 #include <linux/of_dma.h>
  22 #include <linux/amba/bus.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/platform_data/dma-ste-dma40.h>
  25
  26 #include "dmaengine.h"
  27 #include "ste_dma40_ll.h"
  28
  29 #define D40_NAME "dma40"
  30
  31 #define D40_PHY_CHAN -1
  32
  33 /* For masking out/in 2 bit channel positions */
  34 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
  35 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  36
  37 /* Maximum iterations taken before giving up suspending a channel */
  38 #define D40_SUSPEND_MAX_IT 500
  39
  40 /* Milliseconds */
  41 #define DMA40_AUTOSUSPEND_DELAY 100
  42
  43 /* Hardware requirement on LCLA alignment */
  44 #define LCLA_ALIGNMENT 0x40000
  45
  46 /* Max number of links per event group */
  47 #define D40_LCLA_LINK_PER_EVENT_GRP 128
  48 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
  49
  50 /* Max number of logical channels per physical channel */
  51 #define D40_MAX_LOG_CHAN_PER_PHY 32
  52
  53 /* Attempts before giving up to trying to get pages that are aligned */
  54 #define MAX_LCLA_ALLOC_ATTEMPTS 256
  55
  56 /* Bit markings for allocation map */
  57 #define D40_ALLOC_FREE          BIT(31)
  58 #define D40_ALLOC_PHY           BIT(30)
  59 #define D40_ALLOC_LOG_FREE      0
  60
  61 #define D40_MEMCPY_MAX_CHANS    8
  62
  63 /* Reserved event lines for memcpy only. */
  64 #define DB8500_DMA_MEMCPY_EV_0  51
  65 #define DB8500_DMA_MEMCPY_EV_1  56
  66 #define DB8500_DMA_MEMCPY_EV_2  57
  67 #define DB8500_DMA_MEMCPY_EV_3  58
  68 #define DB8500_DMA_MEMCPY_EV_4  59
  69 #define DB8500_DMA_MEMCPY_EV_5  60
  70
  71 static int dma40_memcpy_channels[] = {
  72         DB8500_DMA_MEMCPY_EV_0,
  73         DB8500_DMA_MEMCPY_EV_1,
  74         DB8500_DMA_MEMCPY_EV_2,
  75         DB8500_DMA_MEMCPY_EV_3,
  76         DB8500_DMA_MEMCPY_EV_4,
  77         DB8500_DMA_MEMCPY_EV_5,
  78 };
  79
  80 /* Default configuration for physcial memcpy */
  81 struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  82         .mode = STEDMA40_MODE_PHYSICAL,
  83         .dir = DMA_MEM_TO_MEM,
  84
  85         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  86         .src_info.psize = STEDMA40_PSIZE_PHY_1,
  87         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  88
  89         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  90         .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  91         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  92 };
  93
  94 /* Default configuration for logical memcpy */
  95 struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  96         .mode = STEDMA40_MODE_LOGICAL,
  97         .dir = DMA_MEM_TO_MEM,
  98
  99         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 100         .src_info.psize = STEDMA40_PSIZE_LOG_1,
 101         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 102
 103         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 104         .dst_info.psize = STEDMA40_PSIZE_LOG_1,
 105         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 106 };
 107
 108 /**
 109  * enum 40_command - The different commands and/or statuses.
 110  *
 111  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
 112  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
 113  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
 114  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
 115  */
 116 enum d40_command {
 117         D40_DMA_STOP            = 0,
 118         D40_DMA_RUN             = 1,
 119         D40_DMA_SUSPEND_REQ     = 2,
 120         D40_DMA_SUSPENDED       = 3
 121 };
 122
 123 /*
 124  * enum d40_events - The different Event Enables for the event lines.
 125  *
 126  * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
 127  * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
 128  * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
 129  * @D40_ROUND_EVENTLINE: Status check for event line.
 130  */
 131
 132 enum d40_events {
 133         D40_DEACTIVATE_EVENTLINE        = 0,
 134         D40_ACTIVATE_EVENTLINE          = 1,
 135         D40_SUSPEND_REQ_EVENTLINE       = 2,
 136         D40_ROUND_EVENTLINE             = 3
 137 };
 138
 139 /*
 140  * These are the registers that has to be saved and later restored
 141  * when the DMA hw is powered off.
 142  * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
 143  */
 144 static u32 d40_backup_regs[] = {
 145         D40_DREG_LCPA,
 146         D40_DREG_LCLA,
 147         D40_DREG_PRMSE,
 148         D40_DREG_PRMSO,
 149         D40_DREG_PRMOE,
 150         D40_DREG_PRMOO,
 151 };
 152
 153 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
 154
 155 /*
 156  * since 9540 and 8540 has the same HW revision
 157  * use v4a for 9540 or ealier
 158  * use v4b for 8540 or later
 159  * HW revision:
 160  * DB8500ed has revision 0
 161  * DB8500v1 has revision 2
 162  * DB8500v2 has revision 3
 163  * AP9540v1 has revision 4
 164  * DB8540v1 has revision 4
 165  * TODO: Check if all these registers have to be saved/restored on dma40 v4a
 166  */
 167 static u32 d40_backup_regs_v4a[] = {
 168         D40_DREG_PSEG1,
 169         D40_DREG_PSEG2,
 170         D40_DREG_PSEG3,
 171         D40_DREG_PSEG4,
 172         D40_DREG_PCEG1,
 173         D40_DREG_PCEG2,
 174         D40_DREG_PCEG3,
 175         D40_DREG_PCEG4,
 176         D40_DREG_RSEG1,
 177         D40_DREG_RSEG2,
 178         D40_DREG_RSEG3,
 179         D40_DREG_RSEG4,
 180         D40_DREG_RCEG1,
 181         D40_DREG_RCEG2,
 182         D40_DREG_RCEG3,
 183         D40_DREG_RCEG4,
 184 };
 185
 186 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
 187
 188 static u32 d40_backup_regs_v4b[] = {
 189         D40_DREG_CPSEG1,
 190         D40_DREG_CPSEG2,
 191         D40_DREG_CPSEG3,
 192         D40_DREG_CPSEG4,
 193         D40_DREG_CPSEG5,
 194         D40_DREG_CPCEG1,
 195         D40_DREG_CPCEG2,
 196         D40_DREG_CPCEG3,
 197         D40_DREG_CPCEG4,
 198         D40_DREG_CPCEG5,
 199         D40_DREG_CRSEG1,
 200         D40_DREG_CRSEG2,
 201         D40_DREG_CRSEG3,
 202         D40_DREG_CRSEG4,
 203         D40_DREG_CRSEG5,
 204         D40_DREG_CRCEG1,
 205         D40_DREG_CRCEG2,
 206         D40_DREG_CRCEG3,
 207         D40_DREG_CRCEG4,
 208         D40_DREG_CRCEG5,
 209 };
 210
 211 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
 212
 213 static u32 d40_backup_regs_chan[] = {
 214         D40_CHAN_REG_SSCFG,
 215         D40_CHAN_REG_SSELT,
 216         D40_CHAN_REG_SSPTR,
 217         D40_CHAN_REG_SSLNK,
 218         D40_CHAN_REG_SDCFG,
 219         D40_CHAN_REG_SDELT,
 220         D40_CHAN_REG_SDPTR,
 221         D40_CHAN_REG_SDLNK,
 222 };
 223
 224 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
 225                              BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
 226
 227 /**
 228  * struct d40_interrupt_lookup - lookup table for interrupt handler
 229  *
 230  * @src: Interrupt mask register.
 231  * @clr: Interrupt clear register.
 232  * @is_error: true if this is an error interrupt.
 233  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
 234  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
 235  */
 236 struct d40_interrupt_lookup {
 237         u32 src;
 238         u32 clr;
 239         bool is_error;
 240         int offset;
 241 };
 242
 243
 244 static struct d40_interrupt_lookup il_v4a[] = {
 245         {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
 246         {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
 247         {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
 248         {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
 249         {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
 250         {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
 251         {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
 252         {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
 253         {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
 254         {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
 255 };
 256
 257 static struct d40_interrupt_lookup il_v4b[] = {
 258         {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false,  0},
 259         {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
 260         {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
 261         {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
 262         {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
 263         {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true,   0},
 264         {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true,  32},
 265         {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true,  64},
 266         {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true,  96},
 267         {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true,  128},
 268         {D40_DREG_CPCTIS,  D40_DREG_CPCICR,  false, D40_PHY_CHAN},
 269         {D40_DREG_CPCEIS,  D40_DREG_CPCICR,  true,  D40_PHY_CHAN},
 270 };
 271
 272 /**
 273  * struct d40_reg_val - simple lookup struct
 274  *
 275  * @reg: The register.
 276  * @val: The value that belongs to the register in reg.
 277  */
 278 struct d40_reg_val {
 279         unsigned int reg;
 280         unsigned int val;
 281 };
 282
 283 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
 284         /* Clock every part of the DMA block from start */
 285         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
 286
 287         /* Interrupts on all logical channels */
 288         { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
 289         { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
 290         { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
 291         { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
 292         { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
 293         { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
 294         { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
 295         { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
 296         { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
 297         { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
 298         { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
 299         { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
 300 };
 301 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
 302         /* Clock every part of the DMA block from start */
 303         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
 304
 305         /* Interrupts on all logical channels */
 306         { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
 307         { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
 308         { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
 309         { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
 310         { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
 311         { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
 312         { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
 313         { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
 314         { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
 315         { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
 316         { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
 317         { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
 318         { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
 319         { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
 320         { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
 321 };
 322
 323 /**
 324  * struct d40_lli_pool - Structure for keeping LLIs in memory
 325  *
 326  * @base: Pointer to memory area when the pre_alloc_lli's are not large
 327  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
 328  * pre_alloc_lli is used.
 329  * @dma_addr: DMA address, if mapped
 330  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
 331  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
 332  * one buffer to one buffer.
 333  */
 334 struct d40_lli_pool {
 335         void    *base;
 336         int      size;
 337         dma_addr_t      dma_addr;
 338         /* Space for dst and src, plus an extra for padding */
 339         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
 340 };
 341
 342 /**
 343  * struct d40_desc - A descriptor is one DMA job.
 344  *
 345  * @lli_phy: LLI settings for physical channel. Both src and dst=
 346  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
 347  * lli_len equals one.
 348  * @lli_log: Same as above but for logical channels.
 349  * @lli_pool: The pool with two entries pre-allocated.
 350  * @lli_len: Number of llis of current descriptor.
 351  * @lli_current: Number of transferred llis.
 352  * @lcla_alloc: Number of LCLA entries allocated.
 353  * @txd: DMA engine struct. Used for among other things for communication
 354  * during a transfer.
 355  * @node: List entry.
 356  * @is_in_client_list: true if the client owns this descriptor.
 357  * @cyclic: true if this is a cyclic job
 358  *
 359  * This descriptor is used for both logical and physical transfers.
 360  */
 361 struct d40_desc {
 362         /* LLI physical */
 363         struct d40_phy_lli_bidir         lli_phy;
 364         /* LLI logical */
 365         struct d40_log_lli_bidir         lli_log;
 366
 367         struct d40_lli_pool              lli_pool;
 368         int                              lli_len;
 369         int                              lli_current;
 370         int                              lcla_alloc;
 371
 372         struct dma_async_tx_descriptor   txd;
 373         struct list_head                 node;
 374
 375         bool                             is_in_client_list;
 376         bool                             cyclic;
 377 };
 378
 379 /**
 380  * struct d40_lcla_pool - LCLA pool settings and data.
 381  *
 382  * @base: The virtual address of LCLA. 18 bit aligned.
 383  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
 384  * This pointer is only there for clean-up on error.
 385  * @pages: The number of pages needed for all physical channels.
 386  * Only used later for clean-up on error
 387  * @lock: Lock to protect the content in this struct.
 388  * @alloc_map: big map over which LCLA entry is own by which job.
 389  */
 390 struct d40_lcla_pool {
 391         void            *base;
 392         dma_addr_t      dma_addr;
 393         void            *base_unaligned;
 394         int              pages;
 395         spinlock_t       lock;
 396         struct d40_desc **alloc_map;
 397 };
 398
 399 /**
 400  * struct d40_phy_res - struct for handling eventlines mapped to physical
 401  * channels.
 402  *
 403  * @lock: A lock protection this entity.
 404  * @reserved: True if used by secure world or otherwise.
 405  * @num: The physical channel number of this entity.
 406  * @allocated_src: Bit mapped to show which src event line's are mapped to
 407  * this physical channel. Can also be free or physically allocated.
 408  * @allocated_dst: Same as for src but is dst.
 409  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
 410  * event line number.
 411  * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
 412  */
 413 struct d40_phy_res {
 414         spinlock_t lock;
 415         bool       reserved;
 416         int        num;
 417         u32        allocated_src;
 418         u32        allocated_dst;
 419         bool       use_soft_lli;
 420 };
 421
 422 struct d40_base;
 423
 424 /**
 425  * struct d40_chan - Struct that describes a channel.
 426  *
 427  * @lock: A spinlock to protect this struct.
 428  * @log_num: The logical number, if any of this channel.
 429  * @pending_tx: The number of pending transfers. Used between interrupt handler
 430  * and tasklet.
 431  * @busy: Set to true when transfer is ongoing on this channel.
 432  * @phy_chan: Pointer to physical channel which this instance runs on. If this
 433  * point is NULL, then the channel is not allocated.
 434  * @chan: DMA engine handle.
 435  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
 436  * transfer and call client callback.
 437  * @client: Cliented owned descriptor list.
 438  * @pending_queue: Submitted jobs, to be issued by issue_pending()
 439  * @active: Active descriptor.
 440  * @done: Completed jobs
 441  * @queue: Queued jobs.
 442  * @prepare_queue: Prepared jobs.
 443  * @dma_cfg: The client configuration of this dma channel.
 444  * @configured: whether the dma_cfg configuration is valid
 445  * @base: Pointer to the device instance struct.
 446  * @src_def_cfg: Default cfg register setting for src.
 447  * @dst_def_cfg: Default cfg register setting for dst.
 448  * @log_def: Default logical channel settings.
 449  * @lcpa: Pointer to dst and src lcpa settings.
 450  * @runtime_addr: runtime configured address.
 451  * @runtime_direction: runtime configured direction.
 452  *
 453  * This struct can either "be" a logical or a physical channel.
 454  */
 455 struct d40_chan {
 456         spinlock_t                       lock;
 457         int                              log_num;
 458         int                              pending_tx;
 459         bool                             busy;
 460         struct d40_phy_res              *phy_chan;
 461         struct dma_chan                  chan;
 462         struct tasklet_struct            tasklet;
 463         struct list_head                 client;
 464         struct list_head                 pending_queue;
 465         struct list_head                 active;
 466         struct list_head                 done;
 467         struct list_head                 queue;
 468         struct list_head                 prepare_queue;
 469         struct stedma40_chan_cfg         dma_cfg;
 470         bool                             configured;
 471         struct d40_base                 *base;
 472         /* Default register configurations */
 473         u32                              src_def_cfg;
 474         u32                              dst_def_cfg;
 475         struct d40_def_lcsp              log_def;
 476         struct d40_log_lli_full         *lcpa;
 477         /* Runtime reconfiguration */
 478         dma_addr_t                      runtime_addr;
 479         enum dma_transfer_direction     runtime_direction;
 480 };
 481
 482 /**
 483  * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
 484  * controller
 485  *
 486  * @backup: the pointer to the registers address array for backup
 487  * @backup_size: the size of the registers address array for backup
 488  * @realtime_en: the realtime enable register
 489  * @realtime_clear: the realtime clear register
 490  * @high_prio_en: the high priority enable register
 491  * @high_prio_clear: the high priority clear register
 492  * @interrupt_en: the interrupt enable register
 493  * @interrupt_clear: the interrupt clear register
 494  * @il: the pointer to struct d40_interrupt_lookup
 495  * @il_size: the size of d40_interrupt_lookup array
 496  * @init_reg: the pointer to the struct d40_reg_val
 497  * @init_reg_size: the size of d40_reg_val array
 498  */
 499 struct d40_gen_dmac {
 500         u32                             *backup;
 501         u32                              backup_size;
 502         u32                              realtime_en;
 503         u32                              realtime_clear;
 504         u32                              high_prio_en;
 505         u32                              high_prio_clear;
 506         u32                              interrupt_en;
 507         u32                              interrupt_clear;
 508         struct d40_interrupt_lookup     *il;
 509         u32                              il_size;
 510         struct d40_reg_val              *init_reg;
 511         u32                              init_reg_size;
 512 };
 513
 514 /**
 515  * struct d40_base - The big global struct, one for each probe'd instance.
 516  *
 517  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
 518  * @execmd_lock: Lock for execute command usage since several channels share
 519  * the same physical register.
 520  * @dev: The device structure.
 521  * @virtbase: The virtual base address of the DMA's register.
 522  * @rev: silicon revision detected.
 523  * @clk: Pointer to the DMA clock structure.
 524  * @phy_start: Physical memory start of the DMA registers.
 525  * @phy_size: Size of the DMA register map.
 526  * @irq: The IRQ number.
 527  * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
 528  * transfers).
 529  * @num_phy_chans: The number of physical channels. Read from HW. This
 530  * is the number of available channels for this driver, not counting "Secure
 531  * mode" allocated physical channels.
 532  * @num_log_chans: The number of logical channels. Calculated from
 533  * num_phy_chans.
 534  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
 535  * @dma_slave: dma_device channels that can do only do slave transfers.
 536  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
 537  * @phy_chans: Room for all possible physical channels in system.
 538  * @log_chans: Room for all possible logical channels in system.
 539  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
 540  * to log_chans entries.
 541  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
 542  * to phy_chans entries.
 543  * @plat_data: Pointer to provided platform_data which is the driver
 544  * configuration.
 545  * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
 546  * @phy_res: Vector containing all physical channels.
 547  * @lcla_pool: lcla pool settings and data.
 548  * @lcpa_base: The virtual mapped address of LCPA.
 549  * @phy_lcpa: The physical address of the LCPA.
 550  * @lcpa_size: The size of the LCPA area.
 551  * @desc_slab: cache for descriptors.
 552  * @reg_val_backup: Here the values of some hardware registers are stored
 553  * before the DMA is powered off. They are restored when the power is back on.
 554  * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
 555  * later
 556  * @reg_val_backup_chan: Backup data for standard channel parameter registers.
 557  * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
 558  * @initialized: true if the dma has been initialized
 559  * @gen_dmac: the struct for generic registers values to represent u8500/8540
 560  * DMA controller
 561  */
 562 struct d40_base {
 563         spinlock_t                       interrupt_lock;
 564         spinlock_t                       execmd_lock;
 565         struct device                    *dev;
 566         void __iomem                     *virtbase;
 567         u8                                rev:4;
 568         struct clk                       *clk;
 569         phys_addr_t                       phy_start;
 570         resource_size_t                   phy_size;
 571         int                               irq;
 572         int                               num_memcpy_chans;
 573         int                               num_phy_chans;
 574         int                               num_log_chans;
 575         struct device_dma_parameters      dma_parms;
 576         struct dma_device                 dma_both;
 577         struct dma_device                 dma_slave;
 578         struct dma_device                 dma_memcpy;
 579         struct d40_chan                  *phy_chans;
 580         struct d40_chan                  *log_chans;
 581         struct d40_chan                 **lookup_log_chans;
 582         struct d40_chan                 **lookup_phy_chans;
 583         struct stedma40_platform_data    *plat_data;
 584         struct regulator                 *lcpa_regulator;
 585         /* Physical half channels */
 586         struct d40_phy_res               *phy_res;
 587         struct d40_lcla_pool              lcla_pool;
 588         void                             *lcpa_base;
 589         dma_addr_t                        phy_lcpa;
 590         resource_size_t                   lcpa_size;
 591         struct kmem_cache                *desc_slab;
 592         u32                               reg_val_backup[BACKUP_REGS_SZ];
 593         u32                               reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
 594         u32                              *reg_val_backup_chan;
 595         u16                               gcc_pwr_off_mask;
 596         bool                              initialized;
 597         struct d40_gen_dmac               gen_dmac;
 598 };
 599
 600 static struct device *chan2dev(struct d40_chan *d40c)
 601 {
 602         return &d40c->chan.dev->device;
 603 }
 604
 605 static bool chan_is_physical(struct d40_chan *chan)
 606 {
 607         return chan->log_num == D40_PHY_CHAN;
 608 }
 609
 610 static bool chan_is_logical(struct d40_chan *chan)
 611 {
 612         return !chan_is_physical(chan);
 613 }
 614
 615 static void __iomem *chan_base(struct d40_chan *chan)
 616 {
 617         return chan->base->virtbase + D40_DREG_PCBASE +
 618                chan->phy_chan->num * D40_DREG_PCDELTA;
 619 }
 620
 621 #define d40_err(dev, format, arg...)            \
 622         dev_err(dev, "[%s] " format, __func__, ## arg)
 623
 624 #define chan_err(d40c, format, arg...)          \
 625         d40_err(chan2dev(d40c), format, ## arg)
 626
 627 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
 628                               int lli_len)
 629 {
 630         bool is_log = chan_is_logical(d40c);
 631         u32 align;
 632         void *base;
 633
 634         if (is_log)
 635                 align = sizeof(struct d40_log_lli);
 636         else
 637                 align = sizeof(struct d40_phy_lli);
 638
 639         if (lli_len == 1) {
 640                 base = d40d->lli_pool.pre_alloc_lli;
 641                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
 642                 d40d->lli_pool.base = NULL;
 643         } else {
 644                 d40d->lli_pool.size = lli_len * 2 * align;
 645
 646                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
 647                 d40d->lli_pool.base = base;
 648
 649                 if (d40d->lli_pool.base == NULL)
 650                         return -ENOMEM;
 651         }
 652
 653         if (is_log) {
 654                 d40d->lli_log.src = PTR_ALIGN(base, align);
 655                 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
 656
 657                 d40d->lli_pool.dma_addr = 0;
 658         } else {
 659                 d40d->lli_phy.src = PTR_ALIGN(base, align);
 660                 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
 661
 662                 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
 663                                                          d40d->lli_phy.src,
 664                                                          d40d->lli_pool.size,
 665                                                          DMA_TO_DEVICE);
 666
 667                 if (dma_mapping_error(d40c->base->dev,
 668                                       d40d->lli_pool.dma_addr)) {
 669                         kfree(d40d->lli_pool.base);
 670                         d40d->lli_pool.base = NULL;
 671                         d40d->lli_pool.dma_addr = 0;
 672                         return -ENOMEM;
 673                 }
 674         }
 675
 676         return 0;
 677 }
 678
 679 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
 680 {
 681         if (d40d->lli_pool.dma_addr)
 682                 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
 683                                  d40d->lli_pool.size, DMA_TO_DEVICE);
 684
 685         kfree(d40d->lli_pool.base);
 686         d40d->lli_pool.base = NULL;
 687         d40d->lli_pool.size = 0;
 688         d40d->lli_log.src = NULL;
 689         d40d->lli_log.dst = NULL;
 690         d40d->lli_phy.src = NULL;
 691         d40d->lli_phy.dst = NULL;
 692 }
 693
 694 static int d40_lcla_alloc_one(struct d40_chan *d40c,
 695                               struct d40_desc *d40d)
 696 {
 697         unsigned long flags;
 698         int i;
 699         int ret = -EINVAL;
 700
 701         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 702
 703         /*
 704          * Allocate both src and dst at the same time, therefore the half
 705          * start on 1 since 0 can't be used since zero is used as end marker.
 706          */
 707         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 708                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
 709
 710                 if (!d40c->base->lcla_pool.alloc_map[idx]) {
 711                         d40c->base->lcla_pool.alloc_map[idx] = d40d;
 712                         d40d->lcla_alloc++;
 713                         ret = i;
 714                         break;
 715                 }
 716         }
 717
 718         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 719
 720         return ret;
 721 }
 722
 723 static int d40_lcla_free_all(struct d40_chan *d40c,
 724                              struct d40_desc *d40d)
 725 {
 726         unsigned long flags;
 727         int i;
 728         int ret = -EINVAL;
 729
 730         if (chan_is_physical(d40c))
 731                 return 0;
 732
 733         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 734
 735         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 736                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
 737
 738                 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
 739                         d40c->base->lcla_pool.alloc_map[idx] = NULL;
 740                         d40d->lcla_alloc--;
 741                         if (d40d->lcla_alloc == 0) {
 742                                 ret = 0;
 743                                 break;
 744                         }
 745                 }
 746         }
 747
 748         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 749
 750         return ret;
 751
 752 }
 753
 754 static void d40_desc_remove(struct d40_desc *d40d)
 755 {
 756         list_del(&d40d->node);
 757 }
 758
 759 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
 760 {
 761         struct d40_desc *desc = NULL;
 762
 763         if (!list_empty(&d40c->client)) {
 764                 struct d40_desc *d;
 765                 struct d40_desc *_d;
 766
 767                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
 768                         if (async_tx_test_ack(&d->txd)) {
 769                                 d40_desc_remove(d);
 770                                 desc = d;
 771                                 memset(desc, 0, sizeof(*desc));
 772                                 break;
 773                         }
 774                 }
 775         }
 776
 777         if (!desc)
 778                 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
 779
 780         if (desc)
 781                 INIT_LIST_HEAD(&desc->node);
 782
 783         return desc;
 784 }
 785
 786 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
 787 {
 788
 789         d40_pool_lli_free(d40c, d40d);
 790         d40_lcla_free_all(d40c, d40d);
 791         kmem_cache_free(d40c->base->desc_slab, d40d);
 792 }
 793
 794 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
 795 {
 796         list_add_tail(&desc->node, &d40c->active);
 797 }
 798
 799 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
 800 {
 801         struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
 802         struct d40_phy_lli *lli_src = desc->lli_phy.src;
 803         void __iomem *base = chan_base(chan);
 804
 805         writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
 806         writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
 807         writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
 808         writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
 809
 810         writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
 811         writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
 812         writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
 813         writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
 814 }
 815
 816 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
 817 {
 818         list_add_tail(&desc->node, &d40c->done);
 819 }
 820
 821 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
 822 {
 823         struct d40_lcla_pool *pool = &chan->base->lcla_pool;
 824         struct d40_log_lli_bidir *lli = &desc->lli_log;
 825         int lli_current = desc->lli_current;
 826         int lli_len = desc->lli_len;
 827         bool cyclic = desc->cyclic;
 828         int curr_lcla = -EINVAL;
 829         int first_lcla = 0;
 830         bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
 831         bool linkback;
 832
 833         /*
 834          * We may have partially running cyclic transfers, in case we did't get
 835          * enough LCLA entries.
 836          */
 837         linkback = cyclic && lli_current == 0;
 838
 839         /*
 840          * For linkback, we need one LCLA even with only one link, because we
 841          * can't link back to the one in LCPA space
 842          */
 843         if (linkback || (lli_len - lli_current > 1)) {
 844                 /*
 845                  * If the channel is expected to use only soft_lli don't
 846                  * allocate a lcla. This is to avoid a HW issue that exists
 847                  * in some controller during a peripheral to memory transfer
 848                  * that uses linked lists.
 849                  */
 850                 if (!(chan->phy_chan->use_soft_lli &&
 851                         chan->dma_cfg.dir == DMA_DEV_TO_MEM))
 852                         curr_lcla = d40_lcla_alloc_one(chan, desc);
 853
 854                 first_lcla = curr_lcla;
 855         }
 856
 857         /*
 858          * For linkback, we normally load the LCPA in the loop since we need to
 859          * link it to the second LCLA and not the first.  However, if we
 860          * couldn't even get a first LCLA, then we have to run in LCPA and
 861          * reload manually.
 862          */
 863         if (!linkback || curr_lcla == -EINVAL) {
 864                 unsigned int flags = 0;
 865
 866                 if (curr_lcla == -EINVAL)
 867                         flags |= LLI_TERM_INT;
 868
 869                 d40_log_lli_lcpa_write(chan->lcpa,
 870                                        &lli->dst[lli_current],
 871                                        &lli->src[lli_current],
 872                                        curr_lcla,
 873                                        flags);
 874                 lli_current++;
 875         }
 876
 877         if (curr_lcla < 0)
 878                 goto out;
 879
 880         for (; lli_current < lli_len; lli_current++) {
 881                 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
 882                                            8 * curr_lcla * 2;
 883                 struct d40_log_lli *lcla = pool->base + lcla_offset;
 884                 unsigned int flags = 0;
 885                 int next_lcla;
 886
 887                 if (lli_current + 1 < lli_len)
 888                         next_lcla = d40_lcla_alloc_one(chan, desc);
 889                 else
 890                         next_lcla = linkback ? first_lcla : -EINVAL;
 891
 892                 if (cyclic || next_lcla == -EINVAL)
 893                         flags |= LLI_TERM_INT;
 894
 895                 if (linkback && curr_lcla == first_lcla) {
 896                         /* First link goes in both LCPA and LCLA */
 897                         d40_log_lli_lcpa_write(chan->lcpa,
 898                                                &lli->dst[lli_current],
 899                                                &lli->src[lli_current],
 900                                                next_lcla, flags);
 901                 }
 902
 903                 /*
 904                  * One unused LCLA in the cyclic case if the very first
 905                  * next_lcla fails...
 906                  */
 907                 d40_log_lli_lcla_write(lcla,
 908                                        &lli->dst[lli_current],
 909                                        &lli->src[lli_current],
 910                                        next_lcla, flags);
 911
 912                 /*
 913                  * Cache maintenance is not needed if lcla is
 914                  * mapped in esram
 915                  */
 916                 if (!use_esram_lcla) {
 917                         dma_sync_single_range_for_device(chan->base->dev,
 918                                                 pool->dma_addr, lcla_offset,
 919                                                 2 * sizeof(struct d40_log_lli),
 920                                                 DMA_TO_DEVICE);
 921                 }
 922                 curr_lcla = next_lcla;
 923
 924                 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
 925                         lli_current++;
 926                         break;
 927                 }
 928         }
 929
 930 out:
 931         desc->lli_current = lli_current;
 932 }
 933
 934 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
 935 {
 936         if (chan_is_physical(d40c)) {
 937                 d40_phy_lli_load(d40c, d40d);
 938                 d40d->lli_current = d40d->lli_len;
 939         } else
 940                 d40_log_lli_to_lcxa(d40c, d40d);
 941 }
 942
 943 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
 944 {
 945         struct d40_desc *d;
 946
 947         if (list_empty(&d40c->active))
 948                 return NULL;
 949
 950         d = list_first_entry(&d40c->active,
 951                              struct d40_desc,
 952                              node);
 953         return d;
 954 }
 955
 956 /* remove desc from current queue and add it to the pending_queue */
 957 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
 958 {
 959         d40_desc_remove(desc);
 960         desc->is_in_client_list = false;
 961         list_add_tail(&desc->node, &d40c->pending_queue);
 962 }
 963
 964 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
 965 {
 966         struct d40_desc *d;
 967
 968         if (list_empty(&d40c->pending_queue))
 969                 return NULL;
 970
 971         d = list_first_entry(&d40c->pending_queue,
 972                              struct d40_desc,
 973                              node);
 974         return d;
 975 }
 976
 977 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
 978 {
 979         struct d40_desc *d;
 980
 981         if (list_empty(&d40c->queue))
 982                 return NULL;
 983
 984         d = list_first_entry(&d40c->queue,
 985                              struct d40_desc,
 986                              node);
 987         return d;
 988 }
 989
 990 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
 991 {
 992         if (list_empty(&d40c->done))
 993                 return NULL;
 994
 995         return list_first_entry(&d40c->done, struct d40_desc, node);
 996 }
 997
 998 static int d40_psize_2_burst_size(bool is_log, int psize)
 999 {
1000         if (is_log) {
1001                 if (psize == STEDMA40_PSIZE_LOG_1)
1002                         return 1;
1003         } else {
1004                 if (psize == STEDMA40_PSIZE_PHY_1)
1005                         return 1;
1006         }
1007
1008         return 2 << psize;
1009 }
1010
1011 /*
1012  * The dma only supports transmitting packages up to
1013  * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1014  *
1015  * Calculate the total number of dma elements required to send the entire sg list.
1016  */
1017 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1018 {
1019         int dmalen;
1020         u32 max_w = max(data_width1, data_width2);
1021         u32 min_w = min(data_width1, data_width2);
1022         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
1023
1024         if (seg_max > STEDMA40_MAX_SEG_SIZE)
1025                 seg_max -= max_w;
1026
1027         if (!IS_ALIGNED(size, max_w))
1028                 return -EINVAL;
1029
1030         if (size <= seg_max)
1031                 dmalen = 1;
1032         else {
1033                 dmalen = size / seg_max;
1034                 if (dmalen * seg_max < size)
1035                         dmalen++;
1036         }
1037         return dmalen;
1038 }
1039
1040 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1041                            u32 data_width1, u32 data_width2)
1042 {
1043         struct scatterlist *sg;
1044         int i;
1045         int len = 0;
1046         int ret;
1047
1048         for_each_sg(sgl, sg, sg_len, i) {
1049                 ret = d40_size_2_dmalen(sg_dma_len(sg),
1050                                         data_width1, data_width2);
1051                 if (ret < 0)
1052                         return ret;
1053                 len += ret;
1054         }
1055         return len;
1056 }
1057
1058
1059 #ifdef CONFIG_PM
1060 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
1061                          u32 *regaddr, int num, bool save)
1062 {
1063         int i;
1064
1065         for (i = 0; i < num; i++) {
1066                 void __iomem *addr = baseaddr + regaddr[i];
1067
1068                 if (save)
1069                         backup[i] = readl_relaxed(addr);
1070                 else
1071                         writel_relaxed(backup[i], addr);
1072         }
1073 }
1074
1075 static void d40_save_restore_registers(struct d40_base *base, bool save)
1076 {
1077         int i;
1078
1079         /* Save/Restore channel specific registers */
1080         for (i = 0; i < base->num_phy_chans; i++) {
1081                 void __iomem *addr;
1082                 int idx;
1083
1084                 if (base->phy_res[i].reserved)
1085                         continue;
1086
1087                 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
1088                 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
1089
1090                 dma40_backup(addr, &base->reg_val_backup_chan[idx],
1091                              d40_backup_regs_chan,
1092                              ARRAY_SIZE(d40_backup_regs_chan),
1093                              save);
1094         }
1095
1096         /* Save/Restore global registers */
1097         dma40_backup(base->virtbase, base->reg_val_backup,
1098                      d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
1099                      save);
1100
1101         /* Save/Restore registers only existing on dma40 v3 and later */
1102         if (base->gen_dmac.backup)
1103                 dma40_backup(base->virtbase, base->reg_val_backup_v4,
1104                              base->gen_dmac.backup,
1105                         base->gen_dmac.backup_size,
1106                         save);
1107 }
1108 #else
1109 static void d40_save_restore_registers(struct d40_base *base, bool save)
1110 {
1111 }
1112 #endif
1113
1114 static int __d40_execute_command_phy(struct d40_chan *d40c,
1115                                      enum d40_command command)
1116 {
1117         u32 status;
1118         int i;
1119         void __iomem *active_reg;
1120         int ret = 0;
1121         unsigned long flags;
1122         u32 wmask;
1123
1124         if (command == D40_DMA_STOP) {
1125                 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1126                 if (ret)
1127                         return ret;
1128         }
1129
1130         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1131
1132         if (d40c->phy_chan->num % 2 == 0)
1133                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1134         else
1135                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1136
1137         if (command == D40_DMA_SUSPEND_REQ) {
1138                 status = (readl(active_reg) &
1139                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1140                         D40_CHAN_POS(d40c->phy_chan->num);
1141
1142                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1143                         goto done;
1144         }
1145
1146         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1147         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1148                active_reg);
1149
1150         if (command == D40_DMA_SUSPEND_REQ) {
1151
1152                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1153                         status = (readl(active_reg) &
1154                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1155                                 D40_CHAN_POS(d40c->phy_chan->num);
1156
1157                         cpu_relax();
1158                         /*
1159                          * Reduce the number of bus accesses while
1160                          * waiting for the DMA to suspend.
1161                          */
1162                         udelay(3);
1163
1164                         if (status == D40_DMA_STOP ||
1165                             status == D40_DMA_SUSPENDED)
1166                                 break;
1167                 }
1168
1169                 if (i == D40_SUSPEND_MAX_IT) {
1170                         chan_err(d40c,
1171                                 "unable to suspend the chl %d (log: %d) status %x\n",
1172                                 d40c->phy_chan->num, d40c->log_num,
1173                                 status);
1174                         dump_stack();
1175                         ret = -EBUSY;
1176                 }
1177
1178         }
1179 done:
1180         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1181         return ret;
1182 }
1183
1184 static void d40_term_all(struct d40_chan *d40c)
1185 {
1186         struct d40_desc *d40d;
1187         struct d40_desc *_d;
1188
1189         /* Release completed descriptors */
1190         while ((d40d = d40_first_done(d40c))) {
1191                 d40_desc_remove(d40d);
1192                 d40_desc_free(d40c, d40d);
1193         }
1194
1195         /* Release active descriptors */
1196         while ((d40d = d40_first_active_get(d40c))) {
1197                 d40_desc_remove(d40d);
1198                 d40_desc_free(d40c, d40d);
1199         }
1200
1201         /* Release queued descriptors waiting for transfer */
1202         while ((d40d = d40_first_queued(d40c))) {
1203                 d40_desc_remove(d40d);
1204                 d40_desc_free(d40c, d40d);
1205         }
1206
1207         /* Release pending descriptors */
1208         while ((d40d = d40_first_pending(d40c))) {
1209                 d40_desc_remove(d40d);
1210                 d40_desc_free(d40c, d40d);
1211         }
1212
1213         /* Release client owned descriptors */
1214         if (!list_empty(&d40c->client))
1215                 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1216                         d40_desc_remove(d40d);
1217                         d40_desc_free(d40c, d40d);
1218                 }
1219
1220         /* Release descriptors in prepare queue */
1221         if (!list_empty(&d40c->prepare_queue))
1222                 list_for_each_entry_safe(d40d, _d,
1223                                          &d40c->prepare_queue, node) {
1224                         d40_desc_remove(d40d);
1225                         d40_desc_free(d40c, d40d);
1226                 }
1227
1228         d40c->pending_tx = 0;
1229 }
1230
1231 static void __d40_config_set_event(struct d40_chan *d40c,
1232                                    enum d40_events event_type, u32 event,
1233                                    int reg)
1234 {
1235         void __iomem *addr = chan_base(d40c) + reg;
1236         int tries;
1237         u32 status;
1238
1239         switch (event_type) {
1240
1241         case D40_DEACTIVATE_EVENTLINE:
1242
1243                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1244                        | ~D40_EVENTLINE_MASK(event), addr);
1245                 break;
1246
1247         case D40_SUSPEND_REQ_EVENTLINE:
1248                 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1249                           D40_EVENTLINE_POS(event);
1250
1251                 if (status == D40_DEACTIVATE_EVENTLINE ||
1252                     status == D40_SUSPEND_REQ_EVENTLINE)
1253                         break;
1254
1255                 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1256                        | ~D40_EVENTLINE_MASK(event), addr);
1257
1258                 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1259
1260                         status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1261                                   D40_EVENTLINE_POS(event);
1262
1263                         cpu_relax();
1264                         /*
1265                          * Reduce the number of bus accesses while
1266                          * waiting for the DMA to suspend.
1267                          */
1268                         udelay(3);
1269
1270                         if (status == D40_DEACTIVATE_EVENTLINE)
1271                                 break;
1272                 }
1273
1274                 if (tries == D40_SUSPEND_MAX_IT) {
1275                         chan_err(d40c,
1276                                 "unable to stop the event_line chl %d (log: %d)"
1277                                 "status %x\n", d40c->phy_chan->num,
1278                                  d40c->log_num, status);
1279                 }
1280                 break;
1281
1282         case D40_ACTIVATE_EVENTLINE:
1283         /*
1284          * The hardware sometimes doesn't register the enable when src and dst
1285          * event lines are active on the same logical channel.  Retry to ensure
1286          * it does.  Usually only one retry is sufficient.
1287          */
1288                 tries = 100;
1289                 while (--tries) {
1290                         writel((D40_ACTIVATE_EVENTLINE <<
1291                                 D40_EVENTLINE_POS(event)) |
1292                                 ~D40_EVENTLINE_MASK(event), addr);
1293
1294                         if (readl(addr) & D40_EVENTLINE_MASK(event))
1295                                 break;
1296                 }
1297
1298                 if (tries != 99)
1299                         dev_dbg(chan2dev(d40c),
1300                                 "[%s] workaround enable S%cLNK (%d tries)\n",
1301                                 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1302                                 100 - tries);
1303
1304                 WARN_ON(!tries);
1305                 break;
1306
1307         case D40_ROUND_EVENTLINE:
1308                 BUG();
1309                 break;
1310
1311         }
1312 }
1313
1314 static void d40_config_set_event(struct d40_chan *d40c,
1315                                  enum d40_events event_type)
1316 {
1317         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1318
1319         /* Enable event line connected to device (or memcpy) */
1320         if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1321             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1322                 __d40_config_set_event(d40c, event_type, event,
1323                                        D40_CHAN_REG_SSLNK);
1324
1325         if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
1326                 __d40_config_set_event(d40c, event_type, event,
1327                                        D40_CHAN_REG_SDLNK);
1328 }
1329
1330 static u32 d40_chan_has_events(struct d40_chan *d40c)
1331 {
1332         void __iomem *chanbase = chan_base(d40c);
1333         u32 val;
1334
1335         val = readl(chanbase + D40_CHAN_REG_SSLNK);
1336         val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1337
1338         return val;
1339 }
1340
1341 static int
1342 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1343 {
1344         unsigned long flags;
1345         int ret = 0;
1346         u32 active_status;
1347         void __iomem *active_reg;
1348
1349         if (d40c->phy_chan->num % 2 == 0)
1350                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1351         else
1352                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1353
1354
1355         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1356
1357         switch (command) {
1358         case D40_DMA_STOP:
1359         case D40_DMA_SUSPEND_REQ:
1360
1361                 active_status = (readl(active_reg) &
1362                                  D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1363                                  D40_CHAN_POS(d40c->phy_chan->num);
1364
1365                 if (active_status == D40_DMA_RUN)
1366                         d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1367                 else
1368                         d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1369
1370                 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1371                         ret = __d40_execute_command_phy(d40c, command);
1372
1373                 break;
1374
1375         case D40_DMA_RUN:
1376
1377                 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1378                 ret = __d40_execute_command_phy(d40c, command);
1379                 break;
1380
1381         case D40_DMA_SUSPENDED:
1382                 BUG();
1383                 break;
1384         }
1385
1386         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1387         return ret;
1388 }
1389
1390 static int d40_channel_execute_command(struct d40_chan *d40c,
1391                                        enum d40_command command)
1392 {
1393         if (chan_is_logical(d40c))
1394                 return __d40_execute_command_log(d40c, command);
1395         else
1396                 return __d40_execute_command_phy(d40c, command);
1397 }
1398
1399 static u32 d40_get_prmo(struct d40_chan *d40c)
1400 {
1401         static const unsigned int phy_map[] = {
1402                 [STEDMA40_PCHAN_BASIC_MODE]
1403                         = D40_DREG_PRMO_PCHAN_BASIC,
1404                 [STEDMA40_PCHAN_MODULO_MODE]
1405                         = D40_DREG_PRMO_PCHAN_MODULO,
1406                 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1407                         = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1408         };
1409         static const unsigned int log_map[] = {
1410                 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1411                         = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1412                 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1413                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1414                 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1415                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1416         };
1417
1418         if (chan_is_physical(d40c))
1419                 return phy_map[d40c->dma_cfg.mode_opt];
1420         else
1421                 return log_map[d40c->dma_cfg.mode_opt];
1422 }
1423
1424 static void d40_config_write(struct d40_chan *d40c)
1425 {
1426         u32 addr_base;
1427         u32 var;
1428
1429         /* Odd addresses are even addresses + 4 */
1430         addr_base = (d40c->phy_chan->num % 2) * 4;
1431         /* Setup channel mode to logical or physical */
1432         var = ((u32)(chan_is_logical(d40c)) + 1) <<
1433                 D40_CHAN_POS(d40c->phy_chan->num);
1434         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1435
1436         /* Setup operational mode option register */
1437         var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1438
1439         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1440
1441         if (chan_is_logical(d40c)) {
1442                 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1443                            & D40_SREG_ELEM_LOG_LIDX_MASK;
1444                 void __iomem *chanbase = chan_base(d40c);
1445
1446                 /* Set default config for CFG reg */
1447                 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1448                 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1449
1450                 /* Set LIDX for lcla */
1451                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1452                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1453
1454                 /* Clear LNK which will be used by d40_chan_has_events() */
1455                 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1456                 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1457         }
1458 }
1459
1460 static u32 d40_residue(struct d40_chan *d40c)
1461 {
1462         u32 num_elt;
1463
1464         if (chan_is_logical(d40c))
1465                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1466                         >> D40_MEM_LCSP2_ECNT_POS;
1467         else {
1468                 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1469                 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1470                           >> D40_SREG_ELEM_PHY_ECNT_POS;
1471         }
1472
1473         return num_elt * d40c->dma_cfg.dst_info.data_width;
1474 }
1475
1476 static bool d40_tx_is_linked(struct d40_chan *d40c)
1477 {
1478         bool is_link;
1479
1480         if (chan_is_logical(d40c))
1481                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
1482         else
1483                 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1484                           & D40_SREG_LNK_PHYS_LNK_MASK;
1485
1486         return is_link;
1487 }
1488
1489 static int d40_pause(struct d40_chan *d40c)
1490 {
1491         int res = 0;
1492         unsigned long flags;
1493
1494         if (!d40c->busy)
1495                 return 0;
1496
1497         pm_runtime_get_sync(d40c->base->dev);
1498         spin_lock_irqsave(&d40c->lock, flags);
1499
1500         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1501
1502         pm_runtime_mark_last_busy(d40c->base->dev);
1503         pm_runtime_put_autosuspend(d40c->base->dev);
1504         spin_unlock_irqrestore(&d40c->lock, flags);
1505         return res;
1506 }
1507
1508 static int d40_resume(struct d40_chan *d40c)
1509 {
1510         int res = 0;
1511         unsigned long flags;
1512
1513         if (!d40c->busy)
1514                 return 0;
1515
1516         spin_lock_irqsave(&d40c->lock, flags);
1517         pm_runtime_get_sync(d40c->base->dev);
1518
1519         /* If bytes left to transfer or linked tx resume job */
1520         if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1521                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1522
1523         pm_runtime_mark_last_busy(d40c->base->dev);
1524         pm_runtime_put_autosuspend(d40c->base->dev);
1525         spin_unlock_irqrestore(&d40c->lock, flags);
1526         return res;
1527 }
1528
1529 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1530 {
1531         struct d40_chan *d40c = container_of(tx->chan,
1532                                              struct d40_chan,
1533                                              chan);
1534         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1535         unsigned long flags;
1536         dma_cookie_t cookie;
1537
1538         spin_lock_irqsave(&d40c->lock, flags);
1539         cookie = dma_cookie_assign(tx);
1540         d40_desc_queue(d40c, d40d);
1541         spin_unlock_irqrestore(&d40c->lock, flags);
1542
1543         return cookie;
1544 }
1545
1546 static int d40_start(struct d40_chan *d40c)
1547 {
1548         return d40_channel_execute_command(d40c, D40_DMA_RUN);
1549 }
1550
1551 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1552 {
1553         struct d40_desc *d40d;
1554         int err;
1555
1556         /* Start queued jobs, if any */
1557         d40d = d40_first_queued(d40c);
1558
1559         if (d40d != NULL) {
1560                 if (!d40c->busy) {
1561                         d40c->busy = true;
1562                         pm_runtime_get_sync(d40c->base->dev);
1563                 }
1564
1565                 /* Remove from queue */
1566                 d40_desc_remove(d40d);
1567
1568                 /* Add to active queue */
1569                 d40_desc_submit(d40c, d40d);
1570
1571                 /* Initiate DMA job */
1572                 d40_desc_load(d40c, d40d);
1573
1574                 /* Start dma job */
1575                 err = d40_start(d40c);
1576
1577                 if (err)
1578                         return NULL;
1579         }
1580
1581         return d40d;
1582 }
1583
1584 /* called from interrupt context */
1585 static void dma_tc_handle(struct d40_chan *d40c)
1586 {
1587         struct d40_desc *d40d;
1588
1589         /* Get first active entry from list */
1590         d40d = d40_first_active_get(d40c);
1591
1592         if (d40d == NULL)
1593                 return;
1594
1595         if (d40d->cyclic) {
1596                 /*
1597                  * If this was a paritially loaded list, we need to reloaded
1598                  * it, and only when the list is completed.  We need to check
1599                  * for done because the interrupt will hit for every link, and
1600                  * not just the last one.
1601                  */
1602                 if (d40d->lli_current < d40d->lli_len
1603                     && !d40_tx_is_linked(d40c)
1604                     && !d40_residue(d40c)) {
1605                         d40_lcla_free_all(d40c, d40d);
1606                         d40_desc_load(d40c, d40d);
1607                         (void) d40_start(d40c);
1608
1609                         if (d40d->lli_current == d40d->lli_len)
1610                                 d40d->lli_current = 0;
1611                 }
1612         } else {
1613                 d40_lcla_free_all(d40c, d40d);
1614
1615                 if (d40d->lli_current < d40d->lli_len) {
1616                         d40_desc_load(d40c, d40d);
1617                         /* Start dma job */
1618                         (void) d40_start(d40c);
1619                         return;
1620                 }
1621
1622                 if (d40_queue_start(d40c) == NULL)
1623                         d40c->busy = false;
1624                 pm_runtime_mark_last_busy(d40c->base->dev);
1625                 pm_runtime_put_autosuspend(d40c->base->dev);
1626
1627                 d40_desc_remove(d40d);
1628                 d40_desc_done(d40c, d40d);
1629         }
1630
1631         d40c->pending_tx++;
1632         tasklet_schedule(&d40c->tasklet);
1633
1634 }
1635
1636 static void dma_tasklet(unsigned long data)
1637 {
1638         struct d40_chan *d40c = (struct d40_chan *) data;
1639         struct d40_desc *d40d;
1640         unsigned long flags;
1641         dma_async_tx_callback callback;
1642         void *callback_param;
1643
1644         spin_lock_irqsave(&d40c->lock, flags);
1645
1646         /* Get first entry from the done list */
1647         d40d = d40_first_done(d40c);
1648         if (d40d == NULL) {
1649                 /* Check if we have reached here for cyclic job */
1650                 d40d = d40_first_active_get(d40c);
1651                 if (d40d == NULL || !d40d->cyclic)
1652                         goto err;
1653         }
1654
1655         if (!d40d->cyclic)
1656                 dma_cookie_complete(&d40d->txd);
1657
1658         /*
1659          * If terminating a channel pending_tx is set to zero.
1660          * This prevents any finished active jobs to return to the client.
1661          */
1662         if (d40c->pending_tx == 0) {
1663                 spin_unlock_irqrestore(&d40c->lock, flags);
1664                 return;
1665         }
1666
1667         /* Callback to client */
1668         callback = d40d->txd.callback;
1669         callback_param = d40d->txd.callback_param;
1670
1671         if (!d40d->cyclic) {
1672                 if (async_tx_test_ack(&d40d->txd)) {
1673                         d40_desc_remove(d40d);
1674                         d40_desc_free(d40c, d40d);
1675                 } else if (!d40d->is_in_client_list) {
1676                         d40_desc_remove(d40d);
1677                         d40_lcla_free_all(d40c, d40d);
1678                         list_add_tail(&d40d->node, &d40c->client);
1679                         d40d->is_in_client_list = true;
1680                 }
1681         }
1682
1683         d40c->pending_tx--;
1684
1685         if (d40c->pending_tx)
1686                 tasklet_schedule(&d40c->tasklet);
1687
1688         spin_unlock_irqrestore(&d40c->lock, flags);
1689
1690         if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
1691                 callback(callback_param);
1692
1693         return;
1694
1695 err:
1696         /* Rescue manouver if receiving double interrupts */
1697         if (d40c->pending_tx > 0)
1698                 d40c->pending_tx--;
1699         spin_unlock_irqrestore(&d40c->lock, flags);
1700 }
1701
1702 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1703 {
1704         int i;
1705         u32 idx;
1706         u32 row;
1707         long chan = -1;
1708         struct d40_chan *d40c;
1709         unsigned long flags;
1710         struct d40_base *base = data;
1711         u32 regs[base->gen_dmac.il_size];
1712         struct d40_interrupt_lookup *il = base->gen_dmac.il;
1713         u32 il_size = base->gen_dmac.il_size;
1714
1715         spin_lock_irqsave(&base->interrupt_lock, flags);
1716
1717         /* Read interrupt status of both logical and physical channels */
1718         for (i = 0; i < il_size; i++)
1719                 regs[i] = readl(base->virtbase + il[i].src);
1720
1721         for (;;) {
1722
1723                 chan = find_next_bit((unsigned long *)regs,
1724                                      BITS_PER_LONG * il_size, chan + 1);
1725
1726                 /* No more set bits found? */
1727                 if (chan == BITS_PER_LONG * il_size)
1728                         break;
1729
1730                 row = chan / BITS_PER_LONG;
1731                 idx = chan & (BITS_PER_LONG - 1);
1732
1733                 if (il[row].offset == D40_PHY_CHAN)
1734                         d40c = base->lookup_phy_chans[idx];
1735                 else
1736                         d40c = base->lookup_log_chans[il[row].offset + idx];
1737
1738                 if (!d40c) {
1739                         /*
1740                          * No error because this can happen if something else
1741                          * in the system is using the channel.
1742                          */
1743                         continue;
1744                 }
1745
1746                 /* ACK interrupt */
1747                 writel(BIT(idx), base->virtbase + il[row].clr);
1748
1749                 spin_lock(&d40c->lock);
1750
1751                 if (!il[row].is_error)
1752                         dma_tc_handle(d40c);
1753                 else
1754                         d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1755                                 chan, il[row].offset, idx);
1756
1757                 spin_unlock(&d40c->lock);
1758         }
1759
1760         spin_unlock_irqrestore(&base->interrupt_lock, flags);
1761
1762         return IRQ_HANDLED;
1763 }
1764
1765 static int d40_validate_conf(struct d40_chan *d40c,
1766                              struct stedma40_chan_cfg *conf)
1767 {
1768         int res = 0;
1769         bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1770
1771         if (!conf->dir) {
1772                 chan_err(d40c, "Invalid direction.\n");
1773                 res = -EINVAL;
1774         }
1775
1776         if ((is_log && conf->dev_type > d40c->base->num_log_chans)  ||
1777             (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1778             (conf->dev_type < 0)) {
1779                 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
1780                 res = -EINVAL;
1781         }
1782
1783         if (conf->dir == DMA_DEV_TO_DEV) {
1784                 /*
1785                  * DMAC HW supports it. Will be added to this driver,
1786                  * in case any dma client requires it.
1787                  */
1788                 chan_err(d40c, "periph to periph not supported\n");
1789                 res = -EINVAL;
1790         }
1791
1792         if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1793             conf->src_info.data_width !=
1794             d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1795             conf->dst_info.data_width) {
1796                 /*
1797                  * The DMAC hardware only supports
1798                  * src (burst x width) == dst (burst x width)
1799                  */
1800
1801                 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1802                 res = -EINVAL;
1803         }
1804
1805         return res;
1806 }
1807
1808 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1809                                bool is_src, int log_event_line, bool is_log,
1810                                bool *first_user)
1811 {
1812         unsigned long flags;
1813         spin_lock_irqsave(&phy->lock, flags);
1814
1815         *first_user = ((phy->allocated_src | phy->allocated_dst)
1816                         == D40_ALLOC_FREE);
1817
1818         if (!is_log) {
1819                 /* Physical interrupts are masked per physical full channel */
1820                 if (phy->allocated_src == D40_ALLOC_FREE &&
1821                     phy->allocated_dst == D40_ALLOC_FREE) {
1822                         phy->allocated_dst = D40_ALLOC_PHY;
1823                         phy->allocated_src = D40_ALLOC_PHY;
1824                         goto found;
1825                 } else
1826                         goto not_found;
1827         }
1828
1829         /* Logical channel */
1830         if (is_src) {
1831                 if (phy->allocated_src == D40_ALLOC_PHY)
1832                         goto not_found;
1833
1834                 if (phy->allocated_src == D40_ALLOC_FREE)
1835                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1836
1837                 if (!(phy->allocated_src & BIT(log_event_line))) {
1838                         phy->allocated_src |= BIT(log_event_line);
1839                         goto found;
1840                 } else
1841                         goto not_found;
1842         } else {
1843                 if (phy->allocated_dst == D40_ALLOC_PHY)
1844                         goto not_found;
1845
1846                 if (phy->allocated_dst == D40_ALLOC_FREE)
1847                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1848
1849                 if (!(phy->allocated_dst & BIT(log_event_line))) {
1850                         phy->allocated_dst |= BIT(log_event_line);
1851                         goto found;
1852                 } else
1853                         goto not_found;
1854         }
1855
1856 not_found:
1857         spin_unlock_irqrestore(&phy->lock, flags);
1858         return false;
1859 found:
1860         spin_unlock_irqrestore(&phy->lock, flags);
1861         return true;
1862 }
1863
1864 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1865                                int log_event_line)
1866 {
1867         unsigned long flags;
1868         bool is_free = false;
1869
1870         spin_lock_irqsave(&phy->lock, flags);
1871         if (!log_event_line) {
1872                 phy->allocated_dst = D40_ALLOC_FREE;
1873                 phy->allocated_src = D40_ALLOC_FREE;
1874                 is_free = true;
1875                 goto out;
1876         }
1877
1878         /* Logical channel */
1879         if (is_src) {
1880                 phy->allocated_src &= ~BIT(log_event_line);
1881                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1882                         phy->allocated_src = D40_ALLOC_FREE;
1883         } else {
1884                 phy->allocated_dst &= ~BIT(log_event_line);
1885                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1886                         phy->allocated_dst = D40_ALLOC_FREE;
1887         }
1888
1889         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1890                    D40_ALLOC_FREE);
1891
1892 out:
1893         spin_unlock_irqrestore(&phy->lock, flags);
1894
1895         return is_free;
1896 }
1897
1898 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1899 {
1900         int dev_type = d40c->dma_cfg.dev_type;
1901         int event_group;
1902         int event_line;
1903         struct d40_phy_res *phys;
1904         int i;
1905         int j;
1906         int log_num;
1907         int num_phy_chans;
1908         bool is_src;
1909         bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1910
1911         phys = d40c->base->phy_res;
1912         num_phy_chans = d40c->base->num_phy_chans;
1913
1914         if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
1915                 log_num = 2 * dev_type;
1916                 is_src = true;
1917         } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1918                    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1919                 /* dst event lines are used for logical memcpy */
1920                 log_num = 2 * dev_type + 1;
1921                 is_src = false;
1922         } else
1923                 return -EINVAL;
1924
1925         event_group = D40_TYPE_TO_GROUP(dev_type);
1926         event_line = D40_TYPE_TO_EVENT(dev_type);
1927
1928         if (!is_log) {
1929                 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1930                         /* Find physical half channel */
1931                         if (d40c->dma_cfg.use_fixed_channel) {
1932                                 i = d40c->dma_cfg.phy_channel;
1933                                 if (d40_alloc_mask_set(&phys[i], is_src,
1934                                                        0, is_log,
1935                                                        first_phy_user))
1936                                         goto found_phy;
1937                         } else {
1938                                 for (i = 0; i < num_phy_chans; i++) {
1939                                         if (d40_alloc_mask_set(&phys[i], is_src,
1940                                                        0, is_log,
1941                                                        first_phy_user))
1942                                                 goto found_phy;
1943                                 }
1944                         }
1945                 } else
1946                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1947                                 int phy_num = j  + event_group * 2;
1948                                 for (i = phy_num; i < phy_num + 2; i++) {
1949                                         if (d40_alloc_mask_set(&phys[i],
1950                                                                is_src,
1951                                                                0,
1952                                                                is_log,
1953                                                                first_phy_user))
1954                                                 goto found_phy;
1955                                 }
1956                         }
1957                 return -EINVAL;
1958 found_phy:
1959                 d40c->phy_chan = &phys[i];
1960                 d40c->log_num = D40_PHY_CHAN;
1961                 goto out;
1962         }
1963         if (dev_type == -1)
1964                 return -EINVAL;
1965
1966         /* Find logical channel */
1967         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1968                 int phy_num = j + event_group * 2;
1969
1970                 if (d40c->dma_cfg.use_fixed_channel) {
1971                         i = d40c->dma_cfg.phy_channel;
1972
1973                         if ((i != phy_num) && (i != phy_num + 1)) {
1974                                 dev_err(chan2dev(d40c),
1975                                         "invalid fixed phy channel %d\n", i);
1976                                 return -EINVAL;
1977                         }
1978
1979                         if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1980                                                is_log, first_phy_user))
1981                                 goto found_log;
1982
1983                         dev_err(chan2dev(d40c),
1984                                 "could not allocate fixed phy channel %d\n", i);
1985                         return -EINVAL;
1986                 }
1987
1988                 /*
1989                  * Spread logical channels across all available physical rather
1990                  * than pack every logical channel at the first available phy
1991                  * channels.
1992                  */
1993                 if (is_src) {
1994                         for (i = phy_num; i < phy_num + 2; i++) {
1995                                 if (d40_alloc_mask_set(&phys[i], is_src,
1996                                                        event_line, is_log,
1997                                                        first_phy_user))
1998                                         goto found_log;
1999                         }
2000                 } else {
2001                         for (i = phy_num + 1; i >= phy_num; i--) {
2002                                 if (d40_alloc_mask_set(&phys[i], is_src,
2003                                                        event_line, is_log,
2004                                                        first_phy_user))
2005                                         goto found_log;
2006                         }
2007                 }
2008         }
2009         return -EINVAL;
2010
2011 found_log:
2012         d40c->phy_chan = &phys[i];
2013         d40c->log_num = log_num;
2014 out:
2015
2016         if (is_log)
2017                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
2018         else
2019                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
2020
2021         return 0;
2022
2023 }
2024
2025 static int d40_config_memcpy(struct d40_chan *d40c)
2026 {
2027         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
2028
2029         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
2030                 d40c->dma_cfg = dma40_memcpy_conf_log;
2031                 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
2032
2033                 d40_log_cfg(&d40c->dma_cfg,
2034                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2035
2036         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2037                    dma_has_cap(DMA_SLAVE, cap)) {
2038                 d40c->dma_cfg = dma40_memcpy_conf_phy;
2039
2040                 /* Generate interrrupt at end of transfer or relink. */
2041                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
2042
2043                 /* Generate interrupt on error. */
2044                 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2045                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2046
2047         } else {
2048                 chan_err(d40c, "No memcpy\n");
2049                 return -EINVAL;
2050         }
2051
2052         return 0;
2053 }
2054
2055 static int d40_free_dma(struct d40_chan *d40c)
2056 {
2057
2058         int res = 0;
2059         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2060         struct d40_phy_res *phy = d40c->phy_chan;
2061         bool is_src;
2062
2063         /* Terminate all queued and active transfers */
2064         d40_term_all(d40c);
2065
2066         if (phy == NULL) {
2067                 chan_err(d40c, "phy == null\n");
2068                 return -EINVAL;
2069         }
2070
2071         if (phy->allocated_src == D40_ALLOC_FREE &&
2072             phy->allocated_dst == D40_ALLOC_FREE) {
2073                 chan_err(d40c, "channel already free\n");
2074                 return -EINVAL;
2075         }
2076
2077         if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2078             d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
2079                 is_src = false;
2080         else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2081                 is_src = true;
2082         else {
2083                 chan_err(d40c, "Unknown direction\n");
2084                 return -EINVAL;
2085         }
2086
2087         pm_runtime_get_sync(d40c->base->dev);
2088         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
2089         if (res) {
2090                 chan_err(d40c, "stop failed\n");
2091                 goto out;
2092         }
2093
2094         d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
2095
2096         if (chan_is_logical(d40c))
2097                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
2098         else
2099                 d40c->base->lookup_phy_chans[phy->num] = NULL;
2100
2101         if (d40c->busy) {
2102                 pm_runtime_mark_last_busy(d40c->base->dev);
2103                 pm_runtime_put_autosuspend(d40c->base->dev);
2104         }
2105
2106         d40c->busy = false;
2107         d40c->phy_chan = NULL;
2108         d40c->configured = false;
2109 out:
2110
2111         pm_runtime_mark_last_busy(d40c->base->dev);
2112         pm_runtime_put_autosuspend(d40c->base->dev);
2113         return res;
2114 }
2115
2116 static bool d40_is_paused(struct d40_chan *d40c)
2117 {
2118         void __iomem *chanbase = chan_base(d40c);
2119         bool is_paused = false;
2120         unsigned long flags;
2121         void __iomem *active_reg;
2122         u32 status;
2123         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2124
2125         spin_lock_irqsave(&d40c->lock, flags);
2126
2127         if (chan_is_physical(d40c)) {
2128                 if (d40c->phy_chan->num % 2 == 0)
2129                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2130                 else
2131                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2132
2133                 status = (readl(active_reg) &
2134                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2135                         D40_CHAN_POS(d40c->phy_chan->num);
2136                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2137                         is_paused = true;
2138
2139                 goto _exit;
2140         }
2141
2142         if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2143             d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
2144                 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2145         } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
2146                 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2147         } else {
2148                 chan_err(d40c, "Unknown direction\n");
2149                 goto _exit;
2150         }
2151
2152         status = (status & D40_EVENTLINE_MASK(event)) >>
2153                 D40_EVENTLINE_POS(event);
2154
2155         if (status != D40_DMA_RUN)
2156                 is_paused = true;
2157 _exit:
2158         spin_unlock_irqrestore(&d40c->lock, flags);
2159         return is_paused;
2160
2161 }
2162
2163 static u32 stedma40_residue(struct dma_chan *chan)
2164 {
2165         struct d40_chan *d40c =
2166                 container_of(chan, struct d40_chan, chan);
2167         u32 bytes_left;
2168         unsigned long flags;
2169
2170         spin_lock_irqsave(&d40c->lock, flags);
2171         bytes_left = d40_residue(d40c);
2172         spin_unlock_irqrestore(&d40c->lock, flags);
2173
2174         return bytes_left;
2175 }
2176
2177 static int
2178 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2179                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2180                 unsigned int sg_len, dma_addr_t src_dev_addr,
2181                 dma_addr_t dst_dev_addr)
2182 {
2183         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2184         struct stedma40_half_channel_info *src_info = &cfg->src_info;
2185         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2186         int ret;
2187
2188         ret = d40_log_sg_to_lli(sg_src, sg_len,
2189                                 src_dev_addr,
2190                                 desc->lli_log.src,
2191                                 chan->log_def.lcsp1,
2192                                 src_info->data_width,
2193                                 dst_info->data_width);
2194
2195         ret = d40_log_sg_to_lli(sg_dst, sg_len,
2196                                 dst_dev_addr,
2197                                 desc->lli_log.dst,
2198                                 chan->log_def.lcsp3,
2199                                 dst_info->data_width,
2200                                 src_info->data_width);
2201
2202         return ret < 0 ? ret : 0;
2203 }
2204
2205 static int
2206 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2207                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2208                 unsigned int sg_len, dma_addr_t src_dev_addr,
2209                 dma_addr_t dst_dev_addr)
2210 {
2211         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2212         struct stedma40_half_channel_info *src_info = &cfg->src_info;
2213         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2214         unsigned long flags = 0;
2215         int ret;
2216
2217         if (desc->cyclic)
2218                 flags |= LLI_CYCLIC | LLI_TERM_INT;
2219
2220         ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2221                                 desc->lli_phy.src,
2222                                 virt_to_phys(desc->lli_phy.src),
2223                                 chan->src_def_cfg,
2224                                 src_info, dst_info, flags);
2225
2226         ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2227                                 desc->lli_phy.dst,
2228                                 virt_to_phys(desc->lli_phy.dst),
2229                                 chan->dst_def_cfg,
2230                                 dst_info, src_info, flags);
2231
2232         dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2233                                    desc->lli_pool.size, DMA_TO_DEVICE);
2234
2235         return ret < 0 ? ret : 0;
2236 }
2237
2238 static struct d40_desc *
2239 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2240               unsigned int sg_len, unsigned long dma_flags)
2241 {
2242         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2243         struct d40_desc *desc;
2244         int ret;
2245
2246         desc = d40_desc_get(chan);
2247         if (!desc)
2248                 return NULL;
2249
2250         desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2251                                         cfg->dst_info.data_width);
2252         if (desc->lli_len < 0) {
2253                 chan_err(chan, "Unaligned size\n");
2254                 goto err;
2255         }
2256
2257         ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2258         if (ret < 0) {
2259                 chan_err(chan, "Could not allocate lli\n");
2260                 goto err;
2261         }
2262
2263         desc->lli_current = 0;
2264         desc->txd.flags = dma_flags;
2265         desc->txd.tx_submit = d40_tx_submit;
2266
2267         dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2268
2269         return desc;
2270
2271 err:
2272         d40_desc_free(chan, desc);
2273         return NULL;
2274 }
2275
2276 static struct dma_async_tx_descriptor *
2277 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2278             struct scatterlist *sg_dst, unsigned int sg_len,
2279             enum dma_transfer_direction direction, unsigned long dma_flags)
2280 {
2281         struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2282         dma_addr_t src_dev_addr = 0;
2283         dma_addr_t dst_dev_addr = 0;
2284         struct d40_desc *desc;
2285         unsigned long flags;
2286         int ret;
2287
2288         if (!chan->phy_chan) {
2289                 chan_err(chan, "Cannot prepare unallocated channel\n");
2290                 return NULL;
2291         }
2292
2293         spin_lock_irqsave(&chan->lock, flags);
2294
2295         desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2296         if (desc == NULL)
2297                 goto err;
2298
2299         if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2300                 desc->cyclic = true;
2301
2302         if (direction == DMA_DEV_TO_MEM)
2303                 src_dev_addr = chan->runtime_addr;
2304         else if (direction == DMA_MEM_TO_DEV)
2305                 dst_dev_addr = chan->runtime_addr;
2306
2307         if (chan_is_logical(chan))
2308                 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2309                                       sg_len, src_dev_addr, dst_dev_addr);
2310         else
2311                 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2312                                       sg_len, src_dev_addr, dst_dev_addr);
2313
2314         if (ret) {
2315                 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2316                          chan_is_logical(chan) ? "log" : "phy", ret);
2317                 goto err;
2318         }
2319
2320         /*
2321          * add descriptor to the prepare queue in order to be able
2322          * to free them later in terminate_all
2323          */
2324         list_add_tail(&desc->node, &chan->prepare_queue);
2325
2326         spin_unlock_irqrestore(&chan->lock, flags);
2327
2328         return &desc->txd;
2329
2330 err:
2331         if (desc)
2332                 d40_desc_free(chan, desc);
2333         spin_unlock_irqrestore(&chan->lock, flags);
2334         return NULL;
2335 }
2336
2337 bool stedma40_filter(struct dma_chan *chan, void *data)
2338 {
2339         struct stedma40_chan_cfg *info = data;
2340         struct d40_chan *d40c =
2341                 container_of(chan, struct d40_chan, chan);
2342         int err;
2343
2344         if (data) {
2345                 err = d40_validate_conf(d40c, info);
2346                 if (!err)
2347                         d40c->dma_cfg = *info;
2348         } else
2349                 err = d40_config_memcpy(d40c);
2350
2351         if (!err)
2352                 d40c->configured = true;
2353
2354         return err == 0;
2355 }
2356 EXPORT_SYMBOL(stedma40_filter);
2357
2358 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2359 {
2360         bool realtime = d40c->dma_cfg.realtime;
2361         bool highprio = d40c->dma_cfg.high_priority;
2362         u32 rtreg;
2363         u32 event = D40_TYPE_TO_EVENT(dev_type);
2364         u32 group = D40_TYPE_TO_GROUP(dev_type);
2365         u32 bit = BIT(event);
2366         u32 prioreg;
2367         struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2368
2369         rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
2370         /*
2371          * Due to a hardware bug, in some cases a logical channel triggered by
2372          * a high priority destination event line can generate extra packet
2373          * transactions.
2374          *
2375          * The workaround is to not set the high priority level for the
2376          * destination event lines that trigger logical channels.
2377          */
2378         if (!src && chan_is_logical(d40c))
2379                 highprio = false;
2380
2381         prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
2382
2383         /* Destination event lines are stored in the upper halfword */
2384         if (!src)
2385                 bit <<= 16;
2386
2387         writel(bit, d40c->base->virtbase + prioreg + group * 4);
2388         writel(bit, d40c->base->virtbase + rtreg + group * 4);
2389 }
2390
2391 static void d40_set_prio_realtime(struct d40_chan *d40c)
2392 {
2393         if (d40c->base->rev < 3)
2394                 return;
2395
2396         if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
2397             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2398                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2399
2400         if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
2401             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2402                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2403 }
2404
2405 #define D40_DT_FLAGS_MODE(flags)       ((flags >> 0) & 0x1)
2406 #define D40_DT_FLAGS_DIR(flags)        ((flags >> 1) & 0x1)
2407 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2408 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2409
2410 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2411                                   struct of_dma *ofdma)
2412 {
2413         struct stedma40_chan_cfg cfg;
2414         dma_cap_mask_t cap;
2415         u32 flags;
2416
2417         memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2418
2419         dma_cap_zero(cap);
2420         dma_cap_set(DMA_SLAVE, cap);
2421
2422         cfg.dev_type = dma_spec->args[0];
2423         flags = dma_spec->args[2];
2424
2425         switch (D40_DT_FLAGS_MODE(flags)) {
2426         case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2427         case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2428         }
2429
2430         switch (D40_DT_FLAGS_DIR(flags)) {
2431         case 0:
2432                 cfg.dir = DMA_MEM_TO_DEV;
2433                 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2434                 break;
2435         case 1:
2436                 cfg.dir = DMA_DEV_TO_MEM;
2437                 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2438                 break;
2439         }
2440
2441         if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2442                 cfg.phy_channel = dma_spec->args[1];
2443                 cfg.use_fixed_channel = true;
2444         }
2445
2446         return dma_request_channel(cap, stedma40_filter, &cfg);
2447 }
2448
2449 /* DMA ENGINE functions */
2450 static int d40_alloc_chan_resources(struct dma_chan *chan)
2451 {
2452         int err;
2453         unsigned long flags;
2454         struct d40_chan *d40c =
2455                 container_of(chan, struct d40_chan, chan);
2456         bool is_free_phy;
2457         spin_lock_irqsave(&d40c->lock, flags);
2458
2459         dma_cookie_init(chan);
2460
2461         /* If no dma configuration is set use default configuration (memcpy) */
2462         if (!d40c->configured) {
2463                 err = d40_config_memcpy(d40c);
2464                 if (err) {
2465                         chan_err(d40c, "Failed to configure memcpy channel\n");
2466                         goto fail;
2467                 }
2468         }
2469
2470         err = d40_allocate_channel(d40c, &is_free_phy);
2471         if (err) {
2472                 chan_err(d40c, "Failed to allocate channel\n");
2473                 d40c->configured = false;
2474                 goto fail;
2475         }
2476
2477         pm_runtime_get_sync(d40c->base->dev);
2478
2479         d40_set_prio_realtime(d40c);
2480
2481         if (chan_is_logical(d40c)) {
2482                 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2483                         d40c->lcpa = d40c->base->lcpa_base +
2484                                 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2485                 else
2486                         d40c->lcpa = d40c->base->lcpa_base +
2487                                 d40c->dma_cfg.dev_type *
2488                                 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2489
2490                 /* Unmask the Global Interrupt Mask. */
2491                 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2492                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2493         }
2494
2495         dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2496                  chan_is_logical(d40c) ? "logical" : "physical",
2497                  d40c->phy_chan->num,
2498                  d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2499
2500
2501         /*
2502          * Only write channel configuration to the DMA if the physical
2503          * resource is free. In case of multiple logical channels
2504          * on the same physical resource, only the first write is necessary.
2505          */
2506         if (is_free_phy)
2507                 d40_config_write(d40c);
2508 fail:
2509         pm_runtime_mark_last_busy(d40c->base->dev);
2510         pm_runtime_put_autosuspend(d40c->base->dev);
2511         spin_unlock_irqrestore(&d40c->lock, flags);
2512         return err;
2513 }
2514
2515 static void d40_free_chan_resources(struct dma_chan *chan)
2516 {
2517         struct d40_chan *d40c =
2518                 container_of(chan, struct d40_chan, chan);
2519         int err;
2520         unsigned long flags;
2521
2522         if (d40c->phy_chan == NULL) {
2523                 chan_err(d40c, "Cannot free unallocated channel\n");
2524                 return;
2525         }
2526
2527         spin_lock_irqsave(&d40c->lock, flags);
2528
2529         err = d40_free_dma(d40c);
2530
2531         if (err)
2532                 chan_err(d40c, "Failed to free channel\n");
2533         spin_unlock_irqrestore(&d40c->lock, flags);
2534 }
2535
2536 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2537                                                        dma_addr_t dst,
2538                                                        dma_addr_t src,
2539                                                        size_t size,
2540                                                        unsigned long dma_flags)
2541 {
2542         struct scatterlist dst_sg;
2543         struct scatterlist src_sg;
2544
2545         sg_init_table(&dst_sg, 1);
2546         sg_init_table(&src_sg, 1);
2547
2548         sg_dma_address(&dst_sg) = dst;
2549         sg_dma_address(&src_sg) = src;
2550
2551         sg_dma_len(&dst_sg) = size;
2552         sg_dma_len(&src_sg) = size;
2553
2554         return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
2555 }
2556
2557 static struct dma_async_tx_descriptor *
2558 d40_prep_memcpy_sg(struct dma_chan *chan,
2559                    struct scatterlist *dst_sg, unsigned int dst_nents,
2560                    struct scatterlist *src_sg, unsigned int src_nents,
2561                    unsigned long dma_flags)
2562 {
2563         if (dst_nents != src_nents)
2564                 return NULL;
2565
2566         return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
2567 }
2568
2569 static struct dma_async_tx_descriptor *
2570 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2571                   unsigned int sg_len, enum dma_transfer_direction direction,
2572                   unsigned long dma_flags, void *context)
2573 {
2574         if (!is_slave_direction(direction))
2575                 return NULL;
2576
2577         return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2578 }
2579
2580 static struct dma_async_tx_descriptor *
2581 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2582                      size_t buf_len, size_t period_len,
2583                      enum dma_transfer_direction direction, unsigned long flags,
2584                      void *context)
2585 {
2586         unsigned int periods = buf_len / period_len;
2587         struct dma_async_tx_descriptor *txd;
2588         struct scatterlist *sg;
2589         int i;
2590
2591         sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2592         for (i = 0; i < periods; i++) {
2593                 sg_dma_address(&sg[i]) = dma_addr;
2594                 sg_dma_len(&sg[i]) = period_len;
2595                 dma_addr += period_len;
2596         }
2597
2598         sg[periods].offset = 0;
2599         sg_dma_len(&sg[periods]) = 0;
2600         sg[periods].page_link =
2601                 ((unsigned long)sg | 0x01) & ~0x02;
2602
2603         txd = d40_prep_sg(chan, sg, sg, periods, direction,
2604                           DMA_PREP_INTERRUPT);
2605
2606         kfree(sg);
2607
2608         return txd;
2609 }
2610
2611 static enum dma_status d40_tx_status(struct dma_chan *chan,
2612                                      dma_cookie_t cookie,
2613                                      struct dma_tx_state *txstate)
2614 {
2615         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2616         enum dma_status ret;
2617
2618         if (d40c->phy_chan == NULL) {
2619                 chan_err(d40c, "Cannot read status of unallocated channel\n");
2620                 return -EINVAL;
2621         }
2622
2623         ret = dma_cookie_status(chan, cookie, txstate);
2624         if (ret != DMA_SUCCESS)
2625                 dma_set_residue(txstate, stedma40_residue(chan));
2626
2627         if (d40_is_paused(d40c))
2628                 ret = DMA_PAUSED;
2629
2630         return ret;
2631 }
2632
2633 static void d40_issue_pending(struct dma_chan *chan)
2634 {
2635         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2636         unsigned long flags;
2637
2638         if (d40c->phy_chan == NULL) {
2639                 chan_err(d40c, "Channel is not allocated!\n");
2640                 return;
2641         }
2642
2643         spin_lock_irqsave(&d40c->lock, flags);
2644
2645         list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2646
2647         /* Busy means that queued jobs are already being processed */
2648         if (!d40c->busy)
2649                 (void) d40_queue_start(d40c);
2650
2651         spin_unlock_irqrestore(&d40c->lock, flags);
2652 }
2653
2654 static void d40_terminate_all(struct dma_chan *chan)
2655 {
2656         unsigned long flags;
2657         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2658         int ret;
2659
2660         spin_lock_irqsave(&d40c->lock, flags);
2661
2662         pm_runtime_get_sync(d40c->base->dev);
2663         ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2664         if (ret)
2665                 chan_err(d40c, "Failed to stop channel\n");
2666
2667         d40_term_all(d40c);
2668         pm_runtime_mark_last_busy(d40c->base->dev);
2669         pm_runtime_put_autosuspend(d40c->base->dev);
2670         if (d40c->busy) {
2671                 pm_runtime_mark_last_busy(d40c->base->dev);
2672                 pm_runtime_put_autosuspend(d40c->base->dev);
2673         }
2674         d40c->busy = false;
2675
2676         spin_unlock_irqrestore(&d40c->lock, flags);
2677 }
2678
2679 static int
2680 dma40_config_to_halfchannel(struct d40_chan *d40c,
2681                             struct stedma40_half_channel_info *info,
2682                             u32 maxburst)
2683 {
2684         int psize;
2685
2686         if (chan_is_logical(d40c)) {
2687                 if (maxburst >= 16)
2688                         psize = STEDMA40_PSIZE_LOG_16;
2689                 else if (maxburst >= 8)
2690                         psize = STEDMA40_PSIZE_LOG_8;
2691                 else if (maxburst >= 4)
2692                         psize = STEDMA40_PSIZE_LOG_4;
2693                 else
2694                         psize = STEDMA40_PSIZE_LOG_1;
2695         } else {
2696                 if (maxburst >= 16)
2697                         psize = STEDMA40_PSIZE_PHY_16;
2698                 else if (maxburst >= 8)
2699                         psize = STEDMA40_PSIZE_PHY_8;
2700                 else if (maxburst >= 4)
2701                         psize = STEDMA40_PSIZE_PHY_4;
2702                 else
2703                         psize = STEDMA40_PSIZE_PHY_1;
2704         }
2705
2706         info->psize = psize;
2707         info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2708
2709         return 0;
2710 }
2711
2712 /* Runtime reconfiguration extension */
2713 static int d40_set_runtime_config(struct dma_chan *chan,
2714                                   struct dma_slave_config *config)
2715 {
2716         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2717         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2718         enum dma_slave_buswidth src_addr_width, dst_addr_width;
2719         dma_addr_t config_addr;
2720         u32 src_maxburst, dst_maxburst;
2721         int ret;
2722
2723         src_addr_width = config->src_addr_width;
2724         src_maxburst = config->src_maxburst;
2725         dst_addr_width = config->dst_addr_width;
2726         dst_maxburst = config->dst_maxburst;
2727
2728         if (config->direction == DMA_DEV_TO_MEM) {
2729                 config_addr = config->src_addr;
2730
2731                 if (cfg->dir != DMA_DEV_TO_MEM)
2732                         dev_dbg(d40c->base->dev,
2733                                 "channel was not configured for peripheral "
2734                                 "to memory transfer (%d) overriding\n",
2735                                 cfg->dir);
2736                 cfg->dir = DMA_DEV_TO_MEM;
2737
2738                 /* Configure the memory side */
2739                 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2740                         dst_addr_width = src_addr_width;
2741                 if (dst_maxburst == 0)
2742                         dst_maxburst = src_maxburst;
2743
2744         } else if (config->direction == DMA_MEM_TO_DEV) {
2745                 config_addr = config->dst_addr;
2746
2747                 if (cfg->dir != DMA_MEM_TO_DEV)
2748                         dev_dbg(d40c->base->dev,
2749                                 "channel was not configured for memory "
2750                                 "to peripheral transfer (%d) overriding\n",
2751                                 cfg->dir);
2752                 cfg->dir = DMA_MEM_TO_DEV;
2753
2754                 /* Configure the memory side */
2755                 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2756                         src_addr_width = dst_addr_width;
2757                 if (src_maxburst == 0)
2758                         src_maxburst = dst_maxburst;
2759         } else {
2760                 dev_err(d40c->base->dev,
2761                         "unrecognized channel direction %d\n",
2762                         config->direction);
2763                 return -EINVAL;
2764         }
2765
2766         if (config_addr <= 0) {
2767                 dev_err(d40c->base->dev, "no address supplied\n");
2768                 return -EINVAL;
2769         }
2770
2771         if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2772                 dev_err(d40c->base->dev,
2773                         "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2774                         src_maxburst,
2775                         src_addr_width,
2776                         dst_maxburst,
2777                         dst_addr_width);
2778                 return -EINVAL;
2779         }
2780
2781         if (src_maxburst > 16) {
2782                 src_maxburst = 16;
2783                 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2784         } else if (dst_maxburst > 16) {
2785                 dst_maxburst = 16;
2786                 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2787         }
2788
2789         /* Only valid widths are; 1, 2, 4 and 8. */
2790         if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2791             src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
2792             dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2793             dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
2794             ((src_addr_width > 1) && (src_addr_width & 1)) ||
2795             ((dst_addr_width > 1) && (dst_addr_width & 1)))
2796                 return -EINVAL;
2797
2798         cfg->src_info.data_width = src_addr_width;
2799         cfg->dst_info.data_width = dst_addr_width;
2800
2801         ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2802                                           src_maxburst);
2803         if (ret)
2804                 return ret;
2805
2806         ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2807                                           dst_maxburst);
2808         if (ret)
2809                 return ret;
2810
2811         /* Fill in register values */
2812         if (chan_is_logical(d40c))
2813                 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2814         else
2815                 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
2816
2817         /* These settings will take precedence later */
2818         d40c->runtime_addr = config_addr;
2819         d40c->runtime_direction = config->direction;
2820         dev_dbg(d40c->base->dev,
2821                 "configured channel %s for %s, data width %d/%d, "
2822                 "maxburst %d/%d elements, LE, no flow control\n",
2823                 dma_chan_name(chan),
2824                 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2825                 src_addr_width, dst_addr_width,
2826                 src_maxburst, dst_maxburst);
2827
2828         return 0;
2829 }
2830
2831 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2832                        unsigned long arg)
2833 {
2834         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2835
2836         if (d40c->phy_chan == NULL) {
2837                 chan_err(d40c, "Channel is not allocated!\n");
2838                 return -EINVAL;
2839         }
2840
2841         switch (cmd) {
2842         case DMA_TERMINATE_ALL:
2843                 d40_terminate_all(chan);
2844                 return 0;
2845         case DMA_PAUSE:
2846                 return d40_pause(d40c);
2847         case DMA_RESUME:
2848                 return d40_resume(d40c);
2849         case DMA_SLAVE_CONFIG:
2850                 return d40_set_runtime_config(chan,
2851                         (struct dma_slave_config *) arg);
2852         default:
2853                 break;
2854         }
2855
2856         /* Other commands are unimplemented */
2857         return -ENXIO;
2858 }
2859
2860 /* Initialization functions */
2861
2862 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2863                                  struct d40_chan *chans, int offset,
2864                                  int num_chans)
2865 {
2866         int i = 0;
2867         struct d40_chan *d40c;
2868
2869         INIT_LIST_HEAD(&dma->channels);
2870
2871         for (i = offset; i < offset + num_chans; i++) {
2872                 d40c = &chans[i];
2873                 d40c->base = base;
2874                 d40c->chan.device = dma;
2875
2876                 spin_lock_init(&d40c->lock);
2877
2878                 d40c->log_num = D40_PHY_CHAN;
2879
2880                 INIT_LIST_HEAD(&d40c->done);
2881                 INIT_LIST_HEAD(&d40c->active);
2882                 INIT_LIST_HEAD(&d40c->queue);
2883                 INIT_LIST_HEAD(&d40c->pending_queue);
2884                 INIT_LIST_HEAD(&d40c->client);
2885                 INIT_LIST_HEAD(&d40c->prepare_queue);
2886
2887                 tasklet_init(&d40c->tasklet, dma_tasklet,
2888                              (unsigned long) d40c);
2889
2890                 list_add_tail(&d40c->chan.device_node,
2891                               &dma->channels);
2892         }
2893 }
2894
2895 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2896 {
2897         if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2898                 dev->device_prep_slave_sg = d40_prep_slave_sg;
2899
2900         if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2901                 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2902
2903                 /*
2904                  * This controller can only access address at even
2905                  * 32bit boundaries, i.e. 2^2
2906                  */
2907                 dev->copy_align = 2;
2908         }
2909
2910         if (dma_has_cap(DMA_SG, dev->cap_mask))
2911                 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2912
2913         if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2914                 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2915
2916         dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2917         dev->device_free_chan_resources = d40_free_chan_resources;
2918         dev->device_issue_pending = d40_issue_pending;
2919         dev->device_tx_status = d40_tx_status;
2920         dev->device_control = d40_control;
2921         dev->dev = base->dev;
2922 }
2923
2924 static int __init d40_dmaengine_init(struct d40_base *base,
2925                                      int num_reserved_chans)
2926 {
2927         int err ;
2928
2929         d40_chan_init(base, &base->dma_slave, base->log_chans,
2930                       0, base->num_log_chans);
2931
2932         dma_cap_zero(base->dma_slave.cap_mask);
2933         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2934         dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2935
2936         d40_ops_init(base, &base->dma_slave);
2937
2938         err = dma_async_device_register(&base->dma_slave);
2939
2940         if (err) {
2941                 d40_err(base->dev, "Failed to register slave channels\n");
2942                 goto failure1;
2943         }
2944
2945         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2946                       base->num_log_chans, base->num_memcpy_chans);
2947
2948         dma_cap_zero(base->dma_memcpy.cap_mask);
2949         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2950         dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2951
2952         d40_ops_init(base, &base->dma_memcpy);
2953
2954         err = dma_async_device_register(&base->dma_memcpy);
2955
2956         if (err) {
2957                 d40_err(base->dev,
2958                         "Failed to regsiter memcpy only channels\n");
2959                 goto failure2;
2960         }
2961
2962         d40_chan_init(base, &base->dma_both, base->phy_chans,
2963                       0, num_reserved_chans);
2964
2965         dma_cap_zero(base->dma_both.cap_mask);
2966         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2967         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2968         dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2969         dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2970
2971         d40_ops_init(base, &base->dma_both);
2972         err = dma_async_device_register(&base->dma_both);
2973
2974         if (err) {
2975                 d40_err(base->dev,
2976                         "Failed to register logical and physical capable channels\n");
2977                 goto failure3;
2978         }
2979         return 0;
2980 failure3:
2981         dma_async_device_unregister(&base->dma_memcpy);
2982 failure2:
2983         dma_async_device_unregister(&base->dma_slave);
2984 failure1:
2985         return err;
2986 }
2987
2988 /* Suspend resume functionality */
2989 #ifdef CONFIG_PM
2990 static int dma40_pm_suspend(struct device *dev)
2991 {
2992         struct platform_device *pdev = to_platform_device(dev);
2993         struct d40_base *base = platform_get_drvdata(pdev);
2994         int ret = 0;
2995
2996         if (base->lcpa_regulator)
2997                 ret = regulator_disable(base->lcpa_regulator);
2998         return ret;
2999 }
3000
3001 static int dma40_runtime_suspend(struct device *dev)
3002 {
3003         struct platform_device *pdev = to_platform_device(dev);
3004         struct d40_base *base = platform_get_drvdata(pdev);
3005
3006         d40_save_restore_registers(base, true);
3007
3008         /* Don't disable/enable clocks for v1 due to HW bugs */
3009         if (base->rev != 1)
3010                 writel_relaxed(base->gcc_pwr_off_mask,
3011                                base->virtbase + D40_DREG_GCC);
3012
3013         return 0;
3014 }
3015
3016 static int dma40_runtime_resume(struct device *dev)
3017 {
3018         struct platform_device *pdev = to_platform_device(dev);
3019         struct d40_base *base = platform_get_drvdata(pdev);
3020
3021         if (base->initialized)
3022                 d40_save_restore_registers(base, false);
3023
3024         writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3025                        base->virtbase + D40_DREG_GCC);
3026         return 0;
3027 }
3028
3029 static int dma40_resume(struct device *dev)
3030 {
3031         struct platform_device *pdev = to_platform_device(dev);
3032         struct d40_base *base = platform_get_drvdata(pdev);
3033         int ret = 0;
3034
3035         if (base->lcpa_regulator)
3036                 ret = regulator_enable(base->lcpa_regulator);
3037
3038         return ret;
3039 }
3040
3041 static const struct dev_pm_ops dma40_pm_ops = {
3042         .suspend                = dma40_pm_suspend,
3043         .runtime_suspend        = dma40_runtime_suspend,
3044         .runtime_resume         = dma40_runtime_resume,
3045         .resume                 = dma40_resume,
3046 };
3047 #define DMA40_PM_OPS    (&dma40_pm_ops)
3048 #else
3049 #define DMA40_PM_OPS    NULL
3050 #endif
3051
3052 /* Initialization functions. */
3053
3054 static int __init d40_phy_res_init(struct d40_base *base)
3055 {
3056         int i;
3057         int num_phy_chans_avail = 0;
3058         u32 val[2];
3059         int odd_even_bit = -2;
3060         int gcc = D40_DREG_GCC_ENA;
3061
3062         val[0] = readl(base->virtbase + D40_DREG_PRSME);
3063         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3064
3065         for (i = 0; i < base->num_phy_chans; i++) {
3066                 base->phy_res[i].num = i;
3067                 odd_even_bit += 2 * ((i % 2) == 0);
3068                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3069                         /* Mark security only channels as occupied */
3070                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3071                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
3072                         base->phy_res[i].reserved = true;
3073                         gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3074                                                        D40_DREG_GCC_SRC);
3075                         gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3076                                                        D40_DREG_GCC_DST);
3077
3078
3079                 } else {
3080                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3081                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
3082                         base->phy_res[i].reserved = false;
3083                         num_phy_chans_avail++;
3084                 }
3085                 spin_lock_init(&base->phy_res[i].lock);
3086         }
3087
3088         /* Mark disabled channels as occupied */
3089         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
3090                 int chan = base->plat_data->disabled_channels[i];
3091
3092                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3093                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
3094                 base->phy_res[chan].reserved = true;
3095                 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3096                                                D40_DREG_GCC_SRC);
3097                 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3098                                                D40_DREG_GCC_DST);
3099                 num_phy_chans_avail--;
3100         }
3101
3102         /* Mark soft_lli channels */
3103         for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3104                 int chan = base->plat_data->soft_lli_chans[i];
3105
3106                 base->phy_res[chan].use_soft_lli = true;
3107         }
3108
3109         dev_info(base->dev, "%d of %d physical DMA channels available\n",
3110                  num_phy_chans_avail, base->num_phy_chans);
3111
3112         /* Verify settings extended vs standard */
3113         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3114
3115         for (i = 0; i < base->num_phy_chans; i++) {
3116
3117                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3118                     (val[0] & 0x3) != 1)
3119                         dev_info(base->dev,
3120                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
3121                                  __func__, i, val[0] & 0x3);
3122
3123                 val[0] = val[0] >> 2;
3124         }
3125
3126         /*
3127          * To keep things simple, Enable all clocks initially.
3128          * The clocks will get managed later post channel allocation.
3129          * The clocks for the event lines on which reserved channels exists
3130          * are not managed here.
3131          */
3132         writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3133         base->gcc_pwr_off_mask = gcc;
3134
3135         return num_phy_chans_avail;
3136 }
3137
3138 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3139 {
3140         struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
3141         struct clk *clk = NULL;
3142         void __iomem *virtbase = NULL;
3143         struct resource *res = NULL;
3144         struct d40_base *base = NULL;
3145         int num_log_chans = 0;
3146         int num_phy_chans;
3147         int num_memcpy_chans;
3148         int clk_ret = -EINVAL;
3149         int i;
3150         u32 pid;
3151         u32 cid;
3152         u8 rev;
3153
3154         clk = clk_get(&pdev->dev, NULL);
3155         if (IS_ERR(clk)) {
3156                 d40_err(&pdev->dev, "No matching clock found\n");
3157                 goto failure;
3158         }
3159
3160         clk_ret = clk_prepare_enable(clk);
3161         if (clk_ret) {
3162                 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3163                 goto failure;
3164         }
3165
3166         /* Get IO for DMAC base address */
3167         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3168         if (!res)
3169                 goto failure;
3170
3171         if (request_mem_region(res->start, resource_size(res),
3172                                D40_NAME " I/O base") == NULL)
3173                 goto failure;
3174
3175         virtbase = ioremap(res->start, resource_size(res));
3176         if (!virtbase)
3177                 goto failure;
3178
3179         /* This is just a regular AMBA PrimeCell ID actually */
3180         for (pid = 0, i = 0; i < 4; i++)
3181                 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3182                         & 255) << (i * 8);
3183         for (cid = 0, i = 0; i < 4; i++)
3184                 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3185                         & 255) << (i * 8);
3186
3187         if (cid != AMBA_CID) {
3188                 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3189                 goto failure;
3190         }
3191         if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
3192                 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
3193                         AMBA_MANF_BITS(pid),
3194                         AMBA_VENDOR_ST);
3195                 goto failure;
3196         }
3197         /*
3198          * HW revision:
3199          * DB8500ed has revision 0
3200          * ? has revision 1
3201          * DB8500v1 has revision 2
3202          * DB8500v2 has revision 3
3203          * AP9540v1 has revision 4
3204          * DB8540v1 has revision 4
3205          */
3206         rev = AMBA_REV_BITS(pid);
3207         if (rev < 2) {
3208                 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3209                 goto failure;
3210         }
3211
3212         /* The number of physical channels on this HW */
3213         if (plat_data->num_of_phy_chans)
3214                 num_phy_chans = plat_data->num_of_phy_chans;
3215         else
3216                 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3217
3218         /* The number of channels used for memcpy */
3219         if (plat_data->num_of_memcpy_chans)
3220                 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3221         else
3222                 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3223
3224         num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3225
3226         dev_info(&pdev->dev,
3227                  "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n",
3228                  rev, res->start, num_phy_chans, num_log_chans);
3229
3230         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3231                        (num_phy_chans + num_log_chans + num_memcpy_chans) *
3232                        sizeof(struct d40_chan), GFP_KERNEL);
3233
3234         if (base == NULL) {
3235                 d40_err(&pdev->dev, "Out of memory\n");
3236                 goto failure;
3237         }
3238
3239         base->rev = rev;
3240         base->clk = clk;
3241         base->num_memcpy_chans = num_memcpy_chans;
3242         base->num_phy_chans = num_phy_chans;
3243         base->num_log_chans = num_log_chans;
3244         base->phy_start = res->start;
3245         base->phy_size = resource_size(res);
3246         base->virtbase = virtbase;
3247         base->plat_data = plat_data;
3248         base->dev = &pdev->dev;
3249         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3250         base->log_chans = &base->phy_chans[num_phy_chans];
3251
3252         if (base->plat_data->num_of_phy_chans == 14) {
3253                 base->gen_dmac.backup = d40_backup_regs_v4b;
3254                 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3255                 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3256                 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3257                 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3258                 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3259                 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3260                 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3261                 base->gen_dmac.il = il_v4b;
3262                 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3263                 base->gen_dmac.init_reg = dma_init_reg_v4b;
3264                 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3265         } else {
3266                 if (base->rev >= 3) {
3267                         base->gen_dmac.backup = d40_backup_regs_v4a;
3268                         base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3269                 }
3270                 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3271                 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3272                 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3273                 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3274                 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3275                 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3276                 base->gen_dmac.il = il_v4a;
3277                 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3278                 base->gen_dmac.init_reg = dma_init_reg_v4a;
3279                 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3280         }
3281
3282         base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3283                                 GFP_KERNEL);
3284         if (!base->phy_res)
3285                 goto failure;
3286
3287         base->lookup_phy_chans = kzalloc(num_phy_chans *
3288                                          sizeof(struct d40_chan *),
3289                                          GFP_KERNEL);
3290         if (!base->lookup_phy_chans)
3291                 goto failure;
3292
3293         base->lookup_log_chans = kzalloc(num_log_chans *
3294                                          sizeof(struct d40_chan *),
3295                                          GFP_KERNEL);
3296         if (!base->lookup_log_chans)
3297                 goto failure;
3298
3299         base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3300                                             sizeof(d40_backup_regs_chan),
3301                                             GFP_KERNEL);
3302         if (!base->reg_val_backup_chan)
3303                 goto failure;
3304
3305         base->lcla_pool.alloc_map =
3306                 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3307                         * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
3308         if (!base->lcla_pool.alloc_map)
3309                 goto failure;
3310
3311         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3312                                             0, SLAB_HWCACHE_ALIGN,
3313                                             NULL);
3314         if (base->desc_slab == NULL)
3315                 goto failure;
3316
3317         return base;
3318
3319 failure:
3320         if (!clk_ret)
3321                 clk_disable_unprepare(clk);
3322         if (!IS_ERR(clk))
3323                 clk_put(clk);
3324         if (virtbase)
3325                 iounmap(virtbase);
3326         if (res)
3327                 release_mem_region(res->start,
3328                                    resource_size(res));
3329         if (virtbase)
3330                 iounmap(virtbase);
3331
3332         if (base) {
3333                 kfree(base->lcla_pool.alloc_map);
3334                 kfree(base->reg_val_backup_chan);
3335                 kfree(base->lookup_log_chans);
3336                 kfree(base->lookup_phy_chans);
3337                 kfree(base->phy_res);
3338                 kfree(base);
3339         }
3340
3341         return NULL;
3342 }
3343
3344 static void __init d40_hw_init(struct d40_base *base)
3345 {
3346
3347         int i;
3348         u32 prmseo[2] = {0, 0};
3349         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3350         u32 pcmis = 0;
3351         u32 pcicr = 0;
3352         struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3353         u32 reg_size = base->gen_dmac.init_reg_size;
3354
3355         for (i = 0; i < reg_size; i++)
3356                 writel(dma_init_reg[i].val,
3357                        base->virtbase + dma_init_reg[i].reg);
3358
3359         /* Configure all our dma channels to default settings */
3360         for (i = 0; i < base->num_phy_chans; i++) {
3361
3362                 activeo[i % 2] = activeo[i % 2] << 2;
3363
3364                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3365                     == D40_ALLOC_PHY) {
3366                         activeo[i % 2] |= 3;
3367                         continue;
3368                 }
3369
3370                 /* Enable interrupt # */
3371                 pcmis = (pcmis << 1) | 1;
3372
3373                 /* Clear interrupt # */
3374                 pcicr = (pcicr << 1) | 1;
3375
3376                 /* Set channel to physical mode */
3377                 prmseo[i % 2] = prmseo[i % 2] << 2;
3378                 prmseo[i % 2] |= 1;
3379
3380         }
3381
3382         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3383         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3384         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3385         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3386
3387         /* Write which interrupt to enable */
3388         writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3389
3390         /* Write which interrupt to clear */
3391         writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3392
3393         /* These are __initdata and cannot be accessed after init */
3394         base->gen_dmac.init_reg = NULL;
3395         base->gen_dmac.init_reg_size = 0;
3396 }
3397
3398 static int __init d40_lcla_allocate(struct d40_base *base)
3399 {
3400         struct d40_lcla_pool *pool = &base->lcla_pool;
3401         unsigned long *page_list;
3402         int i, j;
3403         int ret = 0;
3404
3405         /*
3406          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3407          * To full fill this hardware requirement without wasting 256 kb
3408          * we allocate pages until we get an aligned one.
3409          */
3410         page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3411                             GFP_KERNEL);
3412
3413         if (!page_list) {
3414                 ret = -ENOMEM;
3415                 goto failure;
3416         }
3417
3418         /* Calculating how many pages that are required */
3419         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3420
3421         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3422                 page_list[i] = __get_free_pages(GFP_KERNEL,
3423                                                 base->lcla_pool.pages);
3424                 if (!page_list[i]) {
3425
3426                         d40_err(base->dev, "Failed to allocate %d pages.\n",
3427                                 base->lcla_pool.pages);
3428
3429                         for (j = 0; j < i; j++)
3430                                 free_pages(page_list[j], base->lcla_pool.pages);
3431                         goto failure;
3432                 }
3433
3434                 if ((virt_to_phys((void *)page_list[i]) &
3435                      (LCLA_ALIGNMENT - 1)) == 0)
3436                         break;
3437         }
3438
3439         for (j = 0; j < i; j++)
3440                 free_pages(page_list[j], base->lcla_pool.pages);
3441
3442         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3443                 base->lcla_pool.base = (void *)page_list[i];
3444         } else {
3445                 /*
3446                  * After many attempts and no succees with finding the correct
3447                  * alignment, try with allocating a big buffer.
3448                  */
3449                 dev_warn(base->dev,
3450                          "[%s] Failed to get %d pages @ 18 bit align.\n",
3451                          __func__, base->lcla_pool.pages);
3452                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3453                                                          base->num_phy_chans +
3454                                                          LCLA_ALIGNMENT,
3455                                                          GFP_KERNEL);
3456                 if (!base->lcla_pool.base_unaligned) {
3457                         ret = -ENOMEM;
3458                         goto failure;
3459                 }
3460
3461                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3462                                                  LCLA_ALIGNMENT);
3463         }
3464
3465         pool->dma_addr = dma_map_single(base->dev, pool->base,
3466                                         SZ_1K * base->num_phy_chans,
3467                                         DMA_TO_DEVICE);
3468         if (dma_mapping_error(base->dev, pool->dma_addr)) {
3469                 pool->dma_addr = 0;
3470                 ret = -ENOMEM;
3471                 goto failure;
3472         }
3473
3474         writel(virt_to_phys(base->lcla_pool.base),
3475                base->virtbase + D40_DREG_LCLA);
3476 failure:
3477         kfree(page_list);
3478         return ret;
3479 }
3480
3481 static int __init d40_of_probe(struct platform_device *pdev,
3482                                struct device_node *np)
3483 {
3484         struct stedma40_platform_data *pdata;
3485         int num_phy = 0, num_memcpy = 0, num_disabled = 0;
3486         const const __be32 *list;
3487
3488         pdata = devm_kzalloc(&pdev->dev,
3489                              sizeof(struct stedma40_platform_data),
3490                              GFP_KERNEL);
3491         if (!pdata)
3492                 return -ENOMEM;
3493
3494         /* If absent this value will be obtained from h/w. */
3495         of_property_read_u32(np, "dma-channels", &num_phy);
3496         if (num_phy > 0)
3497                 pdata->num_of_phy_chans = num_phy;
3498
3499         list = of_get_property(np, "memcpy-channels", &num_memcpy);
3500         num_memcpy /= sizeof(*list);
3501
3502         if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3503                 d40_err(&pdev->dev,
3504                         "Invalid number of memcpy channels specified (%d)\n",
3505                         num_memcpy);
3506                 return -EINVAL;
3507         }
3508         pdata->num_of_memcpy_chans = num_memcpy;
3509
3510         of_property_read_u32_array(np, "memcpy-channels",
3511                                    dma40_memcpy_channels,
3512                                    num_memcpy);
3513
3514         list = of_get_property(np, "disabled-channels", &num_disabled);
3515         num_disabled /= sizeof(*list);
3516
3517         if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
3518                 d40_err(&pdev->dev,
3519                         "Invalid number of disabled channels specified (%d)\n",
3520                         num_disabled);
3521                 return -EINVAL;
3522         }
3523
3524         of_property_read_u32_array(np, "disabled-channels",
3525                                    pdata->disabled_channels,
3526                                    num_disabled);
3527         pdata->disabled_channels[num_disabled] = -1;
3528
3529         pdev->dev.platform_data = pdata;
3530
3531         return 0;
3532 }
3533
3534 static int __init d40_probe(struct platform_device *pdev)
3535 {
3536         struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
3537         struct device_node *np = pdev->dev.of_node;
3538         int ret = -ENOENT;
3539         struct d40_base *base = NULL;
3540         struct resource *res = NULL;
3541         int num_reserved_chans;
3542         u32 val;
3543
3544         if (!plat_data) {
3545                 if (np) {
3546                         if(d40_of_probe(pdev, np)) {
3547                                 ret = -ENOMEM;
3548                                 goto failure;
3549                         }
3550                 } else {
3551                         d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3552                         goto failure;
3553                 }
3554         }
3555
3556         base = d40_hw_detect_init(pdev);
3557         if (!base)
3558                 goto failure;
3559
3560         num_reserved_chans = d40_phy_res_init(base);
3561
3562         platform_set_drvdata(pdev, base);
3563
3564         spin_lock_init(&base->interrupt_lock);
3565         spin_lock_init(&base->execmd_lock);
3566
3567         /* Get IO for logical channel parameter address */
3568         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3569         if (!res) {
3570                 ret = -ENOENT;
3571                 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3572                 goto failure;
3573         }
3574         base->lcpa_size = resource_size(res);
3575         base->phy_lcpa = res->start;
3576
3577         if (request_mem_region(res->start, resource_size(res),
3578                                D40_NAME " I/O lcpa") == NULL) {
3579                 ret = -EBUSY;
3580                 d40_err(&pdev->dev,
3581                         "Failed to request LCPA region 0x%x-0x%x\n",
3582                         res->start, res->end);
3583                 goto failure;
3584         }
3585
3586         /* We make use of ESRAM memory for this. */
3587         val = readl(base->virtbase + D40_DREG_LCPA);
3588         if (res->start != val && val != 0) {
3589                 dev_warn(&pdev->dev,
3590                          "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3591                          __func__, val, res->start);
3592         } else
3593                 writel(res->start, base->virtbase + D40_DREG_LCPA);
3594
3595         base->lcpa_base = ioremap(res->start, resource_size(res));
3596         if (!base->lcpa_base) {
3597                 ret = -ENOMEM;
3598                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3599                 goto failure;
3600         }
3601         /* If lcla has to be located in ESRAM we don't need to allocate */
3602         if (base->plat_data->use_esram_lcla) {
3603                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3604                                                         "lcla_esram");
3605                 if (!res) {
3606                         ret = -ENOENT;
3607                         d40_err(&pdev->dev,
3608                                 "No \"lcla_esram\" memory resource\n");
3609                         goto failure;
3610                 }
3611                 base->lcla_pool.base = ioremap(res->start,
3612                                                 resource_size(res));
3613                 if (!base->lcla_pool.base) {
3614                         ret = -ENOMEM;
3615                         d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3616                         goto failure;
3617                 }
3618                 writel(res->start, base->virtbase + D40_DREG_LCLA);
3619
3620         } else {
3621                 ret = d40_lcla_allocate(base);
3622                 if (ret) {
3623                         d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3624                         goto failure;
3625                 }
3626         }
3627
3628         spin_lock_init(&base->lcla_pool.lock);
3629
3630         base->irq = platform_get_irq(pdev, 0);
3631
3632         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3633         if (ret) {
3634                 d40_err(&pdev->dev, "No IRQ defined\n");
3635                 goto failure;
3636         }
3637
3638         pm_runtime_irq_safe(base->dev);
3639         pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3640         pm_runtime_use_autosuspend(base->dev);
3641         pm_runtime_enable(base->dev);
3642         pm_runtime_resume(base->dev);
3643
3644         if (base->plat_data->use_esram_lcla) {
3645
3646                 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3647                 if (IS_ERR(base->lcpa_regulator)) {
3648                         d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3649                         ret = PTR_ERR(base->lcpa_regulator);
3650                         base->lcpa_regulator = NULL;
3651                         goto failure;
3652                 }
3653
3654                 ret = regulator_enable(base->lcpa_regulator);
3655                 if (ret) {
3656                         d40_err(&pdev->dev,
3657                                 "Failed to enable lcpa_regulator\n");
3658                         regulator_put(base->lcpa_regulator);
3659                         base->lcpa_regulator = NULL;
3660                         goto failure;
3661                 }
3662         }
3663
3664         base->initialized = true;
3665         ret = d40_dmaengine_init(base, num_reserved_chans);
3666         if (ret)
3667                 goto failure;
3668
3669         base->dev->dma_parms = &base->dma_parms;
3670         ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3671         if (ret) {
3672                 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3673                 goto failure;
3674         }
3675
3676         d40_hw_init(base);
3677
3678         if (np) {
3679                 ret = of_dma_controller_register(np, d40_xlate, NULL);
3680                 if (ret)
3681                         dev_err(&pdev->dev,
3682                                 "could not register of_dma_controller\n");
3683         }
3684
3685         dev_info(base->dev, "initialized\n");
3686         return 0;
3687
3688 failure:
3689         if (base) {
3690                 if (base->desc_slab)
3691                         kmem_cache_destroy(base->desc_slab);
3692                 if (base->virtbase)
3693                         iounmap(base->virtbase);
3694
3695                 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3696                         iounmap(base->lcla_pool.base);
3697                         base->lcla_pool.base = NULL;
3698                 }
3699
3700                 if (base->lcla_pool.dma_addr)
3701                         dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3702                                          SZ_1K * base->num_phy_chans,
3703                                          DMA_TO_DEVICE);
3704
3705                 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3706                         free_pages((unsigned long)base->lcla_pool.base,
3707                                    base->lcla_pool.pages);
3708
3709                 kfree(base->lcla_pool.base_unaligned);
3710
3711                 if (base->phy_lcpa)
3712                         release_mem_region(base->phy_lcpa,
3713                                            base->lcpa_size);
3714                 if (base->phy_start)
3715                         release_mem_region(base->phy_start,
3716                                            base->phy_size);
3717                 if (base->clk) {
3718                         clk_disable_unprepare(base->clk);
3719                         clk_put(base->clk);
3720                 }
3721
3722                 if (base->lcpa_regulator) {
3723                         regulator_disable(base->lcpa_regulator);
3724                         regulator_put(base->lcpa_regulator);
3725                 }
3726
3727                 kfree(base->lcla_pool.alloc_map);
3728                 kfree(base->lookup_log_chans);
3729                 kfree(base->lookup_phy_chans);
3730                 kfree(base->phy_res);
3731                 kfree(base);
3732         }
3733
3734         d40_err(&pdev->dev, "probe failed\n");
3735         return ret;
3736 }
3737
3738 static const struct of_device_id d40_match[] = {
3739         { .compatible = "stericsson,dma40", },
3740         {}
3741 };
3742
3743 static struct platform_driver d40_driver = {
3744         .driver = {
3745                 .owner = THIS_MODULE,
3746                 .name  = D40_NAME,
3747                 .pm = DMA40_PM_OPS,
3748                 .of_match_table = d40_match,
3749         },
3750 };
3751
3752 static int __init stedma40_init(void)
3753 {
3754         return platform_driver_probe(&d40_driver, d40_probe);
3755 }
3756 subsys_initcall(stedma40_init);