drivers/dma/ste_dma40.c

   1 /*
   2  * Copyright (C) Ericsson AB 2007-2008
   3  * Copyright (C) ST-Ericsson SA 2008-2010
   4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/slab.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16
  17 #include <plat/ste_dma40.h>
  18
  19 #include "ste_dma40_ll.h"
  20
  21 #define D40_NAME "dma40"
  22
  23 #define D40_PHY_CHAN -1
  24
  25 /* For masking out/in 2 bit channel positions */
  26 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
  27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  28
  29 /* Maximum iterations taken before giving up suspending a channel */
  30 #define D40_SUSPEND_MAX_IT 500
  31
  32 /* Hardware requirement on LCLA alignment */
  33 #define LCLA_ALIGNMENT 0x40000
  34
  35 /* Max number of links per event group */
  36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
  37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
  38
  39 /* Attempts before giving up to trying to get pages that are aligned */
  40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
  41
  42 /* Bit markings for allocation map */
  43 #define D40_ALLOC_FREE          (1 << 31)
  44 #define D40_ALLOC_PHY           (1 << 30)
  45 #define D40_ALLOC_LOG_FREE      0
  46
  47 /* Hardware designer of the block */
  48 #define D40_HW_DESIGNER 0x8
  49
  50 /**
  51  * enum 40_command - The different commands and/or statuses.
  52  *
  53  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
  54  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
  55  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
  56  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
  57  */
  58 enum d40_command {
  59         D40_DMA_STOP            = 0,
  60         D40_DMA_RUN             = 1,
  61         D40_DMA_SUSPEND_REQ     = 2,
  62         D40_DMA_SUSPENDED       = 3
  63 };
  64
  65 /**
  66  * struct d40_lli_pool - Structure for keeping LLIs in memory
  67  *
  68  * @base: Pointer to memory area when the pre_alloc_lli's are not large
  69  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
  70  * pre_alloc_lli is used.
  71  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
  72  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
  73  * one buffer to one buffer.
  74  */
  75 struct d40_lli_pool {
  76         void    *base;
  77         int      size;
  78         /* Space for dst and src, plus an extra for padding */
  79         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
  80 };
  81
  82 /**
  83  * struct d40_desc - A descriptor is one DMA job.
  84  *
  85  * @lli_phy: LLI settings for physical channel. Both src and dst=
  86  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
  87  * lli_len equals one.
  88  * @lli_log: Same as above but for logical channels.
  89  * @lli_pool: The pool with two entries pre-allocated.
  90  * @lli_len: Number of llis of current descriptor.
  91  * @lli_current: Number of transfered llis.
  92  * @lcla_alloc: Number of LCLA entries allocated.
  93  * @txd: DMA engine struct. Used for among other things for communication
  94  * during a transfer.
  95  * @node: List entry.
  96  * @is_in_client_list: true if the client owns this descriptor.
  97  * the previous one.
  98  *
  99  * This descriptor is used for both logical and physical transfers.
 100  */
 101 struct d40_desc {
 102         /* LLI physical */
 103         struct d40_phy_lli_bidir         lli_phy;
 104         /* LLI logical */
 105         struct d40_log_lli_bidir         lli_log;
 106
 107         struct d40_lli_pool              lli_pool;
 108         int                              lli_len;
 109         int                              lli_current;
 110         int                              lcla_alloc;
 111
 112         struct dma_async_tx_descriptor   txd;
 113         struct list_head                 node;
 114
 115         bool                             is_in_client_list;
 116 };
 117
 118 /**
 119  * struct d40_lcla_pool - LCLA pool settings and data.
 120  *
 121  * @base: The virtual address of LCLA. 18 bit aligned.
 122  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
 123  * This pointer is only there for clean-up on error.
 124  * @pages: The number of pages needed for all physical channels.
 125  * Only used later for clean-up on error
 126  * @lock: Lock to protect the content in this struct.
 127  * @alloc_map: big map over which LCLA entry is own by which job.
 128  */
 129 struct d40_lcla_pool {
 130         void            *base;
 131         void            *base_unaligned;
 132         int              pages;
 133         spinlock_t       lock;
 134         struct d40_desc **alloc_map;
 135 };
 136
 137 /**
 138  * struct d40_phy_res - struct for handling eventlines mapped to physical
 139  * channels.
 140  *
 141  * @lock: A lock protection this entity.
 142  * @num: The physical channel number of this entity.
 143  * @allocated_src: Bit mapped to show which src event line's are mapped to
 144  * this physical channel. Can also be free or physically allocated.
 145  * @allocated_dst: Same as for src but is dst.
 146  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
 147  * event line number.
 148  */
 149 struct d40_phy_res {
 150         spinlock_t lock;
 151         int        num;
 152         u32        allocated_src;
 153         u32        allocated_dst;
 154 };
 155
 156 struct d40_base;
 157
 158 /**
 159  * struct d40_chan - Struct that describes a channel.
 160  *
 161  * @lock: A spinlock to protect this struct.
 162  * @log_num: The logical number, if any of this channel.
 163  * @completed: Starts with 1, after first interrupt it is set to dma engine's
 164  * current cookie.
 165  * @pending_tx: The number of pending transfers. Used between interrupt handler
 166  * and tasklet.
 167  * @busy: Set to true when transfer is ongoing on this channel.
 168  * @phy_chan: Pointer to physical channel which this instance runs on. If this
 169  * point is NULL, then the channel is not allocated.
 170  * @chan: DMA engine handle.
 171  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
 172  * transfer and call client callback.
 173  * @client: Cliented owned descriptor list.
 174  * @active: Active descriptor.
 175  * @queue: Queued jobs.
 176  * @dma_cfg: The client configuration of this dma channel.
 177  * @configured: whether the dma_cfg configuration is valid
 178  * @base: Pointer to the device instance struct.
 179  * @src_def_cfg: Default cfg register setting for src.
 180  * @dst_def_cfg: Default cfg register setting for dst.
 181  * @log_def: Default logical channel settings.
 182  * @lcla: Space for one dst src pair for logical channel transfers.
 183  * @lcpa: Pointer to dst and src lcpa settings.
 184  *
 185  * This struct can either "be" a logical or a physical channel.
 186  */
 187 struct d40_chan {
 188         spinlock_t                       lock;
 189         int                              log_num;
 190         /* ID of the most recent completed transfer */
 191         int                              completed;
 192         int                              pending_tx;
 193         bool                             busy;
 194         struct d40_phy_res              *phy_chan;
 195         struct dma_chan                  chan;
 196         struct tasklet_struct            tasklet;
 197         struct list_head                 client;
 198         struct list_head                 active;
 199         struct list_head                 queue;
 200         struct stedma40_chan_cfg         dma_cfg;
 201         bool                             configured;
 202         struct d40_base                 *base;
 203         /* Default register configurations */
 204         u32                              src_def_cfg;
 205         u32                              dst_def_cfg;
 206         struct d40_def_lcsp              log_def;
 207         struct d40_log_lli_full         *lcpa;
 208         /* Runtime reconfiguration */
 209         dma_addr_t                      runtime_addr;
 210         enum dma_data_direction         runtime_direction;
 211 };
 212
 213 /**
 214  * struct d40_base - The big global struct, one for each probe'd instance.
 215  *
 216  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
 217  * @execmd_lock: Lock for execute command usage since several channels share
 218  * the same physical register.
 219  * @dev: The device structure.
 220  * @virtbase: The virtual base address of the DMA's register.
 221  * @rev: silicon revision detected.
 222  * @clk: Pointer to the DMA clock structure.
 223  * @phy_start: Physical memory start of the DMA registers.
 224  * @phy_size: Size of the DMA register map.
 225  * @irq: The IRQ number.
 226  * @num_phy_chans: The number of physical channels. Read from HW. This
 227  * is the number of available channels for this driver, not counting "Secure
 228  * mode" allocated physical channels.
 229  * @num_log_chans: The number of logical channels. Calculated from
 230  * num_phy_chans.
 231  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
 232  * @dma_slave: dma_device channels that can do only do slave transfers.
 233  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
 234  * @log_chans: Room for all possible logical channels in system.
 235  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
 236  * to log_chans entries.
 237  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
 238  * to phy_chans entries.
 239  * @plat_data: Pointer to provided platform_data which is the driver
 240  * configuration.
 241  * @phy_res: Vector containing all physical channels.
 242  * @lcla_pool: lcla pool settings and data.
 243  * @lcpa_base: The virtual mapped address of LCPA.
 244  * @phy_lcpa: The physical address of the LCPA.
 245  * @lcpa_size: The size of the LCPA area.
 246  * @desc_slab: cache for descriptors.
 247  */
 248 struct d40_base {
 249         spinlock_t                       interrupt_lock;
 250         spinlock_t                       execmd_lock;
 251         struct device                    *dev;
 252         void __iomem                     *virtbase;
 253         u8                                rev:4;
 254         struct clk                       *clk;
 255         phys_addr_t                       phy_start;
 256         resource_size_t                   phy_size;
 257         int                               irq;
 258         int                               num_phy_chans;
 259         int                               num_log_chans;
 260         struct dma_device                 dma_both;
 261         struct dma_device                 dma_slave;
 262         struct dma_device                 dma_memcpy;
 263         struct d40_chan                  *phy_chans;
 264         struct d40_chan                  *log_chans;
 265         struct d40_chan                 **lookup_log_chans;
 266         struct d40_chan                 **lookup_phy_chans;
 267         struct stedma40_platform_data    *plat_data;
 268         /* Physical half channels */
 269         struct d40_phy_res               *phy_res;
 270         struct d40_lcla_pool              lcla_pool;
 271         void                             *lcpa_base;
 272         dma_addr_t                        phy_lcpa;
 273         resource_size_t                   lcpa_size;
 274         struct kmem_cache                *desc_slab;
 275 };
 276
 277 /**
 278  * struct d40_interrupt_lookup - lookup table for interrupt handler
 279  *
 280  * @src: Interrupt mask register.
 281  * @clr: Interrupt clear register.
 282  * @is_error: true if this is an error interrupt.
 283  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
 284  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
 285  */
 286 struct d40_interrupt_lookup {
 287         u32 src;
 288         u32 clr;
 289         bool is_error;
 290         int offset;
 291 };
 292
 293 /**
 294  * struct d40_reg_val - simple lookup struct
 295  *
 296  * @reg: The register.
 297  * @val: The value that belongs to the register in reg.
 298  */
 299 struct d40_reg_val {
 300         unsigned int reg;
 301         unsigned int val;
 302 };
 303
 304 static struct device *chan2dev(struct d40_chan *d40c)
 305 {
 306         return &d40c->chan.dev->device;
 307 }
 308
 309 static bool chan_is_physical(struct d40_chan *chan)
 310 {
 311         return chan->log_num == D40_PHY_CHAN;
 312 }
 313
 314 static bool chan_is_logical(struct d40_chan *chan)
 315 {
 316         return !chan_is_physical(chan);
 317 }
 318
 319 static void __iomem *chan_base(struct d40_chan *chan)
 320 {
 321         return chan->base->virtbase + D40_DREG_PCBASE +
 322                chan->phy_chan->num * D40_DREG_PCDELTA;
 323 }
 324
 325 #define d40_err(dev, format, arg...)            \
 326         dev_err(dev, "[%s] " format, __func__, ## arg)
 327
 328 #define chan_err(d40c, format, arg...)          \
 329         d40_err(chan2dev(d40c), format, ## arg)
 330
 331 static int d40_pool_lli_alloc(struct d40_desc *d40d,
 332                               int lli_len, bool is_log)
 333 {
 334         u32 align;
 335         void *base;
 336
 337         if (is_log)
 338                 align = sizeof(struct d40_log_lli);
 339         else
 340                 align = sizeof(struct d40_phy_lli);
 341
 342         if (lli_len == 1) {
 343                 base = d40d->lli_pool.pre_alloc_lli;
 344                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
 345                 d40d->lli_pool.base = NULL;
 346         } else {
 347                 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
 348
 349                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
 350                 d40d->lli_pool.base = base;
 351
 352                 if (d40d->lli_pool.base == NULL)
 353                         return -ENOMEM;
 354         }
 355
 356         if (is_log) {
 357                 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
 358                                               align);
 359                 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
 360                                               align);
 361         } else {
 362                 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
 363                                               align);
 364                 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
 365                                               align);
 366         }
 367
 368         return 0;
 369 }
 370
 371 static void d40_pool_lli_free(struct d40_desc *d40d)
 372 {
 373         kfree(d40d->lli_pool.base);
 374         d40d->lli_pool.base = NULL;
 375         d40d->lli_pool.size = 0;
 376         d40d->lli_log.src = NULL;
 377         d40d->lli_log.dst = NULL;
 378         d40d->lli_phy.src = NULL;
 379         d40d->lli_phy.dst = NULL;
 380 }
 381
 382 static int d40_lcla_alloc_one(struct d40_chan *d40c,
 383                               struct d40_desc *d40d)
 384 {
 385         unsigned long flags;
 386         int i;
 387         int ret = -EINVAL;
 388         int p;
 389
 390         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 391
 392         p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
 393
 394         /*
 395          * Allocate both src and dst at the same time, therefore the half
 396          * start on 1 since 0 can't be used since zero is used as end marker.
 397          */
 398         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 399                 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
 400                         d40c->base->lcla_pool.alloc_map[p + i] = d40d;
 401                         d40d->lcla_alloc++;
 402                         ret = i;
 403                         break;
 404                 }
 405         }
 406
 407         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 408
 409         return ret;
 410 }
 411
 412 static int d40_lcla_free_all(struct d40_chan *d40c,
 413                              struct d40_desc *d40d)
 414 {
 415         unsigned long flags;
 416         int i;
 417         int ret = -EINVAL;
 418
 419         if (chan_is_physical(d40c))
 420                 return 0;
 421
 422         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 423
 424         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 425                 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
 426                                                     D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
 427                         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
 428                                                         D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
 429                         d40d->lcla_alloc--;
 430                         if (d40d->lcla_alloc == 0) {
 431                                 ret = 0;
 432                                 break;
 433                         }
 434                 }
 435         }
 436
 437         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 438
 439         return ret;
 440
 441 }
 442
 443 static void d40_desc_remove(struct d40_desc *d40d)
 444 {
 445         list_del(&d40d->node);
 446 }
 447
 448 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
 449 {
 450         struct d40_desc *desc = NULL;
 451
 452         if (!list_empty(&d40c->client)) {
 453                 struct d40_desc *d;
 454                 struct d40_desc *_d;
 455
 456                 list_for_each_entry_safe(d, _d, &d40c->client, node)
 457                         if (async_tx_test_ack(&d->txd)) {
 458                                 d40_pool_lli_free(d);
 459                                 d40_desc_remove(d);
 460                                 desc = d;
 461                                 memset(desc, 0, sizeof(*desc));
 462                                 break;
 463                         }
 464         }
 465
 466         if (!desc)
 467                 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
 468
 469         if (desc)
 470                 INIT_LIST_HEAD(&desc->node);
 471
 472         return desc;
 473 }
 474
 475 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
 476 {
 477
 478         d40_lcla_free_all(d40c, d40d);
 479         kmem_cache_free(d40c->base->desc_slab, d40d);
 480 }
 481
 482 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
 483 {
 484         list_add_tail(&desc->node, &d40c->active);
 485 }
 486
 487 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
 488 {
 489         int curr_lcla = -EINVAL, next_lcla;
 490
 491         if (chan_is_physical(d40c)) {
 492                 d40_phy_lli_write(d40c->base->virtbase,
 493                                   d40c->phy_chan->num,
 494                                   d40d->lli_phy.dst,
 495                                   d40d->lli_phy.src);
 496                 d40d->lli_current = d40d->lli_len;
 497         } else {
 498
 499                 if ((d40d->lli_len - d40d->lli_current) > 1)
 500                         curr_lcla = d40_lcla_alloc_one(d40c, d40d);
 501
 502                 d40_log_lli_lcpa_write(d40c->lcpa,
 503                                        &d40d->lli_log.dst[d40d->lli_current],
 504                                        &d40d->lli_log.src[d40d->lli_current],
 505                                        curr_lcla);
 506
 507                 d40d->lli_current++;
 508                 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
 509                         struct d40_log_lli *lcla;
 510
 511                         if (d40d->lli_current + 1 < d40d->lli_len)
 512                                 next_lcla = d40_lcla_alloc_one(d40c, d40d);
 513                         else
 514                                 next_lcla = -EINVAL;
 515
 516                         lcla = d40c->base->lcla_pool.base +
 517                                 d40c->phy_chan->num * 1024 +
 518                                 8 * curr_lcla * 2;
 519
 520                         d40_log_lli_lcla_write(lcla,
 521                                                &d40d->lli_log.dst[d40d->lli_current],
 522                                                &d40d->lli_log.src[d40d->lli_current],
 523                                                next_lcla);
 524
 525                         (void) dma_map_single(d40c->base->dev, lcla,
 526                                               2 * sizeof(struct d40_log_lli),
 527                                               DMA_TO_DEVICE);
 528
 529                         curr_lcla = next_lcla;
 530
 531                         if (curr_lcla == -EINVAL) {
 532                                 d40d->lli_current++;
 533                                 break;
 534                         }
 535
 536                 }
 537         }
 538 }
 539
 540 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
 541 {
 542         struct d40_desc *d;
 543
 544         if (list_empty(&d40c->active))
 545                 return NULL;
 546
 547         d = list_first_entry(&d40c->active,
 548                              struct d40_desc,
 549                              node);
 550         return d;
 551 }
 552
 553 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
 554 {
 555         list_add_tail(&desc->node, &d40c->queue);
 556 }
 557
 558 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
 559 {
 560         struct d40_desc *d;
 561
 562         if (list_empty(&d40c->queue))
 563                 return NULL;
 564
 565         d = list_first_entry(&d40c->queue,
 566                              struct d40_desc,
 567                              node);
 568         return d;
 569 }
 570
 571 static int d40_psize_2_burst_size(bool is_log, int psize)
 572 {
 573         if (is_log) {
 574                 if (psize == STEDMA40_PSIZE_LOG_1)
 575                         return 1;
 576         } else {
 577                 if (psize == STEDMA40_PSIZE_PHY_1)
 578                         return 1;
 579         }
 580
 581         return 2 << psize;
 582 }
 583
 584 /*
 585  * The dma only supports transmitting packages up to
 586  * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
 587  * dma elements required to send the entire sg list
 588  */
 589 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
 590 {
 591         int dmalen;
 592         u32 max_w = max(data_width1, data_width2);
 593         u32 min_w = min(data_width1, data_width2);
 594         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
 595
 596         if (seg_max > STEDMA40_MAX_SEG_SIZE)
 597                 seg_max -= (1 << max_w);
 598
 599         if (!IS_ALIGNED(size, 1 << max_w))
 600                 return -EINVAL;
 601
 602         if (size <= seg_max)
 603                 dmalen = 1;
 604         else {
 605                 dmalen = size / seg_max;
 606                 if (dmalen * seg_max < size)
 607                         dmalen++;
 608         }
 609         return dmalen;
 610 }
 611
 612 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
 613                            u32 data_width1, u32 data_width2)
 614 {
 615         struct scatterlist *sg;
 616         int i;
 617         int len = 0;
 618         int ret;
 619
 620         for_each_sg(sgl, sg, sg_len, i) {
 621                 ret = d40_size_2_dmalen(sg_dma_len(sg),
 622                                         data_width1, data_width2);
 623                 if (ret < 0)
 624                         return ret;
 625                 len += ret;
 626         }
 627         return len;
 628 }
 629
 630 /* Support functions for logical channels */
 631
 632 static int d40_channel_execute_command(struct d40_chan *d40c,
 633                                        enum d40_command command)
 634 {
 635         u32 status;
 636         int i;
 637         void __iomem *active_reg;
 638         int ret = 0;
 639         unsigned long flags;
 640         u32 wmask;
 641
 642         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
 643
 644         if (d40c->phy_chan->num % 2 == 0)
 645                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
 646         else
 647                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
 648
 649         if (command == D40_DMA_SUSPEND_REQ) {
 650                 status = (readl(active_reg) &
 651                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
 652                         D40_CHAN_POS(d40c->phy_chan->num);
 653
 654                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
 655                         goto done;
 656         }
 657
 658         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
 659         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
 660                active_reg);
 661
 662         if (command == D40_DMA_SUSPEND_REQ) {
 663
 664                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
 665                         status = (readl(active_reg) &
 666                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
 667                                 D40_CHAN_POS(d40c->phy_chan->num);
 668
 669                         cpu_relax();
 670                         /*
 671                          * Reduce the number of bus accesses while
 672                          * waiting for the DMA to suspend.
 673                          */
 674                         udelay(3);
 675
 676                         if (status == D40_DMA_STOP ||
 677                             status == D40_DMA_SUSPENDED)
 678                                 break;
 679                 }
 680
 681                 if (i == D40_SUSPEND_MAX_IT) {
 682                         chan_err(d40c,
 683                                 "unable to suspend the chl %d (log: %d) status %x\n",
 684                                 d40c->phy_chan->num, d40c->log_num,
 685                                 status);
 686                         dump_stack();
 687                         ret = -EBUSY;
 688                 }
 689
 690         }
 691 done:
 692         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
 693         return ret;
 694 }
 695
 696 static void d40_term_all(struct d40_chan *d40c)
 697 {
 698         struct d40_desc *d40d;
 699
 700         /* Release active descriptors */
 701         while ((d40d = d40_first_active_get(d40c))) {
 702                 d40_desc_remove(d40d);
 703                 d40_desc_free(d40c, d40d);
 704         }
 705
 706         /* Release queued descriptors waiting for transfer */
 707         while ((d40d = d40_first_queued(d40c))) {
 708                 d40_desc_remove(d40d);
 709                 d40_desc_free(d40c, d40d);
 710         }
 711
 712
 713         d40c->pending_tx = 0;
 714         d40c->busy = false;
 715 }
 716
 717 static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
 718                                    u32 event, int reg)
 719 {
 720         void __iomem *addr = chan_base(d40c) + reg;
 721         int tries;
 722
 723         if (!enable) {
 724                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
 725                        | ~D40_EVENTLINE_MASK(event), addr);
 726                 return;
 727         }
 728
 729         /*
 730          * The hardware sometimes doesn't register the enable when src and dst
 731          * event lines are active on the same logical channel.  Retry to ensure
 732          * it does.  Usually only one retry is sufficient.
 733          */
 734         tries = 100;
 735         while (--tries) {
 736                 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
 737                        | ~D40_EVENTLINE_MASK(event), addr);
 738
 739                 if (readl(addr) & D40_EVENTLINE_MASK(event))
 740                         break;
 741         }
 742
 743         if (tries != 99)
 744                 dev_dbg(chan2dev(d40c),
 745                         "[%s] workaround enable S%cLNK (%d tries)\n",
 746                         __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
 747                         100 - tries);
 748
 749         WARN_ON(!tries);
 750 }
 751
 752 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
 753 {
 754         unsigned long flags;
 755
 756         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
 757
 758         /* Enable event line connected to device (or memcpy) */
 759         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
 760             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
 761                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 762
 763                 __d40_config_set_event(d40c, do_enable, event,
 764                                        D40_CHAN_REG_SSLNK);
 765         }
 766
 767         if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
 768                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 769
 770                 __d40_config_set_event(d40c, do_enable, event,
 771                                        D40_CHAN_REG_SDLNK);
 772         }
 773
 774         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
 775 }
 776
 777 static u32 d40_chan_has_events(struct d40_chan *d40c)
 778 {
 779         void __iomem *chanbase = chan_base(d40c);
 780         u32 val;
 781
 782         val = readl(chanbase + D40_CHAN_REG_SSLNK);
 783         val |= readl(chanbase + D40_CHAN_REG_SDLNK);
 784
 785         return val;
 786 }
 787
 788 static u32 d40_get_prmo(struct d40_chan *d40c)
 789 {
 790         static const unsigned int phy_map[] = {
 791                 [STEDMA40_PCHAN_BASIC_MODE]
 792                         = D40_DREG_PRMO_PCHAN_BASIC,
 793                 [STEDMA40_PCHAN_MODULO_MODE]
 794                         = D40_DREG_PRMO_PCHAN_MODULO,
 795                 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
 796                         = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
 797         };
 798         static const unsigned int log_map[] = {
 799                 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
 800                         = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
 801                 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
 802                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
 803                 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
 804                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
 805         };
 806
 807         if (chan_is_physical(d40c))
 808                 return phy_map[d40c->dma_cfg.mode_opt];
 809         else
 810                 return log_map[d40c->dma_cfg.mode_opt];
 811 }
 812
 813 static void d40_config_write(struct d40_chan *d40c)
 814 {
 815         u32 addr_base;
 816         u32 var;
 817
 818         /* Odd addresses are even addresses + 4 */
 819         addr_base = (d40c->phy_chan->num % 2) * 4;
 820         /* Setup channel mode to logical or physical */
 821         var = ((u32)(chan_is_logical(d40c)) + 1) <<
 822                 D40_CHAN_POS(d40c->phy_chan->num);
 823         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
 824
 825         /* Setup operational mode option register */
 826         var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
 827
 828         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
 829
 830         if (chan_is_logical(d40c)) {
 831                 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
 832                            & D40_SREG_ELEM_LOG_LIDX_MASK;
 833                 void __iomem *chanbase = chan_base(d40c);
 834
 835                 /* Set default config for CFG reg */
 836                 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
 837                 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
 838
 839                 /* Set LIDX for lcla */
 840                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
 841                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
 842         }
 843 }
 844
 845 static u32 d40_residue(struct d40_chan *d40c)
 846 {
 847         u32 num_elt;
 848
 849         if (chan_is_logical(d40c))
 850                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
 851                         >> D40_MEM_LCSP2_ECNT_POS;
 852         else {
 853                 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
 854                 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
 855                           >> D40_SREG_ELEM_PHY_ECNT_POS;
 856         }
 857
 858         return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
 859 }
 860
 861 static bool d40_tx_is_linked(struct d40_chan *d40c)
 862 {
 863         bool is_link;
 864
 865         if (chan_is_logical(d40c))
 866                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
 867         else
 868                 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
 869                           & D40_SREG_LNK_PHYS_LNK_MASK;
 870
 871         return is_link;
 872 }
 873
 874 static int d40_pause(struct dma_chan *chan)
 875 {
 876         struct d40_chan *d40c =
 877                 container_of(chan, struct d40_chan, chan);
 878         int res = 0;
 879         unsigned long flags;
 880
 881         if (!d40c->busy)
 882                 return 0;
 883
 884         spin_lock_irqsave(&d40c->lock, flags);
 885
 886         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
 887         if (res == 0) {
 888                 if (chan_is_logical(d40c)) {
 889                         d40_config_set_event(d40c, false);
 890                         /* Resume the other logical channels if any */
 891                         if (d40_chan_has_events(d40c))
 892                                 res = d40_channel_execute_command(d40c,
 893                                                                   D40_DMA_RUN);
 894                 }
 895         }
 896
 897         spin_unlock_irqrestore(&d40c->lock, flags);
 898         return res;
 899 }
 900
 901 static int d40_resume(struct dma_chan *chan)
 902 {
 903         struct d40_chan *d40c =
 904                 container_of(chan, struct d40_chan, chan);
 905         int res = 0;
 906         unsigned long flags;
 907
 908         if (!d40c->busy)
 909                 return 0;
 910
 911         spin_lock_irqsave(&d40c->lock, flags);
 912
 913         if (d40c->base->rev == 0)
 914                 if (chan_is_logical(d40c)) {
 915                         res = d40_channel_execute_command(d40c,
 916                                                           D40_DMA_SUSPEND_REQ);
 917                         goto no_suspend;
 918                 }
 919
 920         /* If bytes left to transfer or linked tx resume job */
 921         if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
 922
 923                 if (chan_is_logical(d40c))
 924                         d40_config_set_event(d40c, true);
 925
 926                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
 927         }
 928
 929 no_suspend:
 930         spin_unlock_irqrestore(&d40c->lock, flags);
 931         return res;
 932 }
 933
 934 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 935 {
 936         struct d40_chan *d40c = container_of(tx->chan,
 937                                              struct d40_chan,
 938                                              chan);
 939         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
 940         unsigned long flags;
 941
 942         spin_lock_irqsave(&d40c->lock, flags);
 943
 944         d40c->chan.cookie++;
 945
 946         if (d40c->chan.cookie < 0)
 947                 d40c->chan.cookie = 1;
 948
 949         d40d->txd.cookie = d40c->chan.cookie;
 950
 951         d40_desc_queue(d40c, d40d);
 952
 953         spin_unlock_irqrestore(&d40c->lock, flags);
 954
 955         return tx->cookie;
 956 }
 957
 958 static int d40_start(struct d40_chan *d40c)
 959 {
 960         if (d40c->base->rev == 0) {
 961                 int err;
 962
 963                 if (chan_is_logical(d40c)) {
 964                         err = d40_channel_execute_command(d40c,
 965                                                           D40_DMA_SUSPEND_REQ);
 966                         if (err)
 967                                 return err;
 968                 }
 969         }
 970
 971         if (chan_is_logical(d40c))
 972                 d40_config_set_event(d40c, true);
 973
 974         return d40_channel_execute_command(d40c, D40_DMA_RUN);
 975 }
 976
 977 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
 978 {
 979         struct d40_desc *d40d;
 980         int err;
 981
 982         /* Start queued jobs, if any */
 983         d40d = d40_first_queued(d40c);
 984
 985         if (d40d != NULL) {
 986                 d40c->busy = true;
 987
 988                 /* Remove from queue */
 989                 d40_desc_remove(d40d);
 990
 991                 /* Add to active queue */
 992                 d40_desc_submit(d40c, d40d);
 993
 994                 /* Initiate DMA job */
 995                 d40_desc_load(d40c, d40d);
 996
 997                 /* Start dma job */
 998                 err = d40_start(d40c);
 999
1000                 if (err)
1001                         return NULL;
1002         }
1003
1004         return d40d;
1005 }
1006
1007 /* called from interrupt context */
1008 static void dma_tc_handle(struct d40_chan *d40c)
1009 {
1010         struct d40_desc *d40d;
1011
1012         /* Get first active entry from list */
1013         d40d = d40_first_active_get(d40c);
1014
1015         if (d40d == NULL)
1016                 return;
1017
1018         d40_lcla_free_all(d40c, d40d);
1019
1020         if (d40d->lli_current < d40d->lli_len) {
1021                 d40_desc_load(d40c, d40d);
1022                 /* Start dma job */
1023                 (void) d40_start(d40c);
1024                 return;
1025         }
1026
1027         if (d40_queue_start(d40c) == NULL)
1028                 d40c->busy = false;
1029
1030         d40c->pending_tx++;
1031         tasklet_schedule(&d40c->tasklet);
1032
1033 }
1034
1035 static void dma_tasklet(unsigned long data)
1036 {
1037         struct d40_chan *d40c = (struct d40_chan *) data;
1038         struct d40_desc *d40d;
1039         unsigned long flags;
1040         dma_async_tx_callback callback;
1041         void *callback_param;
1042
1043         spin_lock_irqsave(&d40c->lock, flags);
1044
1045         /* Get first active entry from list */
1046         d40d = d40_first_active_get(d40c);
1047
1048         if (d40d == NULL)
1049                 goto err;
1050
1051         d40c->completed = d40d->txd.cookie;
1052
1053         /*
1054          * If terminating a channel pending_tx is set to zero.
1055          * This prevents any finished active jobs to return to the client.
1056          */
1057         if (d40c->pending_tx == 0) {
1058                 spin_unlock_irqrestore(&d40c->lock, flags);
1059                 return;
1060         }
1061
1062         /* Callback to client */
1063         callback = d40d->txd.callback;
1064         callback_param = d40d->txd.callback_param;
1065
1066         if (async_tx_test_ack(&d40d->txd)) {
1067                 d40_pool_lli_free(d40d);
1068                 d40_desc_remove(d40d);
1069                 d40_desc_free(d40c, d40d);
1070         } else {
1071                 if (!d40d->is_in_client_list) {
1072                         d40_desc_remove(d40d);
1073                         d40_lcla_free_all(d40c, d40d);
1074                         list_add_tail(&d40d->node, &d40c->client);
1075                         d40d->is_in_client_list = true;
1076                 }
1077         }
1078
1079         d40c->pending_tx--;
1080
1081         if (d40c->pending_tx)
1082                 tasklet_schedule(&d40c->tasklet);
1083
1084         spin_unlock_irqrestore(&d40c->lock, flags);
1085
1086         if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
1087                 callback(callback_param);
1088
1089         return;
1090
1091  err:
1092         /* Rescue manouver if receiving double interrupts */
1093         if (d40c->pending_tx > 0)
1094                 d40c->pending_tx--;
1095         spin_unlock_irqrestore(&d40c->lock, flags);
1096 }
1097
1098 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1099 {
1100         static const struct d40_interrupt_lookup il[] = {
1101                 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
1102                 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1103                 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1104                 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1105                 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
1106                 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
1107                 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
1108                 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
1109                 {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
1110                 {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
1111         };
1112
1113         int i;
1114         u32 regs[ARRAY_SIZE(il)];
1115         u32 idx;
1116         u32 row;
1117         long chan = -1;
1118         struct d40_chan *d40c;
1119         unsigned long flags;
1120         struct d40_base *base = data;
1121
1122         spin_lock_irqsave(&base->interrupt_lock, flags);
1123
1124         /* Read interrupt status of both logical and physical channels */
1125         for (i = 0; i < ARRAY_SIZE(il); i++)
1126                 regs[i] = readl(base->virtbase + il[i].src);
1127
1128         for (;;) {
1129
1130                 chan = find_next_bit((unsigned long *)regs,
1131                                      BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1132
1133                 /* No more set bits found? */
1134                 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1135                         break;
1136
1137                 row = chan / BITS_PER_LONG;
1138                 idx = chan & (BITS_PER_LONG - 1);
1139
1140                 /* ACK interrupt */
1141                 writel(1 << idx, base->virtbase + il[row].clr);
1142
1143                 if (il[row].offset == D40_PHY_CHAN)
1144                         d40c = base->lookup_phy_chans[idx];
1145                 else
1146                         d40c = base->lookup_log_chans[il[row].offset + idx];
1147                 spin_lock(&d40c->lock);
1148
1149                 if (!il[row].is_error)
1150                         dma_tc_handle(d40c);
1151                 else
1152                         d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1153                                 chan, il[row].offset, idx);
1154
1155                 spin_unlock(&d40c->lock);
1156         }
1157
1158         spin_unlock_irqrestore(&base->interrupt_lock, flags);
1159
1160         return IRQ_HANDLED;
1161 }
1162
1163 static int d40_validate_conf(struct d40_chan *d40c,
1164                              struct stedma40_chan_cfg *conf)
1165 {
1166         int res = 0;
1167         u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1168         u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1169         bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1170
1171         if (!conf->dir) {
1172                 chan_err(d40c, "Invalid direction.\n");
1173                 res = -EINVAL;
1174         }
1175
1176         if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1177             d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1178             d40c->runtime_addr == 0) {
1179
1180                 chan_err(d40c, "Invalid TX channel address (%d)\n",
1181                          conf->dst_dev_type);
1182                 res = -EINVAL;
1183         }
1184
1185         if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1186             d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1187             d40c->runtime_addr == 0) {
1188                 chan_err(d40c, "Invalid RX channel address (%d)\n",
1189                         conf->src_dev_type);
1190                 res = -EINVAL;
1191         }
1192
1193         if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1194             dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1195                 chan_err(d40c, "Invalid dst\n");
1196                 res = -EINVAL;
1197         }
1198
1199         if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1200             src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1201                 chan_err(d40c, "Invalid src\n");
1202                 res = -EINVAL;
1203         }
1204
1205         if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1206             dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1207                 chan_err(d40c, "No event line\n");
1208                 res = -EINVAL;
1209         }
1210
1211         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1212             (src_event_group != dst_event_group)) {
1213                 chan_err(d40c, "Invalid event group\n");
1214                 res = -EINVAL;
1215         }
1216
1217         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1218                 /*
1219                  * DMAC HW supports it. Will be added to this driver,
1220                  * in case any dma client requires it.
1221                  */
1222                 chan_err(d40c, "periph to periph not supported\n");
1223                 res = -EINVAL;
1224         }
1225
1226         if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1227             (1 << conf->src_info.data_width) !=
1228             d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1229             (1 << conf->dst_info.data_width)) {
1230                 /*
1231                  * The DMAC hardware only supports
1232                  * src (burst x width) == dst (burst x width)
1233                  */
1234
1235                 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1236                 res = -EINVAL;
1237         }
1238
1239         return res;
1240 }
1241
1242 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1243                                int log_event_line, bool is_log)
1244 {
1245         unsigned long flags;
1246         spin_lock_irqsave(&phy->lock, flags);
1247         if (!is_log) {
1248                 /* Physical interrupts are masked per physical full channel */
1249                 if (phy->allocated_src == D40_ALLOC_FREE &&
1250                     phy->allocated_dst == D40_ALLOC_FREE) {
1251                         phy->allocated_dst = D40_ALLOC_PHY;
1252                         phy->allocated_src = D40_ALLOC_PHY;
1253                         goto found;
1254                 } else
1255                         goto not_found;
1256         }
1257
1258         /* Logical channel */
1259         if (is_src) {
1260                 if (phy->allocated_src == D40_ALLOC_PHY)
1261                         goto not_found;
1262
1263                 if (phy->allocated_src == D40_ALLOC_FREE)
1264                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1265
1266                 if (!(phy->allocated_src & (1 << log_event_line))) {
1267                         phy->allocated_src |= 1 << log_event_line;
1268                         goto found;
1269                 } else
1270                         goto not_found;
1271         } else {
1272                 if (phy->allocated_dst == D40_ALLOC_PHY)
1273                         goto not_found;
1274
1275                 if (phy->allocated_dst == D40_ALLOC_FREE)
1276                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1277
1278                 if (!(phy->allocated_dst & (1 << log_event_line))) {
1279                         phy->allocated_dst |= 1 << log_event_line;
1280                         goto found;
1281                 } else
1282                         goto not_found;
1283         }
1284
1285 not_found:
1286         spin_unlock_irqrestore(&phy->lock, flags);
1287         return false;
1288 found:
1289         spin_unlock_irqrestore(&phy->lock, flags);
1290         return true;
1291 }
1292
1293 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1294                                int log_event_line)
1295 {
1296         unsigned long flags;
1297         bool is_free = false;
1298
1299         spin_lock_irqsave(&phy->lock, flags);
1300         if (!log_event_line) {
1301                 phy->allocated_dst = D40_ALLOC_FREE;
1302                 phy->allocated_src = D40_ALLOC_FREE;
1303                 is_free = true;
1304                 goto out;
1305         }
1306
1307         /* Logical channel */
1308         if (is_src) {
1309                 phy->allocated_src &= ~(1 << log_event_line);
1310                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1311                         phy->allocated_src = D40_ALLOC_FREE;
1312         } else {
1313                 phy->allocated_dst &= ~(1 << log_event_line);
1314                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1315                         phy->allocated_dst = D40_ALLOC_FREE;
1316         }
1317
1318         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1319                    D40_ALLOC_FREE);
1320
1321 out:
1322         spin_unlock_irqrestore(&phy->lock, flags);
1323
1324         return is_free;
1325 }
1326
1327 static int d40_allocate_channel(struct d40_chan *d40c)
1328 {
1329         int dev_type;
1330         int event_group;
1331         int event_line;
1332         struct d40_phy_res *phys;
1333         int i;
1334         int j;
1335         int log_num;
1336         bool is_src;
1337         bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1338
1339         phys = d40c->base->phy_res;
1340
1341         if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1342                 dev_type = d40c->dma_cfg.src_dev_type;
1343                 log_num = 2 * dev_type;
1344                 is_src = true;
1345         } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1346                    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1347                 /* dst event lines are used for logical memcpy */
1348                 dev_type = d40c->dma_cfg.dst_dev_type;
1349                 log_num = 2 * dev_type + 1;
1350                 is_src = false;
1351         } else
1352                 return -EINVAL;
1353
1354         event_group = D40_TYPE_TO_GROUP(dev_type);
1355         event_line = D40_TYPE_TO_EVENT(dev_type);
1356
1357         if (!is_log) {
1358                 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1359                         /* Find physical half channel */
1360                         for (i = 0; i < d40c->base->num_phy_chans; i++) {
1361
1362                                 if (d40_alloc_mask_set(&phys[i], is_src,
1363                                                        0, is_log))
1364                                         goto found_phy;
1365                         }
1366                 } else
1367                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1368                                 int phy_num = j  + event_group * 2;
1369                                 for (i = phy_num; i < phy_num + 2; i++) {
1370                                         if (d40_alloc_mask_set(&phys[i],
1371                                                                is_src,
1372                                                                0,
1373                                                                is_log))
1374                                                 goto found_phy;
1375                                 }
1376                         }
1377                 return -EINVAL;
1378 found_phy:
1379                 d40c->phy_chan = &phys[i];
1380                 d40c->log_num = D40_PHY_CHAN;
1381                 goto out;
1382         }
1383         if (dev_type == -1)
1384                 return -EINVAL;
1385
1386         /* Find logical channel */
1387         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1388                 int phy_num = j + event_group * 2;
1389                 /*
1390                  * Spread logical channels across all available physical rather
1391                  * than pack every logical channel at the first available phy
1392                  * channels.
1393                  */
1394                 if (is_src) {
1395                         for (i = phy_num; i < phy_num + 2; i++) {
1396                                 if (d40_alloc_mask_set(&phys[i], is_src,
1397                                                        event_line, is_log))
1398                                         goto found_log;
1399                         }
1400                 } else {
1401                         for (i = phy_num + 1; i >= phy_num; i--) {
1402                                 if (d40_alloc_mask_set(&phys[i], is_src,
1403                                                        event_line, is_log))
1404                                         goto found_log;
1405                         }
1406                 }
1407         }
1408         return -EINVAL;
1409
1410 found_log:
1411         d40c->phy_chan = &phys[i];
1412         d40c->log_num = log_num;
1413 out:
1414
1415         if (is_log)
1416                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1417         else
1418                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1419
1420         return 0;
1421
1422 }
1423
1424 static int d40_config_memcpy(struct d40_chan *d40c)
1425 {
1426         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1427
1428         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1429                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1430                 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1431                 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1432                         memcpy[d40c->chan.chan_id];
1433
1434         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1435                    dma_has_cap(DMA_SLAVE, cap)) {
1436                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1437         } else {
1438                 chan_err(d40c, "No memcpy\n");
1439                 return -EINVAL;
1440         }
1441
1442         return 0;
1443 }
1444
1445
1446 static int d40_free_dma(struct d40_chan *d40c)
1447 {
1448
1449         int res = 0;
1450         u32 event;
1451         struct d40_phy_res *phy = d40c->phy_chan;
1452         bool is_src;
1453         struct d40_desc *d;
1454         struct d40_desc *_d;
1455
1456
1457         /* Terminate all queued and active transfers */
1458         d40_term_all(d40c);
1459
1460         /* Release client owned descriptors */
1461         if (!list_empty(&d40c->client))
1462                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1463                         d40_pool_lli_free(d);
1464                         d40_desc_remove(d);
1465                         d40_desc_free(d40c, d);
1466                 }
1467
1468         if (phy == NULL) {
1469                 chan_err(d40c, "phy == null\n");
1470                 return -EINVAL;
1471         }
1472
1473         if (phy->allocated_src == D40_ALLOC_FREE &&
1474             phy->allocated_dst == D40_ALLOC_FREE) {
1475                 chan_err(d40c, "channel already free\n");
1476                 return -EINVAL;
1477         }
1478
1479         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1480             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1481                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1482                 is_src = false;
1483         } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1484                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1485                 is_src = true;
1486         } else {
1487                 chan_err(d40c, "Unknown direction\n");
1488                 return -EINVAL;
1489         }
1490
1491         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1492         if (res) {
1493                 chan_err(d40c, "suspend failed\n");
1494                 return res;
1495         }
1496
1497         if (chan_is_logical(d40c)) {
1498                 /* Release logical channel, deactivate the event line */
1499
1500                 d40_config_set_event(d40c, false);
1501                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1502
1503                 /*
1504                  * Check if there are more logical allocation
1505                  * on this phy channel.
1506                  */
1507                 if (!d40_alloc_mask_free(phy, is_src, event)) {
1508                         /* Resume the other logical channels if any */
1509                         if (d40_chan_has_events(d40c)) {
1510                                 res = d40_channel_execute_command(d40c,
1511                                                                   D40_DMA_RUN);
1512                                 if (res) {
1513                                         chan_err(d40c,
1514                                                 "Executing RUN command\n");
1515                                         return res;
1516                                 }
1517                         }
1518                         return 0;
1519                 }
1520         } else {
1521                 (void) d40_alloc_mask_free(phy, is_src, 0);
1522         }
1523
1524         /* Release physical channel */
1525         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1526         if (res) {
1527                 chan_err(d40c, "Failed to stop channel\n");
1528                 return res;
1529         }
1530         d40c->phy_chan = NULL;
1531         d40c->configured = false;
1532         d40c->base->lookup_phy_chans[phy->num] = NULL;
1533
1534         return 0;
1535 }
1536
1537 static bool d40_is_paused(struct d40_chan *d40c)
1538 {
1539         void __iomem *chanbase = chan_base(d40c);
1540         bool is_paused = false;
1541         unsigned long flags;
1542         void __iomem *active_reg;
1543         u32 status;
1544         u32 event;
1545
1546         spin_lock_irqsave(&d40c->lock, flags);
1547
1548         if (chan_is_physical(d40c)) {
1549                 if (d40c->phy_chan->num % 2 == 0)
1550                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1551                 else
1552                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1553
1554                 status = (readl(active_reg) &
1555                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1556                         D40_CHAN_POS(d40c->phy_chan->num);
1557                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1558                         is_paused = true;
1559
1560                 goto _exit;
1561         }
1562
1563         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1564             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1565                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1566                 status = readl(chanbase + D40_CHAN_REG_SDLNK);
1567         } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1568                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1569                 status = readl(chanbase + D40_CHAN_REG_SSLNK);
1570         } else {
1571                 chan_err(d40c, "Unknown direction\n");
1572                 goto _exit;
1573         }
1574
1575         status = (status & D40_EVENTLINE_MASK(event)) >>
1576                 D40_EVENTLINE_POS(event);
1577
1578         if (status != D40_DMA_RUN)
1579                 is_paused = true;
1580 _exit:
1581         spin_unlock_irqrestore(&d40c->lock, flags);
1582         return is_paused;
1583
1584 }
1585
1586
1587 static u32 stedma40_residue(struct dma_chan *chan)
1588 {
1589         struct d40_chan *d40c =
1590                 container_of(chan, struct d40_chan, chan);
1591         u32 bytes_left;
1592         unsigned long flags;
1593
1594         spin_lock_irqsave(&d40c->lock, flags);
1595         bytes_left = d40_residue(d40c);
1596         spin_unlock_irqrestore(&d40c->lock, flags);
1597
1598         return bytes_left;
1599 }
1600
1601 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1602                                                    struct scatterlist *sgl_dst,
1603                                                    struct scatterlist *sgl_src,
1604                                                    unsigned int sgl_len,
1605                                                    unsigned long dma_flags)
1606 {
1607         int res;
1608         struct d40_desc *d40d;
1609         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1610                                              chan);
1611         unsigned long flags;
1612
1613         if (d40c->phy_chan == NULL) {
1614                 chan_err(d40c, "Unallocated channel.\n");
1615                 return ERR_PTR(-EINVAL);
1616         }
1617
1618         spin_lock_irqsave(&d40c->lock, flags);
1619         d40d = d40_desc_get(d40c);
1620
1621         if (d40d == NULL)
1622                 goto err;
1623
1624         d40d->lli_len = d40_sg_2_dmalen(sgl_dst, sgl_len,
1625                                         d40c->dma_cfg.src_info.data_width,
1626                                         d40c->dma_cfg.dst_info.data_width);
1627         if (d40d->lli_len < 0) {
1628                 chan_err(d40c, "Unaligned size\n");
1629                 goto err;
1630         }
1631
1632         d40d->lli_current = 0;
1633         d40d->txd.flags = dma_flags;
1634
1635         if (chan_is_logical(d40c)) {
1636
1637                 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1638                         chan_err(d40c, "Out of memory\n");
1639                         goto err;
1640                 }
1641
1642                 (void) d40_log_sg_to_lli(sgl_src,
1643                                          sgl_len,
1644                                          d40d->lli_log.src,
1645                                          d40c->log_def.lcsp1,
1646                                          d40c->dma_cfg.src_info.data_width,
1647                                          d40c->dma_cfg.dst_info.data_width);
1648
1649                 (void) d40_log_sg_to_lli(sgl_dst,
1650                                          sgl_len,
1651                                          d40d->lli_log.dst,
1652                                          d40c->log_def.lcsp3,
1653                                          d40c->dma_cfg.dst_info.data_width,
1654                                          d40c->dma_cfg.src_info.data_width);
1655         } else {
1656                 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
1657                         chan_err(d40c, "Out of memory\n");
1658                         goto err;
1659                 }
1660
1661                 res = d40_phy_sg_to_lli(sgl_src,
1662                                         sgl_len,
1663                                         0,
1664                                         d40d->lli_phy.src,
1665                                         virt_to_phys(d40d->lli_phy.src),
1666                                         d40c->src_def_cfg,
1667                                         d40c->dma_cfg.src_info.data_width,
1668                                         d40c->dma_cfg.dst_info.data_width,
1669                                         d40c->dma_cfg.src_info.psize);
1670
1671                 if (res < 0)
1672                         goto err;
1673
1674                 res = d40_phy_sg_to_lli(sgl_dst,
1675                                         sgl_len,
1676                                         0,
1677                                         d40d->lli_phy.dst,
1678                                         virt_to_phys(d40d->lli_phy.dst),
1679                                         d40c->dst_def_cfg,
1680                                         d40c->dma_cfg.dst_info.data_width,
1681                                         d40c->dma_cfg.src_info.data_width,
1682                                         d40c->dma_cfg.dst_info.psize);
1683
1684                 if (res < 0)
1685                         goto err;
1686
1687                 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1688                                       d40d->lli_pool.size, DMA_TO_DEVICE);
1689         }
1690
1691         dma_async_tx_descriptor_init(&d40d->txd, chan);
1692
1693         d40d->txd.tx_submit = d40_tx_submit;
1694
1695         spin_unlock_irqrestore(&d40c->lock, flags);
1696
1697         return &d40d->txd;
1698 err:
1699         if (d40d)
1700                 d40_desc_free(d40c, d40d);
1701         spin_unlock_irqrestore(&d40c->lock, flags);
1702         return NULL;
1703 }
1704 EXPORT_SYMBOL(stedma40_memcpy_sg);
1705
1706 bool stedma40_filter(struct dma_chan *chan, void *data)
1707 {
1708         struct stedma40_chan_cfg *info = data;
1709         struct d40_chan *d40c =
1710                 container_of(chan, struct d40_chan, chan);
1711         int err;
1712
1713         if (data) {
1714                 err = d40_validate_conf(d40c, info);
1715                 if (!err)
1716                         d40c->dma_cfg = *info;
1717         } else
1718                 err = d40_config_memcpy(d40c);
1719
1720         if (!err)
1721                 d40c->configured = true;
1722
1723         return err == 0;
1724 }
1725 EXPORT_SYMBOL(stedma40_filter);
1726
1727 /* DMA ENGINE functions */
1728 static int d40_alloc_chan_resources(struct dma_chan *chan)
1729 {
1730         int err;
1731         unsigned long flags;
1732         struct d40_chan *d40c =
1733                 container_of(chan, struct d40_chan, chan);
1734         bool is_free_phy;
1735         spin_lock_irqsave(&d40c->lock, flags);
1736
1737         d40c->completed = chan->cookie = 1;
1738
1739         /* If no dma configuration is set use default configuration (memcpy) */
1740         if (!d40c->configured) {
1741                 err = d40_config_memcpy(d40c);
1742                 if (err) {
1743                         chan_err(d40c, "Failed to configure memcpy channel\n");
1744                         goto fail;
1745                 }
1746         }
1747         is_free_phy = (d40c->phy_chan == NULL);
1748
1749         err = d40_allocate_channel(d40c);
1750         if (err) {
1751                 chan_err(d40c, "Failed to allocate channel\n");
1752                 goto fail;
1753         }
1754
1755         /* Fill in basic CFG register values */
1756         d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1757                     &d40c->dst_def_cfg, chan_is_logical(d40c));
1758
1759         if (chan_is_logical(d40c)) {
1760                 d40_log_cfg(&d40c->dma_cfg,
1761                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1762
1763                 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1764                         d40c->lcpa = d40c->base->lcpa_base +
1765                           d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1766                 else
1767                         d40c->lcpa = d40c->base->lcpa_base +
1768                           d40c->dma_cfg.dst_dev_type *
1769                           D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1770         }
1771
1772         /*
1773          * Only write channel configuration to the DMA if the physical
1774          * resource is free. In case of multiple logical channels
1775          * on the same physical resource, only the first write is necessary.
1776          */
1777         if (is_free_phy)
1778                 d40_config_write(d40c);
1779 fail:
1780         spin_unlock_irqrestore(&d40c->lock, flags);
1781         return err;
1782 }
1783
1784 static void d40_free_chan_resources(struct dma_chan *chan)
1785 {
1786         struct d40_chan *d40c =
1787                 container_of(chan, struct d40_chan, chan);
1788         int err;
1789         unsigned long flags;
1790
1791         if (d40c->phy_chan == NULL) {
1792                 chan_err(d40c, "Cannot free unallocated channel\n");
1793                 return;
1794         }
1795
1796
1797         spin_lock_irqsave(&d40c->lock, flags);
1798
1799         err = d40_free_dma(d40c);
1800
1801         if (err)
1802                 chan_err(d40c, "Failed to free channel\n");
1803         spin_unlock_irqrestore(&d40c->lock, flags);
1804 }
1805
1806 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1807                                                        dma_addr_t dst,
1808                                                        dma_addr_t src,
1809                                                        size_t size,
1810                                                        unsigned long dma_flags)
1811 {
1812         struct d40_desc *d40d;
1813         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1814                                              chan);
1815         unsigned long flags;
1816
1817         if (d40c->phy_chan == NULL) {
1818                 chan_err(d40c, "Channel is not allocated.\n");
1819                 return ERR_PTR(-EINVAL);
1820         }
1821
1822         spin_lock_irqsave(&d40c->lock, flags);
1823         d40d = d40_desc_get(d40c);
1824
1825         if (d40d == NULL) {
1826                 chan_err(d40c, "Descriptor is NULL\n");
1827                 goto err;
1828         }
1829
1830         d40d->txd.flags = dma_flags;
1831         d40d->lli_len = d40_size_2_dmalen(size,
1832                                           d40c->dma_cfg.src_info.data_width,
1833                                           d40c->dma_cfg.dst_info.data_width);
1834         if (d40d->lli_len < 0) {
1835                 chan_err(d40c, "Unaligned size\n");
1836                 goto err;
1837         }
1838
1839
1840         dma_async_tx_descriptor_init(&d40d->txd, chan);
1841
1842         d40d->txd.tx_submit = d40_tx_submit;
1843
1844         if (chan_is_logical(d40c)) {
1845
1846                 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1847                         chan_err(d40c, "Out of memory\n");
1848                         goto err;
1849                 }
1850                 d40d->lli_current = 0;
1851
1852                 if (d40_log_buf_to_lli(d40d->lli_log.src,
1853                                        src,
1854                                        size,
1855                                        d40c->log_def.lcsp1,
1856                                        d40c->dma_cfg.src_info.data_width,
1857                                        d40c->dma_cfg.dst_info.data_width,
1858                                        true) == NULL)
1859                         goto err;
1860
1861                 if (d40_log_buf_to_lli(d40d->lli_log.dst,
1862                                        dst,
1863                                        size,
1864                                        d40c->log_def.lcsp3,
1865                                        d40c->dma_cfg.dst_info.data_width,
1866                                        d40c->dma_cfg.src_info.data_width,
1867                                        true) == NULL)
1868                         goto err;
1869
1870         } else {
1871
1872                 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
1873                         chan_err(d40c, "Out of memory\n");
1874                         goto err;
1875                 }
1876
1877                 if (d40_phy_buf_to_lli(d40d->lli_phy.src,
1878                                        src,
1879                                        size,
1880                                        d40c->dma_cfg.src_info.psize,
1881                                        0,
1882                                        d40c->src_def_cfg,
1883                                        true,
1884                                        d40c->dma_cfg.src_info.data_width,
1885                                        d40c->dma_cfg.dst_info.data_width,
1886                                        false) == NULL)
1887                         goto err;
1888
1889                 if (d40_phy_buf_to_lli(d40d->lli_phy.dst,
1890                                        dst,
1891                                        size,
1892                                        d40c->dma_cfg.dst_info.psize,
1893                                        0,
1894                                        d40c->dst_def_cfg,
1895                                        true,
1896                                        d40c->dma_cfg.dst_info.data_width,
1897                                        d40c->dma_cfg.src_info.data_width,
1898                                        false) == NULL)
1899                         goto err;
1900
1901                 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1902                                       d40d->lli_pool.size, DMA_TO_DEVICE);
1903         }
1904
1905         spin_unlock_irqrestore(&d40c->lock, flags);
1906         return &d40d->txd;
1907
1908 err:
1909         if (d40d)
1910                 d40_desc_free(d40c, d40d);
1911         spin_unlock_irqrestore(&d40c->lock, flags);
1912         return NULL;
1913 }
1914
1915 static struct dma_async_tx_descriptor *
1916 d40_prep_sg(struct dma_chan *chan,
1917             struct scatterlist *dst_sg, unsigned int dst_nents,
1918             struct scatterlist *src_sg, unsigned int src_nents,
1919             unsigned long dma_flags)
1920 {
1921         if (dst_nents != src_nents)
1922                 return NULL;
1923
1924         return stedma40_memcpy_sg(chan, dst_sg, src_sg, dst_nents, dma_flags);
1925 }
1926
1927 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1928                                  struct d40_chan *d40c,
1929                                  struct scatterlist *sgl,
1930                                  unsigned int sg_len,
1931                                  enum dma_data_direction direction,
1932                                  unsigned long dma_flags)
1933 {
1934         dma_addr_t dev_addr = 0;
1935         int total_size;
1936
1937         d40d->lli_len = d40_sg_2_dmalen(sgl, sg_len,
1938                                         d40c->dma_cfg.src_info.data_width,
1939                                         d40c->dma_cfg.dst_info.data_width);
1940         if (d40d->lli_len < 0) {
1941                 chan_err(d40c, "Unaligned size\n");
1942                 return -EINVAL;
1943         }
1944
1945         if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1946                 chan_err(d40c, "Out of memory\n");
1947                 return -ENOMEM;
1948         }
1949
1950         d40d->lli_current = 0;
1951
1952         if (direction == DMA_FROM_DEVICE)
1953                 if (d40c->runtime_addr)
1954                         dev_addr = d40c->runtime_addr;
1955                 else
1956                         dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1957         else if (direction == DMA_TO_DEVICE)
1958                 if (d40c->runtime_addr)
1959                         dev_addr = d40c->runtime_addr;
1960                 else
1961                         dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1962
1963         else
1964                 return -EINVAL;
1965
1966         total_size = d40_log_sg_to_dev(sgl, sg_len,
1967                                        &d40d->lli_log,
1968                                        &d40c->log_def,
1969                                        d40c->dma_cfg.src_info.data_width,
1970                                        d40c->dma_cfg.dst_info.data_width,
1971                                        direction,
1972                                        dev_addr);
1973
1974         if (total_size < 0)
1975                 return -EINVAL;
1976
1977         return 0;
1978 }
1979
1980 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
1981                                  struct d40_chan *d40c,
1982                                  struct scatterlist *sgl,
1983                                  unsigned int sgl_len,
1984                                  enum dma_data_direction direction,
1985                                  unsigned long dma_flags)
1986 {
1987         dma_addr_t src_dev_addr;
1988         dma_addr_t dst_dev_addr;
1989         int res;
1990
1991         d40d->lli_len = d40_sg_2_dmalen(sgl, sgl_len,
1992                                         d40c->dma_cfg.src_info.data_width,
1993                                         d40c->dma_cfg.dst_info.data_width);
1994         if (d40d->lli_len < 0) {
1995                 chan_err(d40c, "Unaligned size\n");
1996                 return -EINVAL;
1997         }
1998
1999         if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
2000                 chan_err(d40c, "Out of memory\n");
2001                 return -ENOMEM;
2002         }
2003
2004         d40d->lli_current = 0;
2005
2006         if (direction == DMA_FROM_DEVICE) {
2007                 dst_dev_addr = 0;
2008                 if (d40c->runtime_addr)
2009                         src_dev_addr = d40c->runtime_addr;
2010                 else
2011                         src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
2012         } else if (direction == DMA_TO_DEVICE) {
2013                 if (d40c->runtime_addr)
2014                         dst_dev_addr = d40c->runtime_addr;
2015                 else
2016                         dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
2017                 src_dev_addr = 0;
2018         } else
2019                 return -EINVAL;
2020
2021         res = d40_phy_sg_to_lli(sgl,
2022                                 sgl_len,
2023                                 src_dev_addr,
2024                                 d40d->lli_phy.src,
2025                                 virt_to_phys(d40d->lli_phy.src),
2026                                 d40c->src_def_cfg,
2027                                 d40c->dma_cfg.src_info.data_width,
2028                                 d40c->dma_cfg.dst_info.data_width,
2029                                 d40c->dma_cfg.src_info.psize);
2030         if (res < 0)
2031                 return res;
2032
2033         res = d40_phy_sg_to_lli(sgl,
2034                                 sgl_len,
2035                                 dst_dev_addr,
2036                                 d40d->lli_phy.dst,
2037                                 virt_to_phys(d40d->lli_phy.dst),
2038                                 d40c->dst_def_cfg,
2039                                 d40c->dma_cfg.dst_info.data_width,
2040                                 d40c->dma_cfg.src_info.data_width,
2041                                 d40c->dma_cfg.dst_info.psize);
2042         if (res < 0)
2043                 return res;
2044
2045         (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
2046                               d40d->lli_pool.size, DMA_TO_DEVICE);
2047         return 0;
2048 }
2049
2050 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2051                                                          struct scatterlist *sgl,
2052                                                          unsigned int sg_len,
2053                                                          enum dma_data_direction direction,
2054                                                          unsigned long dma_flags)
2055 {
2056         struct d40_desc *d40d;
2057         struct d40_chan *d40c = container_of(chan, struct d40_chan,
2058                                              chan);
2059         unsigned long flags;
2060         int err;
2061
2062         if (d40c->phy_chan == NULL) {
2063                 chan_err(d40c, "Cannot prepare unallocated channel\n");
2064                 return ERR_PTR(-EINVAL);
2065         }
2066
2067         spin_lock_irqsave(&d40c->lock, flags);
2068         d40d = d40_desc_get(d40c);
2069
2070         if (d40d == NULL)
2071                 goto err;
2072
2073         if (chan_is_logical(d40c))
2074                 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2075                                             direction, dma_flags);
2076         else
2077                 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2078                                             direction, dma_flags);
2079         if (err) {
2080                 chan_err(d40c, "Failed to prepare %s slave sg job: %d\n",
2081                         chan_is_logical(d40c) ? "log" : "phy", err);
2082                 goto err;
2083         }
2084
2085         d40d->txd.flags = dma_flags;
2086
2087         dma_async_tx_descriptor_init(&d40d->txd, chan);
2088
2089         d40d->txd.tx_submit = d40_tx_submit;
2090
2091         spin_unlock_irqrestore(&d40c->lock, flags);
2092         return &d40d->txd;
2093
2094 err:
2095         if (d40d)
2096                 d40_desc_free(d40c, d40d);
2097         spin_unlock_irqrestore(&d40c->lock, flags);
2098         return NULL;
2099 }
2100
2101 static enum dma_status d40_tx_status(struct dma_chan *chan,
2102                                      dma_cookie_t cookie,
2103                                      struct dma_tx_state *txstate)
2104 {
2105         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2106         dma_cookie_t last_used;
2107         dma_cookie_t last_complete;
2108         int ret;
2109
2110         if (d40c->phy_chan == NULL) {
2111                 chan_err(d40c, "Cannot read status of unallocated channel\n");
2112                 return -EINVAL;
2113         }
2114
2115         last_complete = d40c->completed;
2116         last_used = chan->cookie;
2117
2118         if (d40_is_paused(d40c))
2119                 ret = DMA_PAUSED;
2120         else
2121                 ret = dma_async_is_complete(cookie, last_complete, last_used);
2122
2123         dma_set_tx_state(txstate, last_complete, last_used,
2124                          stedma40_residue(chan));
2125
2126         return ret;
2127 }
2128
2129 static void d40_issue_pending(struct dma_chan *chan)
2130 {
2131         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2132         unsigned long flags;
2133
2134         if (d40c->phy_chan == NULL) {
2135                 chan_err(d40c, "Channel is not allocated!\n");
2136                 return;
2137         }
2138
2139         spin_lock_irqsave(&d40c->lock, flags);
2140
2141         /* Busy means that pending jobs are already being processed */
2142         if (!d40c->busy)
2143                 (void) d40_queue_start(d40c);
2144
2145         spin_unlock_irqrestore(&d40c->lock, flags);
2146 }
2147
2148 /* Runtime reconfiguration extension */
2149 static void d40_set_runtime_config(struct dma_chan *chan,
2150                                struct dma_slave_config *config)
2151 {
2152         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2153         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2154         enum dma_slave_buswidth config_addr_width;
2155         dma_addr_t config_addr;
2156         u32 config_maxburst;
2157         enum stedma40_periph_data_width addr_width;
2158         int psize;
2159
2160         if (config->direction == DMA_FROM_DEVICE) {
2161                 dma_addr_t dev_addr_rx =
2162                         d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2163
2164                 config_addr = config->src_addr;
2165                 if (dev_addr_rx)
2166                         dev_dbg(d40c->base->dev,
2167                                 "channel has a pre-wired RX address %08x "
2168                                 "overriding with %08x\n",
2169                                 dev_addr_rx, config_addr);
2170                 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2171                         dev_dbg(d40c->base->dev,
2172                                 "channel was not configured for peripheral "
2173                                 "to memory transfer (%d) overriding\n",
2174                                 cfg->dir);
2175                 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2176
2177                 config_addr_width = config->src_addr_width;
2178                 config_maxburst = config->src_maxburst;
2179
2180         } else if (config->direction == DMA_TO_DEVICE) {
2181                 dma_addr_t dev_addr_tx =
2182                         d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2183
2184                 config_addr = config->dst_addr;
2185                 if (dev_addr_tx)
2186                         dev_dbg(d40c->base->dev,
2187                                 "channel has a pre-wired TX address %08x "
2188                                 "overriding with %08x\n",
2189                                 dev_addr_tx, config_addr);
2190                 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2191                         dev_dbg(d40c->base->dev,
2192                                 "channel was not configured for memory "
2193                                 "to peripheral transfer (%d) overriding\n",
2194                                 cfg->dir);
2195                 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2196
2197                 config_addr_width = config->dst_addr_width;
2198                 config_maxburst = config->dst_maxburst;
2199
2200         } else {
2201                 dev_err(d40c->base->dev,
2202                         "unrecognized channel direction %d\n",
2203                         config->direction);
2204                 return;
2205         }
2206
2207         switch (config_addr_width) {
2208         case DMA_SLAVE_BUSWIDTH_1_BYTE:
2209                 addr_width = STEDMA40_BYTE_WIDTH;
2210                 break;
2211         case DMA_SLAVE_BUSWIDTH_2_BYTES:
2212                 addr_width = STEDMA40_HALFWORD_WIDTH;
2213                 break;
2214         case DMA_SLAVE_BUSWIDTH_4_BYTES:
2215                 addr_width = STEDMA40_WORD_WIDTH;
2216                 break;
2217         case DMA_SLAVE_BUSWIDTH_8_BYTES:
2218                 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2219                 break;
2220         default:
2221                 dev_err(d40c->base->dev,
2222                         "illegal peripheral address width "
2223                         "requested (%d)\n",
2224                         config->src_addr_width);
2225                 return;
2226         }
2227
2228         if (chan_is_logical(d40c)) {
2229                 if (config_maxburst >= 16)
2230                         psize = STEDMA40_PSIZE_LOG_16;
2231                 else if (config_maxburst >= 8)
2232                         psize = STEDMA40_PSIZE_LOG_8;
2233                 else if (config_maxburst >= 4)
2234                         psize = STEDMA40_PSIZE_LOG_4;
2235                 else
2236                         psize = STEDMA40_PSIZE_LOG_1;
2237         } else {
2238                 if (config_maxburst >= 16)
2239                         psize = STEDMA40_PSIZE_PHY_16;
2240                 else if (config_maxburst >= 8)
2241                         psize = STEDMA40_PSIZE_PHY_8;
2242                 else if (config_maxburst >= 4)
2243                         psize = STEDMA40_PSIZE_PHY_4;
2244                 else if (config_maxburst >= 2)
2245                         psize = STEDMA40_PSIZE_PHY_2;
2246                 else
2247                         psize = STEDMA40_PSIZE_PHY_1;
2248         }
2249
2250         /* Set up all the endpoint configs */
2251         cfg->src_info.data_width = addr_width;
2252         cfg->src_info.psize = psize;
2253         cfg->src_info.big_endian = false;
2254         cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2255         cfg->dst_info.data_width = addr_width;
2256         cfg->dst_info.psize = psize;
2257         cfg->dst_info.big_endian = false;
2258         cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2259
2260         /* Fill in register values */
2261         if (chan_is_logical(d40c))
2262                 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2263         else
2264                 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2265                             &d40c->dst_def_cfg, false);
2266
2267         /* These settings will take precedence later */
2268         d40c->runtime_addr = config_addr;
2269         d40c->runtime_direction = config->direction;
2270         dev_dbg(d40c->base->dev,
2271                 "configured channel %s for %s, data width %d, "
2272                 "maxburst %d bytes, LE, no flow control\n",
2273                 dma_chan_name(chan),
2274                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2275                 config_addr_width,
2276                 config_maxburst);
2277 }
2278
2279 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2280                        unsigned long arg)
2281 {
2282         unsigned long flags;
2283         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2284
2285         if (d40c->phy_chan == NULL) {
2286                 chan_err(d40c, "Channel is not allocated!\n");
2287                 return -EINVAL;
2288         }
2289
2290         switch (cmd) {
2291         case DMA_TERMINATE_ALL:
2292                 spin_lock_irqsave(&d40c->lock, flags);
2293                 d40_term_all(d40c);
2294                 spin_unlock_irqrestore(&d40c->lock, flags);
2295                 return 0;
2296         case DMA_PAUSE:
2297                 return d40_pause(chan);
2298         case DMA_RESUME:
2299                 return d40_resume(chan);
2300         case DMA_SLAVE_CONFIG:
2301                 d40_set_runtime_config(chan,
2302                         (struct dma_slave_config *) arg);
2303                 return 0;
2304         default:
2305                 break;
2306         }
2307
2308         /* Other commands are unimplemented */
2309         return -ENXIO;
2310 }
2311
2312 /* Initialization functions */
2313
2314 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2315                                  struct d40_chan *chans, int offset,
2316                                  int num_chans)
2317 {
2318         int i = 0;
2319         struct d40_chan *d40c;
2320
2321         INIT_LIST_HEAD(&dma->channels);
2322
2323         for (i = offset; i < offset + num_chans; i++) {
2324                 d40c = &chans[i];
2325                 d40c->base = base;
2326                 d40c->chan.device = dma;
2327
2328                 spin_lock_init(&d40c->lock);
2329
2330                 d40c->log_num = D40_PHY_CHAN;
2331
2332                 INIT_LIST_HEAD(&d40c->active);
2333                 INIT_LIST_HEAD(&d40c->queue);
2334                 INIT_LIST_HEAD(&d40c->client);
2335
2336                 tasklet_init(&d40c->tasklet, dma_tasklet,
2337                              (unsigned long) d40c);
2338
2339                 list_add_tail(&d40c->chan.device_node,
2340                               &dma->channels);
2341         }
2342 }
2343
2344 static int __init d40_dmaengine_init(struct d40_base *base,
2345                                      int num_reserved_chans)
2346 {
2347         int err ;
2348
2349         d40_chan_init(base, &base->dma_slave, base->log_chans,
2350                       0, base->num_log_chans);
2351
2352         dma_cap_zero(base->dma_slave.cap_mask);
2353         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2354
2355         base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2356         base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2357         base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2358         base->dma_slave.device_prep_dma_sg = d40_prep_sg;
2359         base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2360         base->dma_slave.device_tx_status = d40_tx_status;
2361         base->dma_slave.device_issue_pending = d40_issue_pending;
2362         base->dma_slave.device_control = d40_control;
2363         base->dma_slave.dev = base->dev;
2364
2365         err = dma_async_device_register(&base->dma_slave);
2366
2367         if (err) {
2368                 d40_err(base->dev, "Failed to register slave channels\n");
2369                 goto failure1;
2370         }
2371
2372         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2373                       base->num_log_chans, base->plat_data->memcpy_len);
2374
2375         dma_cap_zero(base->dma_memcpy.cap_mask);
2376         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2377         dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
2378
2379         base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2380         base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2381         base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2382         base->dma_slave.device_prep_dma_sg = d40_prep_sg;
2383         base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2384         base->dma_memcpy.device_tx_status = d40_tx_status;
2385         base->dma_memcpy.device_issue_pending = d40_issue_pending;
2386         base->dma_memcpy.device_control = d40_control;
2387         base->dma_memcpy.dev = base->dev;
2388         /*
2389          * This controller can only access address at even
2390          * 32bit boundaries, i.e. 2^2
2391          */
2392         base->dma_memcpy.copy_align = 2;
2393
2394         err = dma_async_device_register(&base->dma_memcpy);
2395
2396         if (err) {
2397                 d40_err(base->dev,
2398                         "Failed to regsiter memcpy only channels\n");
2399                 goto failure2;
2400         }
2401
2402         d40_chan_init(base, &base->dma_both, base->phy_chans,
2403                       0, num_reserved_chans);
2404
2405         dma_cap_zero(base->dma_both.cap_mask);
2406         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2407         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2408         dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
2409
2410         base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2411         base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2412         base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2413         base->dma_slave.device_prep_dma_sg = d40_prep_sg;
2414         base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2415         base->dma_both.device_tx_status = d40_tx_status;
2416         base->dma_both.device_issue_pending = d40_issue_pending;
2417         base->dma_both.device_control = d40_control;
2418         base->dma_both.dev = base->dev;
2419         base->dma_both.copy_align = 2;
2420         err = dma_async_device_register(&base->dma_both);
2421
2422         if (err) {
2423                 d40_err(base->dev,
2424                         "Failed to register logical and physical capable channels\n");
2425                 goto failure3;
2426         }
2427         return 0;
2428 failure3:
2429         dma_async_device_unregister(&base->dma_memcpy);
2430 failure2:
2431         dma_async_device_unregister(&base->dma_slave);
2432 failure1:
2433         return err;
2434 }
2435
2436 /* Initialization functions. */
2437
2438 static int __init d40_phy_res_init(struct d40_base *base)
2439 {
2440         int i;
2441         int num_phy_chans_avail = 0;
2442         u32 val[2];
2443         int odd_even_bit = -2;
2444
2445         val[0] = readl(base->virtbase + D40_DREG_PRSME);
2446         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2447
2448         for (i = 0; i < base->num_phy_chans; i++) {
2449                 base->phy_res[i].num = i;
2450                 odd_even_bit += 2 * ((i % 2) == 0);
2451                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2452                         /* Mark security only channels as occupied */
2453                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2454                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2455                 } else {
2456                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2457                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2458                         num_phy_chans_avail++;
2459                 }
2460                 spin_lock_init(&base->phy_res[i].lock);
2461         }
2462
2463         /* Mark disabled channels as occupied */
2464         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2465                 int chan = base->plat_data->disabled_channels[i];
2466
2467                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2468                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2469                 num_phy_chans_avail--;
2470         }
2471
2472         dev_info(base->dev, "%d of %d physical DMA channels available\n",
2473                  num_phy_chans_avail, base->num_phy_chans);
2474
2475         /* Verify settings extended vs standard */
2476         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2477
2478         for (i = 0; i < base->num_phy_chans; i++) {
2479
2480                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2481                     (val[0] & 0x3) != 1)
2482                         dev_info(base->dev,
2483                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
2484                                  __func__, i, val[0] & 0x3);
2485
2486                 val[0] = val[0] >> 2;
2487         }
2488
2489         return num_phy_chans_avail;
2490 }
2491
2492 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2493 {
2494         static const struct d40_reg_val dma_id_regs[] = {
2495                 /* Peripheral Id */
2496                 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2497                 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2498                 /*
2499                  * D40_DREG_PERIPHID2 Depends on HW revision:
2500                  *  MOP500/HREF ED has 0x0008,
2501                  *  ? has 0x0018,
2502                  *  HREF V1 has 0x0028
2503                  */
2504                 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2505
2506                 /* PCell Id */
2507                 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2508                 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2509                 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2510                 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2511         };
2512         struct stedma40_platform_data *plat_data;
2513         struct clk *clk = NULL;
2514         void __iomem *virtbase = NULL;
2515         struct resource *res = NULL;
2516         struct d40_base *base = NULL;
2517         int num_log_chans = 0;
2518         int num_phy_chans;
2519         int i;
2520         u32 val;
2521         u32 rev;
2522
2523         clk = clk_get(&pdev->dev, NULL);
2524
2525         if (IS_ERR(clk)) {
2526                 d40_err(&pdev->dev, "No matching clock found\n");
2527                 goto failure;
2528         }
2529
2530         clk_enable(clk);
2531
2532         /* Get IO for DMAC base address */
2533         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2534         if (!res)
2535                 goto failure;
2536
2537         if (request_mem_region(res->start, resource_size(res),
2538                                D40_NAME " I/O base") == NULL)
2539                 goto failure;
2540
2541         virtbase = ioremap(res->start, resource_size(res));
2542         if (!virtbase)
2543                 goto failure;
2544
2545         /* HW version check */
2546         for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2547                 if (dma_id_regs[i].val !=
2548                     readl(virtbase + dma_id_regs[i].reg)) {
2549                         d40_err(&pdev->dev,
2550                                 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2551                                 dma_id_regs[i].val,
2552                                 dma_id_regs[i].reg,
2553                                 readl(virtbase + dma_id_regs[i].reg));
2554                         goto failure;
2555                 }
2556         }
2557
2558         /* Get silicon revision and designer */
2559         val = readl(virtbase + D40_DREG_PERIPHID2);
2560
2561         if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2562             D40_HW_DESIGNER) {
2563                 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2564                         val & D40_DREG_PERIPHID2_DESIGNER_MASK,
2565                         D40_HW_DESIGNER);
2566                 goto failure;
2567         }
2568
2569         rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2570                 D40_DREG_PERIPHID2_REV_POS;
2571
2572         /* The number of physical channels on this HW */
2573         num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2574
2575         dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2576                  rev, res->start);
2577
2578         plat_data = pdev->dev.platform_data;
2579
2580         /* Count the number of logical channels in use */
2581         for (i = 0; i < plat_data->dev_len; i++)
2582                 if (plat_data->dev_rx[i] != 0)
2583                         num_log_chans++;
2584
2585         for (i = 0; i < plat_data->dev_len; i++)
2586                 if (plat_data->dev_tx[i] != 0)
2587                         num_log_chans++;
2588
2589         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2590                        (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2591                        sizeof(struct d40_chan), GFP_KERNEL);
2592
2593         if (base == NULL) {
2594                 d40_err(&pdev->dev, "Out of memory\n");
2595                 goto failure;
2596         }
2597
2598         base->rev = rev;
2599         base->clk = clk;
2600         base->num_phy_chans = num_phy_chans;
2601         base->num_log_chans = num_log_chans;
2602         base->phy_start = res->start;
2603         base->phy_size = resource_size(res);
2604         base->virtbase = virtbase;
2605         base->plat_data = plat_data;
2606         base->dev = &pdev->dev;
2607         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2608         base->log_chans = &base->phy_chans[num_phy_chans];
2609
2610         base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2611                                 GFP_KERNEL);
2612         if (!base->phy_res)
2613                 goto failure;
2614
2615         base->lookup_phy_chans = kzalloc(num_phy_chans *
2616                                          sizeof(struct d40_chan *),
2617                                          GFP_KERNEL);
2618         if (!base->lookup_phy_chans)
2619                 goto failure;
2620
2621         if (num_log_chans + plat_data->memcpy_len) {
2622                 /*
2623                  * The max number of logical channels are event lines for all
2624                  * src devices and dst devices
2625                  */
2626                 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2627                                                  sizeof(struct d40_chan *),
2628                                                  GFP_KERNEL);
2629                 if (!base->lookup_log_chans)
2630                         goto failure;
2631         }
2632
2633         base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2634                                             sizeof(struct d40_desc *) *
2635                                             D40_LCLA_LINK_PER_EVENT_GRP,
2636                                             GFP_KERNEL);
2637         if (!base->lcla_pool.alloc_map)
2638                 goto failure;
2639
2640         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2641                                             0, SLAB_HWCACHE_ALIGN,
2642                                             NULL);
2643         if (base->desc_slab == NULL)
2644                 goto failure;
2645
2646         return base;
2647
2648 failure:
2649         if (!IS_ERR(clk)) {
2650                 clk_disable(clk);
2651                 clk_put(clk);
2652         }
2653         if (virtbase)
2654                 iounmap(virtbase);
2655         if (res)
2656                 release_mem_region(res->start,
2657                                    resource_size(res));
2658         if (virtbase)
2659                 iounmap(virtbase);
2660
2661         if (base) {
2662                 kfree(base->lcla_pool.alloc_map);
2663                 kfree(base->lookup_log_chans);
2664                 kfree(base->lookup_phy_chans);
2665                 kfree(base->phy_res);
2666                 kfree(base);
2667         }
2668
2669         return NULL;
2670 }
2671
2672 static void __init d40_hw_init(struct d40_base *base)
2673 {
2674
2675         static const struct d40_reg_val dma_init_reg[] = {
2676                 /* Clock every part of the DMA block from start */
2677                 { .reg = D40_DREG_GCC,    .val = 0x0000ff01},
2678
2679                 /* Interrupts on all logical channels */
2680                 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2681                 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2682                 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2683                 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2684                 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2685                 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2686                 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2687                 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2688                 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2689                 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2690                 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2691                 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2692         };
2693         int i;
2694         u32 prmseo[2] = {0, 0};
2695         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2696         u32 pcmis = 0;
2697         u32 pcicr = 0;
2698
2699         for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2700                 writel(dma_init_reg[i].val,
2701                        base->virtbase + dma_init_reg[i].reg);
2702
2703         /* Configure all our dma channels to default settings */
2704         for (i = 0; i < base->num_phy_chans; i++) {
2705
2706                 activeo[i % 2] = activeo[i % 2] << 2;
2707
2708                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2709                     == D40_ALLOC_PHY) {
2710                         activeo[i % 2] |= 3;
2711                         continue;
2712                 }
2713
2714                 /* Enable interrupt # */
2715                 pcmis = (pcmis << 1) | 1;
2716
2717                 /* Clear interrupt # */
2718                 pcicr = (pcicr << 1) | 1;
2719
2720                 /* Set channel to physical mode */
2721                 prmseo[i % 2] = prmseo[i % 2] << 2;
2722                 prmseo[i % 2] |= 1;
2723
2724         }
2725
2726         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2727         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2728         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2729         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2730
2731         /* Write which interrupt to enable */
2732         writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2733
2734         /* Write which interrupt to clear */
2735         writel(pcicr, base->virtbase + D40_DREG_PCICR);
2736
2737 }
2738
2739 static int __init d40_lcla_allocate(struct d40_base *base)
2740 {
2741         unsigned long *page_list;
2742         int i, j;
2743         int ret = 0;
2744
2745         /*
2746          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2747          * To full fill this hardware requirement without wasting 256 kb
2748          * we allocate pages until we get an aligned one.
2749          */
2750         page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2751                             GFP_KERNEL);
2752
2753         if (!page_list) {
2754                 ret = -ENOMEM;
2755                 goto failure;
2756         }
2757
2758         /* Calculating how many pages that are required */
2759         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2760
2761         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2762                 page_list[i] = __get_free_pages(GFP_KERNEL,
2763                                                 base->lcla_pool.pages);
2764                 if (!page_list[i]) {
2765
2766                         d40_err(base->dev, "Failed to allocate %d pages.\n",
2767                                 base->lcla_pool.pages);
2768
2769                         for (j = 0; j < i; j++)
2770                                 free_pages(page_list[j], base->lcla_pool.pages);
2771                         goto failure;
2772                 }
2773
2774                 if ((virt_to_phys((void *)page_list[i]) &
2775                      (LCLA_ALIGNMENT - 1)) == 0)
2776                         break;
2777         }
2778
2779         for (j = 0; j < i; j++)
2780                 free_pages(page_list[j], base->lcla_pool.pages);
2781
2782         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2783                 base->lcla_pool.base = (void *)page_list[i];
2784         } else {
2785                 /*
2786                  * After many attempts and no succees with finding the correct
2787                  * alignment, try with allocating a big buffer.
2788                  */
2789                 dev_warn(base->dev,
2790                          "[%s] Failed to get %d pages @ 18 bit align.\n",
2791                          __func__, base->lcla_pool.pages);
2792                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2793                                                          base->num_phy_chans +
2794                                                          LCLA_ALIGNMENT,
2795                                                          GFP_KERNEL);
2796                 if (!base->lcla_pool.base_unaligned) {
2797                         ret = -ENOMEM;
2798                         goto failure;
2799                 }
2800
2801                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2802                                                  LCLA_ALIGNMENT);
2803         }
2804
2805         writel(virt_to_phys(base->lcla_pool.base),
2806                base->virtbase + D40_DREG_LCLA);
2807 failure:
2808         kfree(page_list);
2809         return ret;
2810 }
2811
2812 static int __init d40_probe(struct platform_device *pdev)
2813 {
2814         int err;
2815         int ret = -ENOENT;
2816         struct d40_base *base;
2817         struct resource *res = NULL;
2818         int num_reserved_chans;
2819         u32 val;
2820
2821         base = d40_hw_detect_init(pdev);
2822
2823         if (!base)
2824                 goto failure;
2825
2826         num_reserved_chans = d40_phy_res_init(base);
2827
2828         platform_set_drvdata(pdev, base);
2829
2830         spin_lock_init(&base->interrupt_lock);
2831         spin_lock_init(&base->execmd_lock);
2832
2833         /* Get IO for logical channel parameter address */
2834         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2835         if (!res) {
2836                 ret = -ENOENT;
2837                 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
2838                 goto failure;
2839         }
2840         base->lcpa_size = resource_size(res);
2841         base->phy_lcpa = res->start;
2842
2843         if (request_mem_region(res->start, resource_size(res),
2844                                D40_NAME " I/O lcpa") == NULL) {
2845                 ret = -EBUSY;
2846                 d40_err(&pdev->dev,
2847                         "Failed to request LCPA region 0x%x-0x%x\n",
2848                         res->start, res->end);
2849                 goto failure;
2850         }
2851
2852         /* We make use of ESRAM memory for this. */
2853         val = readl(base->virtbase + D40_DREG_LCPA);
2854         if (res->start != val && val != 0) {
2855                 dev_warn(&pdev->dev,
2856                          "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2857                          __func__, val, res->start);
2858         } else
2859                 writel(res->start, base->virtbase + D40_DREG_LCPA);
2860
2861         base->lcpa_base = ioremap(res->start, resource_size(res));
2862         if (!base->lcpa_base) {
2863                 ret = -ENOMEM;
2864                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
2865                 goto failure;
2866         }
2867
2868         ret = d40_lcla_allocate(base);
2869         if (ret) {
2870                 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
2871                 goto failure;
2872         }
2873
2874         spin_lock_init(&base->lcla_pool.lock);
2875
2876         base->irq = platform_get_irq(pdev, 0);
2877
2878         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2879         if (ret) {
2880                 d40_err(&pdev->dev, "No IRQ defined\n");
2881                 goto failure;
2882         }
2883
2884         err = d40_dmaengine_init(base, num_reserved_chans);
2885         if (err)
2886                 goto failure;
2887
2888         d40_hw_init(base);
2889
2890         dev_info(base->dev, "initialized\n");
2891         return 0;
2892
2893 failure:
2894         if (base) {
2895                 if (base->desc_slab)
2896                         kmem_cache_destroy(base->desc_slab);
2897                 if (base->virtbase)
2898                         iounmap(base->virtbase);
2899                 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2900                         free_pages((unsigned long)base->lcla_pool.base,
2901                                    base->lcla_pool.pages);
2902
2903                 kfree(base->lcla_pool.base_unaligned);
2904
2905                 if (base->phy_lcpa)
2906                         release_mem_region(base->phy_lcpa,
2907                                            base->lcpa_size);
2908                 if (base->phy_start)
2909                         release_mem_region(base->phy_start,
2910                                            base->phy_size);
2911                 if (base->clk) {
2912                         clk_disable(base->clk);
2913                         clk_put(base->clk);
2914                 }
2915
2916                 kfree(base->lcla_pool.alloc_map);
2917                 kfree(base->lookup_log_chans);
2918                 kfree(base->lookup_phy_chans);
2919                 kfree(base->phy_res);
2920                 kfree(base);
2921         }
2922
2923         d40_err(&pdev->dev, "probe failed\n");
2924         return ret;
2925 }
2926
2927 static struct platform_driver d40_driver = {
2928         .driver = {
2929                 .owner = THIS_MODULE,
2930                 .name  = D40_NAME,
2931         },
2932 };
2933
2934 static int __init stedma40_init(void)
2935 {
2936         return platform_driver_probe(&d40_driver, d40_probe);
2937 }
2938 arch_initcall(stedma40_init);