2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/kernel.h>
9 #include <plat/ste_dma40.h>
11 #include "ste_dma40_ll.h"
13 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
14 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
15 u32 *lcsp1, u32 *lcsp3)
20 /* src is mem? -> increase address pos */
21 if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
22 cfg->dir == STEDMA40_MEM_TO_MEM)
23 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
25 /* dst is mem? -> increase address pos */
26 if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
27 cfg->dir == STEDMA40_MEM_TO_MEM)
28 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
30 /* src is hw? -> master port 1 */
31 if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
32 cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
33 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
35 /* dst is hw? -> master port 1 */
36 if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
37 cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
38 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
40 l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
41 l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
42 l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
44 l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
45 l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
46 l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
53 /* Sets up SRC and DST CFG register for both logical and physical channels */
54 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
55 u32 *src_cfg, u32 *dst_cfg, bool is_log)
61 /* Physical channel */
62 if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
63 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
64 /* Set master port to 1 */
65 src |= 1 << D40_SREG_CFG_MST_POS;
66 src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
68 if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
69 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
71 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
73 if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
74 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
75 /* Set master port to 1 */
76 dst |= 1 << D40_SREG_CFG_MST_POS;
77 dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
79 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
80 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
82 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
84 /* Interrupt on end of transfer for destination */
85 dst |= 1 << D40_SREG_CFG_TIM_POS;
87 /* Generate interrupt on error */
88 src |= 1 << D40_SREG_CFG_EIM_POS;
89 dst |= 1 << D40_SREG_CFG_EIM_POS;
92 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
93 src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
94 src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
96 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
97 dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
98 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
102 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
103 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
106 /* Logical channel */
107 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
108 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
111 if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
112 src |= 1 << D40_SREG_CFG_PRI_POS;
113 dst |= 1 << D40_SREG_CFG_PRI_POS;
116 src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
117 dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
123 int d40_phy_fill_lli(struct d40_phy_lli *lli,
135 if (psize == STEDMA40_PSIZE_PHY_1)
138 num_elems = 2 << psize;
141 * Size is 16bit. data_width is 8, 16, 32 or 64 bit
142 * Block large than 64 KiB must be split.
144 if (data_size > (0xffff << data_width))
147 /* Must be aligned */
148 if (!IS_ALIGNED(data, 0x1 << data_width))
151 /* Transfer size can't be smaller than (num_elms * elem_size) */
152 if (data_size < num_elems * (0x1 << data_width))
155 /* The number of elements. IE now many chunks */
156 lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
159 * Distance to next element sized entry.
160 * Usually the size of the element unless you want gaps.
163 lli->reg_elt |= (0x1 << data_width) <<
164 D40_SREG_ELEM_PHY_EIDX_POS;
166 /* Where the data is */
168 lli->reg_cfg = reg_cfg;
170 /* If this scatter list entry is the last one, no next link */
172 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
174 lli->reg_lnk = next_lli;
176 /* Set/clear interrupt generation on this link item.*/
178 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
180 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
183 lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
188 int d40_phy_sg_to_lli(struct scatterlist *sg,
191 struct d40_phy_lli *lli,
199 struct scatterlist *current_sg = sg;
200 dma_addr_t next_lli_phys;
204 for_each_sg(sg, current_sg, sg_len, i) {
206 total_size += sg_dma_len(current_sg);
208 /* If this scatter list entry is the last one, no next link */
212 next_lli_phys = ALIGN(lli_phys + (i + 1) *
213 sizeof(struct d40_phy_lli),
219 dst = sg_phys(current_sg);
221 err = d40_phy_fill_lli(&lli[i],
223 sg_dma_len(current_sg),
240 void d40_phy_lli_write(void __iomem *virtbase,
242 struct d40_phy_lli *lli_dst,
243 struct d40_phy_lli *lli_src)
246 writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
247 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
248 writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
249 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
250 writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
251 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
252 writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
253 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
255 writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
256 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
257 writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
258 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
259 writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
260 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
261 writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
262 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
266 /* DMA logical lli operations */
268 static void d40_log_lli_link(struct d40_log_lli *lli_dst,
269 struct d40_log_lli *lli_src,
275 if (next != -EINVAL) {
279 lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
280 lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
283 lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
284 (slos << D40_MEM_LCSP1_SLOS_POS);
286 lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
287 (dlos << D40_MEM_LCSP1_SLOS_POS);
290 void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
291 struct d40_log_lli *lli_dst,
292 struct d40_log_lli *lli_src,
295 d40_log_lli_link(lli_dst, lli_src, next);
297 writel(lli_src->lcsp02, &lcpa[0].lcsp0);
298 writel(lli_src->lcsp13, &lcpa[0].lcsp1);
299 writel(lli_dst->lcsp02, &lcpa[0].lcsp2);
300 writel(lli_dst->lcsp13, &lcpa[0].lcsp3);
303 void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
304 struct d40_log_lli *lli_dst,
305 struct d40_log_lli *lli_src,
308 d40_log_lli_link(lli_dst, lli_src, next);
310 writel(lli_src->lcsp02, &lcla[0].lcsp02);
311 writel(lli_src->lcsp13, &lcla[0].lcsp13);
312 writel(lli_dst->lcsp02, &lcla[1].lcsp02);
313 writel(lli_dst->lcsp13, &lcla[1].lcsp13);
316 void d40_log_fill_lli(struct d40_log_lli *lli,
317 dma_addr_t data, u32 data_size,
322 lli->lcsp13 = reg_cfg;
324 /* The number of elements to transfer */
325 lli->lcsp02 = ((data_size >> data_width) <<
326 D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
327 /* 16 LSBs address of the current element */
328 lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
329 /* 16 MSBs address of the current element */
330 lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
333 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
337 int d40_log_sg_to_dev(struct scatterlist *sg,
339 struct d40_log_lli_bidir *lli,
340 struct d40_def_lcsp *lcsp,
343 enum dma_data_direction direction,
347 struct scatterlist *current_sg = sg;
350 for_each_sg(sg, current_sg, sg_len, i) {
351 total_size += sg_dma_len(current_sg);
353 if (direction == DMA_TO_DEVICE) {
354 d40_log_fill_lli(&lli->src[i],
356 sg_dma_len(current_sg),
357 lcsp->lcsp1, src_data_width,
359 d40_log_fill_lli(&lli->dst[i],
361 sg_dma_len(current_sg),
362 lcsp->lcsp3, dst_data_width,
365 d40_log_fill_lli(&lli->dst[i],
367 sg_dma_len(current_sg),
368 lcsp->lcsp3, dst_data_width,
370 d40_log_fill_lli(&lli->src[i],
372 sg_dma_len(current_sg),
373 lcsp->lcsp1, src_data_width,
380 int d40_log_sg_to_lli(struct scatterlist *sg,
382 struct d40_log_lli *lli_sg,
383 u32 lcsp13, /* src or dst*/
387 struct scatterlist *current_sg = sg;
390 for_each_sg(sg, current_sg, sg_len, i) {
391 total_size += sg_dma_len(current_sg);
393 d40_log_fill_lli(&lli_sg[i],
395 sg_dma_len(current_sg),