2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/kernel.h>
9 #include <plat/ste_dma40.h>
11 #include "ste_dma40_ll.h"
13 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
14 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
15 u32 *lcsp1, u32 *lcsp3)
20 /* src is mem? -> increase address pos */
21 if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
22 cfg->dir == STEDMA40_MEM_TO_MEM)
23 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
25 /* dst is mem? -> increase address pos */
26 if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
27 cfg->dir == STEDMA40_MEM_TO_MEM)
28 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
30 /* src is hw? -> master port 1 */
31 if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
32 cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
33 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
35 /* dst is hw? -> master port 1 */
36 if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
37 cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
38 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
40 l3 |= 1 << D40_MEM_LCSP3_DCFG_TIM_POS;
41 l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
42 l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
43 l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
44 l3 |= 1 << D40_MEM_LCSP3_DTCP_POS;
46 l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
47 l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
48 l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
49 l1 |= 1 << D40_MEM_LCSP1_STCP_POS;
56 /* Sets up SRC and DST CFG register for both logical and physical channels */
57 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
58 u32 *src_cfg, u32 *dst_cfg, bool is_log)
64 /* Physical channel */
65 if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
66 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
67 /* Set master port to 1 */
68 src |= 1 << D40_SREG_CFG_MST_POS;
69 src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
71 if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
72 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
74 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
76 if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
77 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
78 /* Set master port to 1 */
79 dst |= 1 << D40_SREG_CFG_MST_POS;
80 dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
82 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
83 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
85 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
87 /* Interrupt on end of transfer for destination */
88 dst |= 1 << D40_SREG_CFG_TIM_POS;
90 /* Generate interrupt on error */
91 src |= 1 << D40_SREG_CFG_EIM_POS;
92 dst |= 1 << D40_SREG_CFG_EIM_POS;
95 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
96 src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
97 src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
99 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
100 dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
101 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
105 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
106 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
109 /* Logical channel */
110 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
111 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
114 if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
115 src |= 1 << D40_SREG_CFG_PRI_POS;
116 dst |= 1 << D40_SREG_CFG_PRI_POS;
119 src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
120 dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
126 int d40_phy_fill_lli(struct d40_phy_lli *lli,
138 if (psize == STEDMA40_PSIZE_PHY_1)
141 num_elems = 2 << psize;
144 * Size is 16bit. data_width is 8, 16, 32 or 64 bit
145 * Block large than 64 KiB must be split.
147 if (data_size > (0xffff << data_width))
150 /* Must be aligned */
151 if (!IS_ALIGNED(data, 0x1 << data_width))
154 /* Transfer size can't be smaller than (num_elms * elem_size) */
155 if (data_size < num_elems * (0x1 << data_width))
158 /* The number of elements. IE now many chunks */
159 lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
162 * Distance to next element sized entry.
163 * Usually the size of the element unless you want gaps.
166 lli->reg_elt |= (0x1 << data_width) <<
167 D40_SREG_ELEM_PHY_EIDX_POS;
169 /* Where the data is */
171 lli->reg_cfg = reg_cfg;
173 /* If this scatter list entry is the last one, no next link */
175 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
177 lli->reg_lnk = next_lli;
179 /* Set/clear interrupt generation on this link item.*/
181 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
183 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
186 lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
191 int d40_phy_sg_to_lli(struct scatterlist *sg,
194 struct d40_phy_lli *lli,
202 struct scatterlist *current_sg = sg;
203 dma_addr_t next_lli_phys;
207 for_each_sg(sg, current_sg, sg_len, i) {
209 total_size += sg_dma_len(current_sg);
211 /* If this scatter list entry is the last one, no next link */
215 next_lli_phys = ALIGN(lli_phys + (i + 1) *
216 sizeof(struct d40_phy_lli),
222 dst = sg_phys(current_sg);
224 err = d40_phy_fill_lli(&lli[i],
226 sg_dma_len(current_sg),
243 void d40_phy_lli_write(void __iomem *virtbase,
245 struct d40_phy_lli *lli_dst,
246 struct d40_phy_lli *lli_src)
249 writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
250 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
251 writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
252 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
253 writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
254 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
255 writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
256 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
258 writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
259 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
260 writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
261 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
262 writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
263 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
264 writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
265 phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
269 /* DMA logical lli operations */
271 void d40_log_fill_lli(struct d40_log_lli *lli,
272 dma_addr_t data, u32 data_size,
273 u32 lli_next_off, u32 reg_cfg,
275 bool term_int, bool addr_inc)
277 lli->lcsp13 = reg_cfg;
279 /* The number of elements to transfer */
280 lli->lcsp02 = ((data_size >> data_width) <<
281 D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
282 /* 16 LSBs address of the current element */
283 lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
284 /* 16 MSBs address of the current element */
285 lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
288 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
290 lli->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
291 /* If this scatter list entry is the last one, no next link */
292 lli->lcsp13 |= (lli_next_off << D40_MEM_LCSP1_SLOS_POS) &
293 D40_MEM_LCSP1_SLOS_MASK;
296 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
298 lli->lcsp13 &= ~D40_MEM_LCSP1_SCFG_TIM_MASK;
301 int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
302 struct scatterlist *sg,
304 struct d40_log_lli_bidir *lli,
305 struct d40_def_lcsp *lcsp,
308 enum dma_data_direction direction,
309 dma_addr_t dev_addr, int max_len,
313 struct scatterlist *current_sg = sg;
315 u32 next_lli_off_dst = 0;
316 u32 next_lli_off_src = 0;
318 for_each_sg(sg, current_sg, sg_len, i) {
319 total_size += sg_dma_len(current_sg);
322 * If this scatter list entry is the last one or
323 * max length, terminate link.
325 if (sg_len - 1 == i || ((i+1) % max_len == 0)) {
326 next_lli_off_src = 0;
327 next_lli_off_dst = 0;
329 if (next_lli_off_dst == 0 &&
330 next_lli_off_src == 0) {
331 /* The first lli will be at next_lli_off */
332 next_lli_off_dst = (lcla->dst_id *
334 next_lli_off_src = (lcla->src_id *
342 if (direction == DMA_TO_DEVICE) {
343 d40_log_fill_lli(&lli->src[i],
345 sg_dma_len(current_sg),
347 lcsp->lcsp1, src_data_width,
350 d40_log_fill_lli(&lli->dst[i],
352 sg_dma_len(current_sg),
354 lcsp->lcsp3, dst_data_width,
355 /* No next == terminal interrupt */
359 d40_log_fill_lli(&lli->dst[i],
361 sg_dma_len(current_sg),
363 lcsp->lcsp3, dst_data_width,
364 /* No next == terminal interrupt */
367 d40_log_fill_lli(&lli->src[i],
369 sg_dma_len(current_sg),
371 lcsp->lcsp1, src_data_width,
379 int d40_log_sg_to_lli(int lcla_id,
380 struct scatterlist *sg,
382 struct d40_log_lli *lli_sg,
383 u32 lcsp13, /* src or dst*/
385 int max_len, int llis_per_log)
388 struct scatterlist *current_sg = sg;
390 u32 next_lli_off = 0;
392 for_each_sg(sg, current_sg, sg_len, i) {
393 total_size += sg_dma_len(current_sg);
396 * If this scatter list entry is the last one or
397 * max length, terminate link.
399 if (sg_len - 1 == i || ((i+1) % max_len == 0))
402 if (next_lli_off == 0)
403 /* The first lli will be at next_lli_off */
404 next_lli_off = lcla_id * llis_per_log + 1;
409 d40_log_fill_lli(&lli_sg[i],
411 sg_dma_len(current_sg),
420 int d40_log_lli_write(struct d40_log_lli_full *lcpa,
421 struct d40_log_lli *lcla_src,
422 struct d40_log_lli *lcla_dst,
423 struct d40_log_lli *lli_dst,
424 struct d40_log_lli *lli_src,
431 writel(lli_src->lcsp02, &lcpa->lcsp0);
432 writel(lli_src->lcsp13, &lcpa->lcsp1);
433 writel(lli_dst->lcsp02, &lcpa->lcsp2);
434 writel(lli_dst->lcsp13, &lcpa->lcsp3);
436 slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
437 dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
439 for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
440 writel(lli_src[i + 1].lcsp02, &lcla_src[i].lcsp02);
441 writel(lli_src[i + 1].lcsp13, &lcla_src[i].lcsp13);
442 writel(lli_dst[i + 1].lcsp02, &lcla_dst[i].lcsp02);
443 writel(lli_dst[i + 1].lcsp13, &lcla_dst[i].lcsp13);
445 slos = lli_src[i + 1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
446 dlos = lli_dst[i + 1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;