drivers/dma/tegra20-apb-dma.c

   1 /*
   2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/slab.h>
  34
  35 #include <mach/clk.h>
  36 #include "dmaengine.h"
  37
  38 #define TEGRA_APBDMA_GENERAL                    0x0
  39 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
  40
  41 #define TEGRA_APBDMA_CONTROL                    0x010
  42 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
  43 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
  44
  45 /* CSR register */
  46 #define TEGRA_APBDMA_CHAN_CSR                   0x00
  47 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
  48 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
  49 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
  50 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
  51 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
  52 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
  53 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
  54 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
  55
  56 /* STATUS register */
  57 #define TEGRA_APBDMA_CHAN_STATUS                0x004
  58 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
  59 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
  60 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
  61 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
  62 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
  63 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
  64
  65 #define TEGRA_APBDMA_CHAN_CSRE                  0x00C
  66 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE            (1 << 31)
  67
  68 /* AHB memory address */
  69 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
  70
  71 /* AHB sequence register */
  72 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
  73 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
  74 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
  75 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
  76 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
  77 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
  78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
  79 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
  80 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
  81 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
  82 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
  83 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
  84 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
  85 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
  86
  87 /* APB address */
  88 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
  89
  90 /* APB sequence register */
  91 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
  92 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
  93 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
  94 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
  95 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
  96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
  97 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
  98 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
  99
 100 /*
 101  * If any burst is in flight and DMA paused then this is the time to complete
 102  * on-flight burst and update DMA status register.
 103  */
 104 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
 105
 106 /* Channel base address offset from APBDMA base address */
 107 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
 108
 109 /* DMA channel register space size */
 110 #define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE      0x20
 111
 112 struct tegra_dma;
 113
 114 /*
 115  * tegra_dma_chip_data Tegra chip specific DMA data
 116  * @nr_channels: Number of channels available in the controller.
 117  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 118  * @support_channel_pause: Support channel wise pause of dma.
 119  */
 120 struct tegra_dma_chip_data {
 121         int nr_channels;
 122         int max_dma_count;
 123         bool support_channel_pause;
 124 };
 125
 126 /* DMA channel registers */
 127 struct tegra_dma_channel_regs {
 128         unsigned long   csr;
 129         unsigned long   ahb_ptr;
 130         unsigned long   apb_ptr;
 131         unsigned long   ahb_seq;
 132         unsigned long   apb_seq;
 133 };
 134
 135 /*
 136  * tegra_dma_sg_req: Dma request details to configure hardware. This
 137  * contains the details for one transfer to configure DMA hw.
 138  * The client's request for data transfer can be broken into multiple
 139  * sub-transfer as per requester details and hw support.
 140  * This sub transfer get added in the list of transfer and point to Tegra
 141  * DMA descriptor which manages the transfer details.
 142  */
 143 struct tegra_dma_sg_req {
 144         struct tegra_dma_channel_regs   ch_regs;
 145         int                             req_len;
 146         bool                            configured;
 147         bool                            last_sg;
 148         bool                            half_done;
 149         struct list_head                node;
 150         struct tegra_dma_desc           *dma_desc;
 151 };
 152
 153 /*
 154  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 155  * This descriptor keep track of transfer status, callbacks and request
 156  * counts etc.
 157  */
 158 struct tegra_dma_desc {
 159         struct dma_async_tx_descriptor  txd;
 160         int                             bytes_requested;
 161         int                             bytes_transferred;
 162         enum dma_status                 dma_status;
 163         struct list_head                node;
 164         struct list_head                tx_list;
 165         struct list_head                cb_node;
 166         int                             cb_count;
 167 };
 168
 169 struct tegra_dma_channel;
 170
 171 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
 172                                 bool to_terminate);
 173
 174 /* tegra_dma_channel: Channel specific information */
 175 struct tegra_dma_channel {
 176         struct dma_chan         dma_chan;
 177         char                    name[30];
 178         bool                    config_init;
 179         int                     id;
 180         int                     irq;
 181         unsigned long           chan_base_offset;
 182         spinlock_t              lock;
 183         bool                    busy;
 184         struct tegra_dma        *tdma;
 185         bool                    cyclic;
 186
 187         /* Different lists for managing the requests */
 188         struct list_head        free_sg_req;
 189         struct list_head        pending_sg_req;
 190         struct list_head        free_dma_desc;
 191         struct list_head        cb_desc;
 192
 193         /* ISR handler and tasklet for bottom half of isr handling */
 194         dma_isr_handler         isr_handler;
 195         struct tasklet_struct   tasklet;
 196         dma_async_tx_callback   callback;
 197         void                    *callback_param;
 198
 199         /* Channel-slave specific configuration */
 200         struct dma_slave_config dma_sconfig;
 201 };
 202
 203 /* tegra_dma: Tegra DMA specific information */
 204 struct tegra_dma {
 205         struct dma_device               dma_dev;
 206         struct device                   *dev;
 207         struct clk                      *dma_clk;
 208         spinlock_t                      global_lock;
 209         void __iomem                    *base_addr;
 210         const struct tegra_dma_chip_data *chip_data;
 211
 212         /* Some register need to be cache before suspend */
 213         u32                             reg_gen;
 214
 215         /* Last member of the structure */
 216         struct tegra_dma_channel channels[0];
 217 };
 218
 219 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
 220 {
 221         writel(val, tdma->base_addr + reg);
 222 }
 223
 224 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
 225 {
 226         return readl(tdma->base_addr + reg);
 227 }
 228
 229 static inline void tdc_write(struct tegra_dma_channel *tdc,
 230                 u32 reg, u32 val)
 231 {
 232         writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 233 }
 234
 235 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
 236 {
 237         return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 238 }
 239
 240 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
 241 {
 242         return container_of(dc, struct tegra_dma_channel, dma_chan);
 243 }
 244
 245 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
 246                 struct dma_async_tx_descriptor *td)
 247 {
 248         return container_of(td, struct tegra_dma_desc, txd);
 249 }
 250
 251 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
 252 {
 253         return &tdc->dma_chan.dev->device;
 254 }
 255
 256 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
 257 static int tegra_dma_runtime_suspend(struct device *dev);
 258 static int tegra_dma_runtime_resume(struct device *dev);
 259
 260 /* Get DMA desc from free list, if not there then allocate it.  */
 261 static struct tegra_dma_desc *tegra_dma_desc_get(
 262                 struct tegra_dma_channel *tdc)
 263 {
 264         struct tegra_dma_desc *dma_desc;
 265         unsigned long flags;
 266
 267         spin_lock_irqsave(&tdc->lock, flags);
 268
 269         /* Do not allocate if desc are waiting for ack */
 270         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 271                 if (async_tx_test_ack(&dma_desc->txd)) {
 272                         list_del(&dma_desc->node);
 273                         spin_unlock_irqrestore(&tdc->lock, flags);
 274                         return dma_desc;
 275                 }
 276         }
 277
 278         spin_unlock_irqrestore(&tdc->lock, flags);
 279
 280         /* Allocate DMA desc */
 281         dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
 282         if (!dma_desc) {
 283                 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
 284                 return NULL;
 285         }
 286
 287         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 288         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
 289         dma_desc->txd.flags = 0;
 290         return dma_desc;
 291 }
 292
 293 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
 294                 struct tegra_dma_desc *dma_desc)
 295 {
 296         unsigned long flags;
 297
 298         spin_lock_irqsave(&tdc->lock, flags);
 299         if (!list_empty(&dma_desc->tx_list))
 300                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
 301         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 302         spin_unlock_irqrestore(&tdc->lock, flags);
 303 }
 304
 305 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
 306                 struct tegra_dma_channel *tdc)
 307 {
 308         struct tegra_dma_sg_req *sg_req = NULL;
 309         unsigned long flags;
 310
 311         spin_lock_irqsave(&tdc->lock, flags);
 312         if (!list_empty(&tdc->free_sg_req)) {
 313                 sg_req = list_first_entry(&tdc->free_sg_req,
 314                                         typeof(*sg_req), node);
 315                 list_del(&sg_req->node);
 316                 spin_unlock_irqrestore(&tdc->lock, flags);
 317                 return sg_req;
 318         }
 319         spin_unlock_irqrestore(&tdc->lock, flags);
 320
 321         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
 322         if (!sg_req)
 323                 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
 324         return sg_req;
 325 }
 326
 327 static int tegra_dma_slave_config(struct dma_chan *dc,
 328                 struct dma_slave_config *sconfig)
 329 {
 330         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 331
 332         if (!list_empty(&tdc->pending_sg_req)) {
 333                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
 334                 return -EBUSY;
 335         }
 336
 337         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
 338         tdc->config_init = true;
 339         return 0;
 340 }
 341
 342 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
 343         bool wait_for_burst_complete)
 344 {
 345         struct tegra_dma *tdma = tdc->tdma;
 346
 347         spin_lock(&tdma->global_lock);
 348         tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
 349         if (wait_for_burst_complete)
 350                 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 351 }
 352
 353 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
 354 {
 355         struct tegra_dma *tdma = tdc->tdma;
 356
 357         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
 358         spin_unlock(&tdma->global_lock);
 359 }
 360
 361 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
 362         bool wait_for_burst_complete)
 363 {
 364         struct tegra_dma *tdma = tdc->tdma;
 365
 366         if (tdma->chip_data->support_channel_pause) {
 367                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
 368                                 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
 369                 if (wait_for_burst_complete)
 370                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 371         } else {
 372                 tegra_dma_global_pause(tdc, wait_for_burst_complete);
 373         }
 374 }
 375
 376 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
 377 {
 378         struct tegra_dma *tdma = tdc->tdma;
 379
 380         if (tdma->chip_data->support_channel_pause) {
 381                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
 382         } else {
 383                 tegra_dma_global_resume(tdc);
 384         }
 385 }
 386
 387 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
 388 {
 389         u32 csr;
 390         u32 status;
 391
 392         /* Disable interrupts */
 393         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
 394         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
 395         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 396
 397         /* Disable DMA */
 398         csr &= ~TEGRA_APBDMA_CSR_ENB;
 399         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 400
 401         /* Clear interrupt status if it is there */
 402         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 403         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 404                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
 405                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 406         }
 407         tdc->busy = false;
 408 }
 409
 410 static void tegra_dma_start(struct tegra_dma_channel *tdc,
 411                 struct tegra_dma_sg_req *sg_req)
 412 {
 413         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
 414
 415         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
 416         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
 417         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
 418         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
 419         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
 420
 421         /* Start DMA */
 422         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 423                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
 424 }
 425
 426 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
 427                 struct tegra_dma_sg_req *nsg_req)
 428 {
 429         unsigned long status;
 430
 431         /*
 432          * The DMA controller reloads the new configuration for next transfer
 433          * after last burst of current transfer completes.
 434          * If there is no IEC status then this makes sure that last burst
 435          * has not be completed. There may be case that last burst is on
 436          * flight and so it can complete but because DMA is paused, it
 437          * will not generates interrupt as well as not reload the new
 438          * configuration.
 439          * If there is already IEC status then interrupt handler need to
 440          * load new configuration.
 441          */
 442         tegra_dma_pause(tdc, false);
 443         status  = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 444
 445         /*
 446          * If interrupt is pending then do nothing as the ISR will handle
 447          * the programing for new request.
 448          */
 449         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 450                 dev_err(tdc2dev(tdc),
 451                         "Skipping new configuration as interrupt is pending\n");
 452                 tegra_dma_resume(tdc);
 453                 return;
 454         }
 455
 456         /* Safe to program new configuration */
 457         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
 458         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
 459         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 460                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
 461         nsg_req->configured = true;
 462
 463         tegra_dma_resume(tdc);
 464 }
 465
 466 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
 467 {
 468         struct tegra_dma_sg_req *sg_req;
 469
 470         if (list_empty(&tdc->pending_sg_req))
 471                 return;
 472
 473         sg_req = list_first_entry(&tdc->pending_sg_req,
 474                                         typeof(*sg_req), node);
 475         tegra_dma_start(tdc, sg_req);
 476         sg_req->configured = true;
 477         tdc->busy = true;
 478 }
 479
 480 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
 481 {
 482         struct tegra_dma_sg_req *hsgreq;
 483         struct tegra_dma_sg_req *hnsgreq;
 484
 485         if (list_empty(&tdc->pending_sg_req))
 486                 return;
 487
 488         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 489         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
 490                 hnsgreq = list_first_entry(&hsgreq->node,
 491                                         typeof(*hnsgreq), node);
 492                 tegra_dma_configure_for_next(tdc, hnsgreq);
 493         }
 494 }
 495
 496 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
 497         struct tegra_dma_sg_req *sg_req, unsigned long status)
 498 {
 499         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
 500 }
 501
 502 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
 503 {
 504         struct tegra_dma_sg_req *sgreq;
 505         struct tegra_dma_desc *dma_desc;
 506
 507         while (!list_empty(&tdc->pending_sg_req)) {
 508                 sgreq = list_first_entry(&tdc->pending_sg_req,
 509                                                 typeof(*sgreq), node);
 510                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
 511                 if (sgreq->last_sg) {
 512                         dma_desc = sgreq->dma_desc;
 513                         dma_desc->dma_status = DMA_ERROR;
 514                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 515
 516                         /* Add in cb list if it is not there. */
 517                         if (!dma_desc->cb_count)
 518                                 list_add_tail(&dma_desc->cb_node,
 519                                                         &tdc->cb_desc);
 520                         dma_desc->cb_count++;
 521                 }
 522         }
 523         tdc->isr_handler = NULL;
 524 }
 525
 526 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
 527                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
 528 {
 529         struct tegra_dma_sg_req *hsgreq = NULL;
 530
 531         if (list_empty(&tdc->pending_sg_req)) {
 532                 dev_err(tdc2dev(tdc), "Dma is running without req\n");
 533                 tegra_dma_stop(tdc);
 534                 return false;
 535         }
 536
 537         /*
 538          * Check that head req on list should be in flight.
 539          * If it is not in flight then abort transfer as
 540          * looping of transfer can not continue.
 541          */
 542         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 543         if (!hsgreq->configured) {
 544                 tegra_dma_stop(tdc);
 545                 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
 546                 tegra_dma_abort_all(tdc);
 547                 return false;
 548         }
 549
 550         /* Configure next request */
 551         if (!to_terminate)
 552                 tdc_configure_next_head_desc(tdc);
 553         return true;
 554 }
 555
 556 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
 557         bool to_terminate)
 558 {
 559         struct tegra_dma_sg_req *sgreq;
 560         struct tegra_dma_desc *dma_desc;
 561
 562         tdc->busy = false;
 563         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 564         dma_desc = sgreq->dma_desc;
 565         dma_desc->bytes_transferred += sgreq->req_len;
 566
 567         list_del(&sgreq->node);
 568         if (sgreq->last_sg) {
 569                 dma_desc->dma_status = DMA_SUCCESS;
 570                 dma_cookie_complete(&dma_desc->txd);
 571                 if (!dma_desc->cb_count)
 572                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 573                 dma_desc->cb_count++;
 574                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 575         }
 576         list_add_tail(&sgreq->node, &tdc->free_sg_req);
 577
 578         /* Do not start DMA if it is going to be terminate */
 579         if (to_terminate || list_empty(&tdc->pending_sg_req))
 580                 return;
 581
 582         tdc_start_head_req(tdc);
 583         return;
 584 }
 585
 586 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
 587                 bool to_terminate)
 588 {
 589         struct tegra_dma_sg_req *sgreq;
 590         struct tegra_dma_desc *dma_desc;
 591         bool st;
 592
 593         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 594         dma_desc = sgreq->dma_desc;
 595         dma_desc->bytes_transferred += sgreq->req_len;
 596
 597         /* Callback need to be call */
 598         if (!dma_desc->cb_count)
 599                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 600         dma_desc->cb_count++;
 601
 602         /* If not last req then put at end of pending list */
 603         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
 604                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
 605                 sgreq->configured = false;
 606                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
 607                 if (!st)
 608                         dma_desc->dma_status = DMA_ERROR;
 609         }
 610         return;
 611 }
 612
 613 static void tegra_dma_tasklet(unsigned long data)
 614 {
 615         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
 616         dma_async_tx_callback callback = NULL;
 617         void *callback_param = NULL;
 618         struct tegra_dma_desc *dma_desc;
 619         unsigned long flags;
 620         int cb_count;
 621
 622         spin_lock_irqsave(&tdc->lock, flags);
 623         while (!list_empty(&tdc->cb_desc)) {
 624                 dma_desc  = list_first_entry(&tdc->cb_desc,
 625                                         typeof(*dma_desc), cb_node);
 626                 list_del(&dma_desc->cb_node);
 627                 callback = dma_desc->txd.callback;
 628                 callback_param = dma_desc->txd.callback_param;
 629                 cb_count = dma_desc->cb_count;
 630                 dma_desc->cb_count = 0;
 631                 spin_unlock_irqrestore(&tdc->lock, flags);
 632                 while (cb_count-- && callback)
 633                         callback(callback_param);
 634                 spin_lock_irqsave(&tdc->lock, flags);
 635         }
 636         spin_unlock_irqrestore(&tdc->lock, flags);
 637 }
 638
 639 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
 640 {
 641         struct tegra_dma_channel *tdc = dev_id;
 642         unsigned long status;
 643         unsigned long flags;
 644
 645         spin_lock_irqsave(&tdc->lock, flags);
 646
 647         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 648         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 649                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 650                 tdc->isr_handler(tdc, false);
 651                 tasklet_schedule(&tdc->tasklet);
 652                 spin_unlock_irqrestore(&tdc->lock, flags);
 653                 return IRQ_HANDLED;
 654         }
 655
 656         spin_unlock_irqrestore(&tdc->lock, flags);
 657         dev_info(tdc2dev(tdc),
 658                 "Interrupt already served status 0x%08lx\n", status);
 659         return IRQ_NONE;
 660 }
 661
 662 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 663 {
 664         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 665         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
 666         unsigned long flags;
 667         dma_cookie_t cookie;
 668
 669         spin_lock_irqsave(&tdc->lock, flags);
 670         dma_desc->dma_status = DMA_IN_PROGRESS;
 671         cookie = dma_cookie_assign(&dma_desc->txd);
 672         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
 673         spin_unlock_irqrestore(&tdc->lock, flags);
 674         return cookie;
 675 }
 676
 677 static void tegra_dma_issue_pending(struct dma_chan *dc)
 678 {
 679         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 680         unsigned long flags;
 681
 682         spin_lock_irqsave(&tdc->lock, flags);
 683         if (list_empty(&tdc->pending_sg_req)) {
 684                 dev_err(tdc2dev(tdc), "No DMA request\n");
 685                 goto end;
 686         }
 687         if (!tdc->busy) {
 688                 tdc_start_head_req(tdc);
 689
 690                 /* Continuous single mode: Configure next req */
 691                 if (tdc->cyclic) {
 692                         /*
 693                          * Wait for 1 burst time for configure DMA for
 694                          * next transfer.
 695                          */
 696                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 697                         tdc_configure_next_head_desc(tdc);
 698                 }
 699         }
 700 end:
 701         spin_unlock_irqrestore(&tdc->lock, flags);
 702         return;
 703 }
 704
 705 static void tegra_dma_terminate_all(struct dma_chan *dc)
 706 {
 707         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 708         struct tegra_dma_sg_req *sgreq;
 709         struct tegra_dma_desc *dma_desc;
 710         unsigned long flags;
 711         unsigned long status;
 712         bool was_busy;
 713
 714         spin_lock_irqsave(&tdc->lock, flags);
 715         if (list_empty(&tdc->pending_sg_req)) {
 716                 spin_unlock_irqrestore(&tdc->lock, flags);
 717                 return;
 718         }
 719
 720         if (!tdc->busy)
 721                 goto skip_dma_stop;
 722
 723         /* Pause DMA before checking the queue status */
 724         tegra_dma_pause(tdc, true);
 725
 726         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 727         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 728                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
 729                 tdc->isr_handler(tdc, true);
 730                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 731         }
 732
 733         was_busy = tdc->busy;
 734         tegra_dma_stop(tdc);
 735
 736         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
 737                 sgreq = list_first_entry(&tdc->pending_sg_req,
 738                                         typeof(*sgreq), node);
 739                 sgreq->dma_desc->bytes_transferred +=
 740                                 get_current_xferred_count(tdc, sgreq, status);
 741         }
 742         tegra_dma_resume(tdc);
 743
 744 skip_dma_stop:
 745         tegra_dma_abort_all(tdc);
 746
 747         while (!list_empty(&tdc->cb_desc)) {
 748                 dma_desc  = list_first_entry(&tdc->cb_desc,
 749                                         typeof(*dma_desc), cb_node);
 750                 list_del(&dma_desc->cb_node);
 751                 dma_desc->cb_count = 0;
 752         }
 753         spin_unlock_irqrestore(&tdc->lock, flags);
 754 }
 755
 756 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
 757         dma_cookie_t cookie, struct dma_tx_state *txstate)
 758 {
 759         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 760         struct tegra_dma_desc *dma_desc;
 761         struct tegra_dma_sg_req *sg_req;
 762         enum dma_status ret;
 763         unsigned long flags;
 764         unsigned int residual;
 765
 766         spin_lock_irqsave(&tdc->lock, flags);
 767
 768         ret = dma_cookie_status(dc, cookie, txstate);
 769         if (ret == DMA_SUCCESS) {
 770                 dma_set_residue(txstate, 0);
 771                 spin_unlock_irqrestore(&tdc->lock, flags);
 772                 return ret;
 773         }
 774
 775         /* Check on wait_ack desc status */
 776         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 777                 if (dma_desc->txd.cookie == cookie) {
 778                         residual =  dma_desc->bytes_requested -
 779                                         (dma_desc->bytes_transferred %
 780                                                 dma_desc->bytes_requested);
 781                         dma_set_residue(txstate, residual);
 782                         ret = dma_desc->dma_status;
 783                         spin_unlock_irqrestore(&tdc->lock, flags);
 784                         return ret;
 785                 }
 786         }
 787
 788         /* Check in pending list */
 789         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
 790                 dma_desc = sg_req->dma_desc;
 791                 if (dma_desc->txd.cookie == cookie) {
 792                         residual =  dma_desc->bytes_requested -
 793                                         (dma_desc->bytes_transferred %
 794                                                 dma_desc->bytes_requested);
 795                         dma_set_residue(txstate, residual);
 796                         ret = dma_desc->dma_status;
 797                         spin_unlock_irqrestore(&tdc->lock, flags);
 798                         return ret;
 799                 }
 800         }
 801
 802         dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
 803         spin_unlock_irqrestore(&tdc->lock, flags);
 804         return ret;
 805 }
 806
 807 static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
 808                         unsigned long arg)
 809 {
 810         switch (cmd) {
 811         case DMA_SLAVE_CONFIG:
 812                 return tegra_dma_slave_config(dc,
 813                                 (struct dma_slave_config *)arg);
 814
 815         case DMA_TERMINATE_ALL:
 816                 tegra_dma_terminate_all(dc);
 817                 return 0;
 818
 819         default:
 820                 break;
 821         }
 822
 823         return -ENXIO;
 824 }
 825
 826 static inline int get_bus_width(struct tegra_dma_channel *tdc,
 827                 enum dma_slave_buswidth slave_bw)
 828 {
 829         switch (slave_bw) {
 830         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 831                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
 832         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 833                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 834         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 835                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 836         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 837                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
 838         default:
 839                 dev_warn(tdc2dev(tdc),
 840                         "slave bw is not supported, using 32bits\n");
 841                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 842         }
 843 }
 844
 845 static inline int get_burst_size(struct tegra_dma_channel *tdc,
 846         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
 847 {
 848         int burst_byte;
 849         int burst_ahb_width;
 850
 851         /*
 852          * burst_size from client is in terms of the bus_width.
 853          * convert them into AHB memory width which is 4 byte.
 854          */
 855         burst_byte = burst_size * slave_bw;
 856         burst_ahb_width = burst_byte / 4;
 857
 858         /* If burst size is 0 then calculate the burst size based on length */
 859         if (!burst_ahb_width) {
 860                 if (len & 0xF)
 861                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
 862                 else if ((len >> 4) & 0x1)
 863                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
 864                 else
 865                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
 866         }
 867         if (burst_ahb_width < 4)
 868                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
 869         else if (burst_ahb_width < 8)
 870                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
 871         else
 872                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
 873 }
 874
 875 static int get_transfer_param(struct tegra_dma_channel *tdc,
 876         enum dma_transfer_direction direction, unsigned long *apb_addr,
 877         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
 878         enum dma_slave_buswidth *slave_bw)
 879 {
 880
 881         switch (direction) {
 882         case DMA_MEM_TO_DEV:
 883                 *apb_addr = tdc->dma_sconfig.dst_addr;
 884                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
 885                 *burst_size = tdc->dma_sconfig.dst_maxburst;
 886                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
 887                 *csr = TEGRA_APBDMA_CSR_DIR;
 888                 return 0;
 889
 890         case DMA_DEV_TO_MEM:
 891                 *apb_addr = tdc->dma_sconfig.src_addr;
 892                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
 893                 *burst_size = tdc->dma_sconfig.src_maxburst;
 894                 *slave_bw = tdc->dma_sconfig.src_addr_width;
 895                 *csr = 0;
 896                 return 0;
 897
 898         default:
 899                 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
 900                 return -EINVAL;
 901         }
 902         return -EINVAL;
 903 }
 904
 905 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 906         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
 907         enum dma_transfer_direction direction, unsigned long flags,
 908         void *context)
 909 {
 910         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 911         struct tegra_dma_desc *dma_desc;
 912         unsigned int        i;
 913         struct scatterlist      *sg;
 914         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
 915         struct list_head req_list;
 916         struct tegra_dma_sg_req  *sg_req = NULL;
 917         u32 burst_size;
 918         enum dma_slave_buswidth slave_bw;
 919         int ret;
 920
 921         if (!tdc->config_init) {
 922                 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
 923                 return NULL;
 924         }
 925         if (sg_len < 1) {
 926                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
 927                 return NULL;
 928         }
 929
 930         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
 931                                 &burst_size, &slave_bw);
 932         if (ret < 0)
 933                 return NULL;
 934
 935         INIT_LIST_HEAD(&req_list);
 936
 937         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
 938         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
 939                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 940         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 941
 942         csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
 943         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 944         if (flags & DMA_PREP_INTERRUPT)
 945                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
 946
 947         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 948
 949         dma_desc = tegra_dma_desc_get(tdc);
 950         if (!dma_desc) {
 951                 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
 952                 return NULL;
 953         }
 954         INIT_LIST_HEAD(&dma_desc->tx_list);
 955         INIT_LIST_HEAD(&dma_desc->cb_node);
 956         dma_desc->cb_count = 0;
 957         dma_desc->bytes_requested = 0;
 958         dma_desc->bytes_transferred = 0;
 959         dma_desc->dma_status = DMA_IN_PROGRESS;
 960
 961         /* Make transfer requests */
 962         for_each_sg(sgl, sg, sg_len, i) {
 963                 u32 len, mem;
 964
 965                 mem = sg_dma_address(sg);
 966                 len = sg_dma_len(sg);
 967
 968                 if ((len & 3) || (mem & 3) ||
 969                                 (len > tdc->tdma->chip_data->max_dma_count)) {
 970                         dev_err(tdc2dev(tdc),
 971                                 "Dma length/memory address is not supported\n");
 972                         tegra_dma_desc_put(tdc, dma_desc);
 973                         return NULL;
 974                 }
 975
 976                 sg_req = tegra_dma_sg_req_get(tdc);
 977                 if (!sg_req) {
 978                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
 979                         tegra_dma_desc_put(tdc, dma_desc);
 980                         return NULL;
 981                 }
 982
 983                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
 984                 dma_desc->bytes_requested += len;
 985
 986                 sg_req->ch_regs.apb_ptr = apb_ptr;
 987                 sg_req->ch_regs.ahb_ptr = mem;
 988                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
 989                 sg_req->ch_regs.apb_seq = apb_seq;
 990                 sg_req->ch_regs.ahb_seq = ahb_seq;
 991                 sg_req->configured = false;
 992                 sg_req->last_sg = false;
 993                 sg_req->dma_desc = dma_desc;
 994                 sg_req->req_len = len;
 995
 996                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
 997         }
 998         sg_req->last_sg = true;
 999         if (flags & DMA_CTRL_ACK)
1000                 dma_desc->txd.flags = DMA_CTRL_ACK;
1001
1002         /*
1003          * Make sure that mode should not be conflicting with currently
1004          * configured mode.
1005          */
1006         if (!tdc->isr_handler) {
1007                 tdc->isr_handler = handle_once_dma_done;
1008                 tdc->cyclic = false;
1009         } else {
1010                 if (tdc->cyclic) {
1011                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1012                         tegra_dma_desc_put(tdc, dma_desc);
1013                         return NULL;
1014                 }
1015         }
1016
1017         return &dma_desc->txd;
1018 }
1019
1020 struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1021         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1022         size_t period_len, enum dma_transfer_direction direction,
1023         unsigned long flags, void *context)
1024 {
1025         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1026         struct tegra_dma_desc *dma_desc = NULL;
1027         struct tegra_dma_sg_req  *sg_req = NULL;
1028         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1029         int len;
1030         size_t remain_len;
1031         dma_addr_t mem = buf_addr;
1032         u32 burst_size;
1033         enum dma_slave_buswidth slave_bw;
1034         int ret;
1035
1036         if (!buf_len || !period_len) {
1037                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1038                 return NULL;
1039         }
1040
1041         if (!tdc->config_init) {
1042                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1043                 return NULL;
1044         }
1045
1046         /*
1047          * We allow to take more number of requests till DMA is
1048          * not started. The driver will loop over all requests.
1049          * Once DMA is started then new requests can be queued only after
1050          * terminating the DMA.
1051          */
1052         if (tdc->busy) {
1053                 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1054                 return NULL;
1055         }
1056
1057         /*
1058          * We only support cycle transfer when buf_len is multiple of
1059          * period_len.
1060          */
1061         if (buf_len % period_len) {
1062                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1063                 return NULL;
1064         }
1065
1066         len = period_len;
1067         if ((len & 3) || (buf_addr & 3) ||
1068                         (len > tdc->tdma->chip_data->max_dma_count)) {
1069                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1070                 return NULL;
1071         }
1072
1073         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1074                                 &burst_size, &slave_bw);
1075         if (ret < 0)
1076                 return NULL;
1077
1078
1079         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1080         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1081                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1082         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1083
1084         csr |= TEGRA_APBDMA_CSR_FLOW | TEGRA_APBDMA_CSR_IE_EOC;
1085         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1086
1087         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1088
1089         dma_desc = tegra_dma_desc_get(tdc);
1090         if (!dma_desc) {
1091                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1092                 return NULL;
1093         }
1094
1095         INIT_LIST_HEAD(&dma_desc->tx_list);
1096         INIT_LIST_HEAD(&dma_desc->cb_node);
1097         dma_desc->cb_count = 0;
1098
1099         dma_desc->bytes_transferred = 0;
1100         dma_desc->bytes_requested = buf_len;
1101         remain_len = buf_len;
1102
1103         /* Split transfer equal to period size */
1104         while (remain_len) {
1105                 sg_req = tegra_dma_sg_req_get(tdc);
1106                 if (!sg_req) {
1107                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1108                         tegra_dma_desc_put(tdc, dma_desc);
1109                         return NULL;
1110                 }
1111
1112                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1113                 sg_req->ch_regs.apb_ptr = apb_ptr;
1114                 sg_req->ch_regs.ahb_ptr = mem;
1115                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1116                 sg_req->ch_regs.apb_seq = apb_seq;
1117                 sg_req->ch_regs.ahb_seq = ahb_seq;
1118                 sg_req->configured = false;
1119                 sg_req->half_done = false;
1120                 sg_req->last_sg = false;
1121                 sg_req->dma_desc = dma_desc;
1122                 sg_req->req_len = len;
1123
1124                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1125                 remain_len -= len;
1126                 mem += len;
1127         }
1128         sg_req->last_sg = true;
1129         dma_desc->txd.flags = 0;
1130
1131         /*
1132          * Make sure that mode should not be conflicting with currently
1133          * configured mode.
1134          */
1135         if (!tdc->isr_handler) {
1136                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1137                 tdc->cyclic = true;
1138         } else {
1139                 if (!tdc->cyclic) {
1140                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1141                         tegra_dma_desc_put(tdc, dma_desc);
1142                         return NULL;
1143                 }
1144         }
1145
1146         return &dma_desc->txd;
1147 }
1148
1149 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1150 {
1151         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1152         struct tegra_dma *tdma = tdc->tdma;
1153         int ret;
1154
1155         dma_cookie_init(&tdc->dma_chan);
1156         tdc->config_init = false;
1157         ret = clk_prepare_enable(tdma->dma_clk);
1158         if (ret < 0)
1159                 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1160         return ret;
1161 }
1162
1163 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1164 {
1165         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1166         struct tegra_dma *tdma = tdc->tdma;
1167
1168         struct tegra_dma_desc *dma_desc;
1169         struct tegra_dma_sg_req *sg_req;
1170         struct list_head dma_desc_list;
1171         struct list_head sg_req_list;
1172         unsigned long flags;
1173
1174         INIT_LIST_HEAD(&dma_desc_list);
1175         INIT_LIST_HEAD(&sg_req_list);
1176
1177         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1178
1179         if (tdc->busy)
1180                 tegra_dma_terminate_all(dc);
1181
1182         spin_lock_irqsave(&tdc->lock, flags);
1183         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1184         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1185         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1186         INIT_LIST_HEAD(&tdc->cb_desc);
1187         tdc->config_init = false;
1188         spin_unlock_irqrestore(&tdc->lock, flags);
1189
1190         while (!list_empty(&dma_desc_list)) {
1191                 dma_desc = list_first_entry(&dma_desc_list,
1192                                         typeof(*dma_desc), node);
1193                 list_del(&dma_desc->node);
1194                 kfree(dma_desc);
1195         }
1196
1197         while (!list_empty(&sg_req_list)) {
1198                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1199                 list_del(&sg_req->node);
1200                 kfree(sg_req);
1201         }
1202         clk_disable_unprepare(tdma->dma_clk);
1203 }
1204
1205 /* Tegra20 specific DMA controller information */
1206 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1207         .nr_channels            = 16,
1208         .max_dma_count          = 1024UL * 64,
1209         .support_channel_pause  = false,
1210 };
1211
1212 #if defined(CONFIG_OF)
1213 /* Tegra30 specific DMA controller information */
1214 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1215         .nr_channels            = 32,
1216         .max_dma_count          = 1024UL * 64,
1217         .support_channel_pause  = false,
1218 };
1219
1220 static const struct of_device_id tegra_dma_of_match[] __devinitconst = {
1221         {
1222                 .compatible = "nvidia,tegra30-apbdma",
1223                 .data = &tegra30_dma_chip_data,
1224         }, {
1225                 .compatible = "nvidia,tegra20-apbdma",
1226                 .data = &tegra20_dma_chip_data,
1227         }, {
1228         },
1229 };
1230 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1231 #endif
1232
1233 static int tegra_dma_probe(struct platform_device *pdev)
1234 {
1235         struct resource *res;
1236         struct tegra_dma *tdma;
1237         int ret;
1238         int i;
1239         const struct tegra_dma_chip_data *cdata = NULL;
1240
1241         if (pdev->dev.of_node) {
1242                 const struct of_device_id *match;
1243                 match = of_match_device(of_match_ptr(tegra_dma_of_match),
1244                                         &pdev->dev);
1245                 if (!match) {
1246                         dev_err(&pdev->dev, "Error: No device match found\n");
1247                         return -ENODEV;
1248                 }
1249                 cdata = match->data;
1250         } else {
1251                 /* If no device tree then fallback to tegra20 */
1252                 cdata = &tegra20_dma_chip_data;
1253         }
1254
1255         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1256                         sizeof(struct tegra_dma_channel), GFP_KERNEL);
1257         if (!tdma) {
1258                 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1259                 return -ENOMEM;
1260         }
1261
1262         tdma->dev = &pdev->dev;
1263         tdma->chip_data = cdata;
1264         platform_set_drvdata(pdev, tdma);
1265
1266         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267         if (!res) {
1268                 dev_err(&pdev->dev, "No mem resource for DMA\n");
1269                 return -EINVAL;
1270         }
1271
1272         tdma->base_addr = devm_request_and_ioremap(&pdev->dev, res);
1273         if (!tdma->base_addr) {
1274                 dev_err(&pdev->dev,
1275                         "Cannot request memregion/iomap dma address\n");
1276                 return -EADDRNOTAVAIL;
1277         }
1278
1279         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1280         if (IS_ERR(tdma->dma_clk)) {
1281                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1282                 return PTR_ERR(tdma->dma_clk);
1283         }
1284
1285         spin_lock_init(&tdma->global_lock);
1286
1287         pm_runtime_enable(&pdev->dev);
1288         if (!pm_runtime_enabled(&pdev->dev)) {
1289                 ret = tegra_dma_runtime_resume(&pdev->dev);
1290                 if (ret) {
1291                         dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1292                                 ret);
1293                         goto err_pm_disable;
1294                 }
1295         }
1296
1297         /* Enable clock before accessing registers */
1298         ret = clk_prepare_enable(tdma->dma_clk);
1299         if (ret < 0) {
1300                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1301                 goto err_pm_disable;
1302         }
1303
1304         /* Reset DMA controller */
1305         tegra_periph_reset_assert(tdma->dma_clk);
1306         udelay(2);
1307         tegra_periph_reset_deassert(tdma->dma_clk);
1308
1309         /* Enable global DMA registers */
1310         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1311         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1312         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1313
1314         clk_disable_unprepare(tdma->dma_clk);
1315
1316         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1317         for (i = 0; i < cdata->nr_channels; i++) {
1318                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1319
1320                 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1321                                         i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1322
1323                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1324                 if (!res) {
1325                         ret = -EINVAL;
1326                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1327                         goto err_irq;
1328                 }
1329                 tdc->irq = res->start;
1330                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1331                 ret = devm_request_irq(&pdev->dev, tdc->irq,
1332                                 tegra_dma_isr, 0, tdc->name, tdc);
1333                 if (ret) {
1334                         dev_err(&pdev->dev,
1335                                 "request_irq failed with err %d channel %d\n",
1336                                 i, ret);
1337                         goto err_irq;
1338                 }
1339
1340                 tdc->dma_chan.device = &tdma->dma_dev;
1341                 dma_cookie_init(&tdc->dma_chan);
1342                 list_add_tail(&tdc->dma_chan.device_node,
1343                                 &tdma->dma_dev.channels);
1344                 tdc->tdma = tdma;
1345                 tdc->id = i;
1346
1347                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1348                                 (unsigned long)tdc);
1349                 spin_lock_init(&tdc->lock);
1350
1351                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1352                 INIT_LIST_HEAD(&tdc->free_sg_req);
1353                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1354                 INIT_LIST_HEAD(&tdc->cb_desc);
1355         }
1356
1357         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1358         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1359         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1360
1361         tdma->dma_dev.dev = &pdev->dev;
1362         tdma->dma_dev.device_alloc_chan_resources =
1363                                         tegra_dma_alloc_chan_resources;
1364         tdma->dma_dev.device_free_chan_resources =
1365                                         tegra_dma_free_chan_resources;
1366         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1367         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1368         tdma->dma_dev.device_control = tegra_dma_device_control;
1369         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1370         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1371
1372         ret = dma_async_device_register(&tdma->dma_dev);
1373         if (ret < 0) {
1374                 dev_err(&pdev->dev,
1375                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1376                 goto err_irq;
1377         }
1378
1379         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1380                         cdata->nr_channels);
1381         return 0;
1382
1383 err_irq:
1384         while (--i >= 0) {
1385                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1386                 tasklet_kill(&tdc->tasklet);
1387         }
1388
1389 err_pm_disable:
1390         pm_runtime_disable(&pdev->dev);
1391         if (!pm_runtime_status_suspended(&pdev->dev))
1392                 tegra_dma_runtime_suspend(&pdev->dev);
1393         return ret;
1394 }
1395
1396 static int __devexit tegra_dma_remove(struct platform_device *pdev)
1397 {
1398         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1399         int i;
1400         struct tegra_dma_channel *tdc;
1401
1402         dma_async_device_unregister(&tdma->dma_dev);
1403
1404         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1405                 tdc = &tdma->channels[i];
1406                 tasklet_kill(&tdc->tasklet);
1407         }
1408
1409         pm_runtime_disable(&pdev->dev);
1410         if (!pm_runtime_status_suspended(&pdev->dev))
1411                 tegra_dma_runtime_suspend(&pdev->dev);
1412
1413         return 0;
1414 }
1415
1416 static int tegra_dma_runtime_suspend(struct device *dev)
1417 {
1418         struct platform_device *pdev = to_platform_device(dev);
1419         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1420
1421         clk_disable_unprepare(tdma->dma_clk);
1422         return 0;
1423 }
1424
1425 static int tegra_dma_runtime_resume(struct device *dev)
1426 {
1427         struct platform_device *pdev = to_platform_device(dev);
1428         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1429         int ret;
1430
1431         ret = clk_prepare_enable(tdma->dma_clk);
1432         if (ret < 0) {
1433                 dev_err(dev, "clk_enable failed: %d\n", ret);
1434                 return ret;
1435         }
1436         return 0;
1437 }
1438
1439 static const struct dev_pm_ops tegra_dma_dev_pm_ops __devinitconst = {
1440 #ifdef CONFIG_PM_RUNTIME
1441         .runtime_suspend = tegra_dma_runtime_suspend,
1442         .runtime_resume = tegra_dma_runtime_resume,
1443 #endif
1444 };
1445
1446 static struct platform_driver tegra_dmac_driver = {
1447         .driver = {
1448                 .name   = "tegra-apbdma",
1449                 .owner = THIS_MODULE,
1450                 .pm     = &tegra_dma_dev_pm_ops,
1451                 .of_match_table = of_match_ptr(tegra_dma_of_match),
1452         },
1453         .probe          = tegra_dma_probe,
1454         .remove         = tegra_dma_remove,
1455 };
1456
1457 module_platform_driver(tegra_dmac_driver);
1458
1459 MODULE_ALIAS("platform:tegra20-apbdma");
1460 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1461 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1462 MODULE_LICENSE("GPL v2");