drivers/dma/tegra20-apb-dma.c

   1 /*
   2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/slab.h>
  34
  35 #include <mach/clk.h>
  36 #include "dmaengine.h"
  37
  38 #define TEGRA_APBDMA_GENERAL                    0x0
  39 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
  40
  41 #define TEGRA_APBDMA_CONTROL                    0x010
  42 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
  43 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
  44
  45 /* CSR register */
  46 #define TEGRA_APBDMA_CHAN_CSR                   0x00
  47 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
  48 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
  49 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
  50 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
  51 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
  52 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
  53 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
  54 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
  55
  56 /* STATUS register */
  57 #define TEGRA_APBDMA_CHAN_STATUS                0x004
  58 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
  59 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
  60 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
  61 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
  62 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
  63 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
  64
  65 #define TEGRA_APBDMA_CHAN_CSRE                  0x00C
  66 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE            (1 << 31)
  67
  68 /* AHB memory address */
  69 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
  70
  71 /* AHB sequence register */
  72 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
  73 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
  74 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
  75 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
  76 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
  77 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
  78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
  79 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
  80 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
  81 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
  82 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
  83 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
  84 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
  85 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
  86
  87 /* APB address */
  88 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
  89
  90 /* APB sequence register */
  91 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
  92 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
  93 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
  94 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
  95 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
  96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
  97 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
  98 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
  99
 100 /*
 101  * If any burst is in flight and DMA paused then this is the time to complete
 102  * on-flight burst and update DMA status register.
 103  */
 104 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
 105
 106 /* Channel base address offset from APBDMA base address */
 107 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
 108
 109 /* DMA channel register space size */
 110 #define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE      0x20
 111
 112 struct tegra_dma;
 113
 114 /*
 115  * tegra_dma_chip_data Tegra chip specific DMA data
 116  * @nr_channels: Number of channels available in the controller.
 117  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 118  * @support_channel_pause: Support channel wise pause of dma.
 119  */
 120 struct tegra_dma_chip_data {
 121         int nr_channels;
 122         int max_dma_count;
 123         bool support_channel_pause;
 124 };
 125
 126 /* DMA channel registers */
 127 struct tegra_dma_channel_regs {
 128         unsigned long   csr;
 129         unsigned long   ahb_ptr;
 130         unsigned long   apb_ptr;
 131         unsigned long   ahb_seq;
 132         unsigned long   apb_seq;
 133 };
 134
 135 /*
 136  * tegra_dma_sg_req: Dma request details to configure hardware. This
 137  * contains the details for one transfer to configure DMA hw.
 138  * The client's request for data transfer can be broken into multiple
 139  * sub-transfer as per requester details and hw support.
 140  * This sub transfer get added in the list of transfer and point to Tegra
 141  * DMA descriptor which manages the transfer details.
 142  */
 143 struct tegra_dma_sg_req {
 144         struct tegra_dma_channel_regs   ch_regs;
 145         int                             req_len;
 146         bool                            configured;
 147         bool                            last_sg;
 148         bool                            half_done;
 149         struct list_head                node;
 150         struct tegra_dma_desc           *dma_desc;
 151 };
 152
 153 /*
 154  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 155  * This descriptor keep track of transfer status, callbacks and request
 156  * counts etc.
 157  */
 158 struct tegra_dma_desc {
 159         struct dma_async_tx_descriptor  txd;
 160         int                             bytes_requested;
 161         int                             bytes_transferred;
 162         enum dma_status                 dma_status;
 163         struct list_head                node;
 164         struct list_head                tx_list;
 165         struct list_head                cb_node;
 166         int                             cb_count;
 167 };
 168
 169 struct tegra_dma_channel;
 170
 171 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
 172                                 bool to_terminate);
 173
 174 /* tegra_dma_channel: Channel specific information */
 175 struct tegra_dma_channel {
 176         struct dma_chan         dma_chan;
 177         char                    name[30];
 178         bool                    config_init;
 179         int                     id;
 180         int                     irq;
 181         unsigned long           chan_base_offset;
 182         spinlock_t              lock;
 183         bool                    busy;
 184         struct tegra_dma        *tdma;
 185         bool                    cyclic;
 186
 187         /* Different lists for managing the requests */
 188         struct list_head        free_sg_req;
 189         struct list_head        pending_sg_req;
 190         struct list_head        free_dma_desc;
 191         struct list_head        cb_desc;
 192
 193         /* ISR handler and tasklet for bottom half of isr handling */
 194         dma_isr_handler         isr_handler;
 195         struct tasklet_struct   tasklet;
 196         dma_async_tx_callback   callback;
 197         void                    *callback_param;
 198
 199         /* Channel-slave specific configuration */
 200         struct dma_slave_config dma_sconfig;
 201 };
 202
 203 /* tegra_dma: Tegra DMA specific information */
 204 struct tegra_dma {
 205         struct dma_device               dma_dev;
 206         struct device                   *dev;
 207         struct clk                      *dma_clk;
 208         spinlock_t                      global_lock;
 209         void __iomem                    *base_addr;
 210         const struct tegra_dma_chip_data *chip_data;
 211
 212         /* Some register need to be cache before suspend */
 213         u32                             reg_gen;
 214
 215         /* Last member of the structure */
 216         struct tegra_dma_channel channels[0];
 217 };
 218
 219 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
 220 {
 221         writel(val, tdma->base_addr + reg);
 222 }
 223
 224 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
 225 {
 226         return readl(tdma->base_addr + reg);
 227 }
 228
 229 static inline void tdc_write(struct tegra_dma_channel *tdc,
 230                 u32 reg, u32 val)
 231 {
 232         writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 233 }
 234
 235 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
 236 {
 237         return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 238 }
 239
 240 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
 241 {
 242         return container_of(dc, struct tegra_dma_channel, dma_chan);
 243 }
 244
 245 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
 246                 struct dma_async_tx_descriptor *td)
 247 {
 248         return container_of(td, struct tegra_dma_desc, txd);
 249 }
 250
 251 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
 252 {
 253         return &tdc->dma_chan.dev->device;
 254 }
 255
 256 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
 257 static int tegra_dma_runtime_suspend(struct device *dev);
 258 static int tegra_dma_runtime_resume(struct device *dev);
 259
 260 /* Get DMA desc from free list, if not there then allocate it.  */
 261 static struct tegra_dma_desc *tegra_dma_desc_get(
 262                 struct tegra_dma_channel *tdc)
 263 {
 264         struct tegra_dma_desc *dma_desc;
 265         unsigned long flags;
 266
 267         spin_lock_irqsave(&tdc->lock, flags);
 268
 269         /* Do not allocate if desc are waiting for ack */
 270         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 271                 if (async_tx_test_ack(&dma_desc->txd)) {
 272                         list_del(&dma_desc->node);
 273                         spin_unlock_irqrestore(&tdc->lock, flags);
 274                         return dma_desc;
 275                 }
 276         }
 277
 278         spin_unlock_irqrestore(&tdc->lock, flags);
 279
 280         /* Allocate DMA desc */
 281         dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
 282         if (!dma_desc) {
 283                 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
 284                 return NULL;
 285         }
 286
 287         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 288         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
 289         dma_desc->txd.flags = 0;
 290         return dma_desc;
 291 }
 292
 293 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
 294                 struct tegra_dma_desc *dma_desc)
 295 {
 296         unsigned long flags;
 297
 298         spin_lock_irqsave(&tdc->lock, flags);
 299         if (!list_empty(&dma_desc->tx_list))
 300                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
 301         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 302         spin_unlock_irqrestore(&tdc->lock, flags);
 303 }
 304
 305 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
 306                 struct tegra_dma_channel *tdc)
 307 {
 308         struct tegra_dma_sg_req *sg_req = NULL;
 309         unsigned long flags;
 310
 311         spin_lock_irqsave(&tdc->lock, flags);
 312         if (!list_empty(&tdc->free_sg_req)) {
 313                 sg_req = list_first_entry(&tdc->free_sg_req,
 314                                         typeof(*sg_req), node);
 315                 list_del(&sg_req->node);
 316                 spin_unlock_irqrestore(&tdc->lock, flags);
 317                 return sg_req;
 318         }
 319         spin_unlock_irqrestore(&tdc->lock, flags);
 320
 321         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
 322         if (!sg_req)
 323                 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
 324         return sg_req;
 325 }
 326
 327 static int tegra_dma_slave_config(struct dma_chan *dc,
 328                 struct dma_slave_config *sconfig)
 329 {
 330         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 331
 332         if (!list_empty(&tdc->pending_sg_req)) {
 333                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
 334                 return -EBUSY;
 335         }
 336
 337         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
 338         tdc->config_init = true;
 339         return 0;
 340 }
 341
 342 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
 343         bool wait_for_burst_complete)
 344 {
 345         struct tegra_dma *tdma = tdc->tdma;
 346
 347         spin_lock(&tdma->global_lock);
 348         tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
 349         if (wait_for_burst_complete)
 350                 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 351 }
 352
 353 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
 354 {
 355         struct tegra_dma *tdma = tdc->tdma;
 356
 357         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
 358         spin_unlock(&tdma->global_lock);
 359 }
 360
 361 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
 362         bool wait_for_burst_complete)
 363 {
 364         struct tegra_dma *tdma = tdc->tdma;
 365
 366         if (tdma->chip_data->support_channel_pause) {
 367                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
 368                                 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
 369                 if (wait_for_burst_complete)
 370                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 371         } else {
 372                 tegra_dma_global_pause(tdc, wait_for_burst_complete);
 373         }
 374 }
 375
 376 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
 377 {
 378         struct tegra_dma *tdma = tdc->tdma;
 379
 380         if (tdma->chip_data->support_channel_pause) {
 381                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
 382         } else {
 383                 tegra_dma_global_resume(tdc);
 384         }
 385 }
 386
 387 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
 388 {
 389         u32 csr;
 390         u32 status;
 391
 392         /* Disable interrupts */
 393         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
 394         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
 395         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 396
 397         /* Disable DMA */
 398         csr &= ~TEGRA_APBDMA_CSR_ENB;
 399         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 400
 401         /* Clear interrupt status if it is there */
 402         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 403         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 404                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
 405                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 406         }
 407         tdc->busy = false;
 408 }
 409
 410 static void tegra_dma_start(struct tegra_dma_channel *tdc,
 411                 struct tegra_dma_sg_req *sg_req)
 412 {
 413         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
 414
 415         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
 416         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
 417         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
 418         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
 419         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
 420
 421         /* Start DMA */
 422         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 423                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
 424 }
 425
 426 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
 427                 struct tegra_dma_sg_req *nsg_req)
 428 {
 429         unsigned long status;
 430
 431         /*
 432          * The DMA controller reloads the new configuration for next transfer
 433          * after last burst of current transfer completes.
 434          * If there is no IEC status then this makes sure that last burst
 435          * has not be completed. There may be case that last burst is on
 436          * flight and so it can complete but because DMA is paused, it
 437          * will not generates interrupt as well as not reload the new
 438          * configuration.
 439          * If there is already IEC status then interrupt handler need to
 440          * load new configuration.
 441          */
 442         tegra_dma_pause(tdc, false);
 443         status  = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 444
 445         /*
 446          * If interrupt is pending then do nothing as the ISR will handle
 447          * the programing for new request.
 448          */
 449         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 450                 dev_err(tdc2dev(tdc),
 451                         "Skipping new configuration as interrupt is pending\n");
 452                 tegra_dma_resume(tdc);
 453                 return;
 454         }
 455
 456         /* Safe to program new configuration */
 457         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
 458         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
 459         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 460                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
 461         nsg_req->configured = true;
 462
 463         tegra_dma_resume(tdc);
 464 }
 465
 466 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
 467 {
 468         struct tegra_dma_sg_req *sg_req;
 469
 470         if (list_empty(&tdc->pending_sg_req))
 471                 return;
 472
 473         sg_req = list_first_entry(&tdc->pending_sg_req,
 474                                         typeof(*sg_req), node);
 475         tegra_dma_start(tdc, sg_req);
 476         sg_req->configured = true;
 477         tdc->busy = true;
 478 }
 479
 480 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
 481 {
 482         struct tegra_dma_sg_req *hsgreq;
 483         struct tegra_dma_sg_req *hnsgreq;
 484
 485         if (list_empty(&tdc->pending_sg_req))
 486                 return;
 487
 488         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 489         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
 490                 hnsgreq = list_first_entry(&hsgreq->node,
 491                                         typeof(*hnsgreq), node);
 492                 tegra_dma_configure_for_next(tdc, hnsgreq);
 493         }
 494 }
 495
 496 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
 497         struct tegra_dma_sg_req *sg_req, unsigned long status)
 498 {
 499         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
 500 }
 501
 502 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
 503 {
 504         struct tegra_dma_sg_req *sgreq;
 505         struct tegra_dma_desc *dma_desc;
 506
 507         while (!list_empty(&tdc->pending_sg_req)) {
 508                 sgreq = list_first_entry(&tdc->pending_sg_req,
 509                                                 typeof(*sgreq), node);
 510                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
 511                 if (sgreq->last_sg) {
 512                         dma_desc = sgreq->dma_desc;
 513                         dma_desc->dma_status = DMA_ERROR;
 514                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 515
 516                         /* Add in cb list if it is not there. */
 517                         if (!dma_desc->cb_count)
 518                                 list_add_tail(&dma_desc->cb_node,
 519                                                         &tdc->cb_desc);
 520                         dma_desc->cb_count++;
 521                 }
 522         }
 523         tdc->isr_handler = NULL;
 524 }
 525
 526 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
 527                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
 528 {
 529         struct tegra_dma_sg_req *hsgreq = NULL;
 530
 531         if (list_empty(&tdc->pending_sg_req)) {
 532                 dev_err(tdc2dev(tdc), "Dma is running without req\n");
 533                 tegra_dma_stop(tdc);
 534                 return false;
 535         }
 536
 537         /*
 538          * Check that head req on list should be in flight.
 539          * If it is not in flight then abort transfer as
 540          * looping of transfer can not continue.
 541          */
 542         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 543         if (!hsgreq->configured) {
 544                 tegra_dma_stop(tdc);
 545                 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
 546                 tegra_dma_abort_all(tdc);
 547                 return false;
 548         }
 549
 550         /* Configure next request */
 551         if (!to_terminate)
 552                 tdc_configure_next_head_desc(tdc);
 553         return true;
 554 }
 555
 556 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
 557         bool to_terminate)
 558 {
 559         struct tegra_dma_sg_req *sgreq;
 560         struct tegra_dma_desc *dma_desc;
 561
 562         tdc->busy = false;
 563         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 564         dma_desc = sgreq->dma_desc;
 565         dma_desc->bytes_transferred += sgreq->req_len;
 566
 567         list_del(&sgreq->node);
 568         if (sgreq->last_sg) {
 569                 dma_desc->dma_status = DMA_SUCCESS;
 570                 dma_cookie_complete(&dma_desc->txd);
 571                 if (!dma_desc->cb_count)
 572                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 573                 dma_desc->cb_count++;
 574                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 575         }
 576         list_add_tail(&sgreq->node, &tdc->free_sg_req);
 577
 578         /* Do not start DMA if it is going to be terminate */
 579         if (to_terminate || list_empty(&tdc->pending_sg_req))
 580                 return;
 581
 582         tdc_start_head_req(tdc);
 583         return;
 584 }
 585
 586 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
 587                 bool to_terminate)
 588 {
 589         struct tegra_dma_sg_req *sgreq;
 590         struct tegra_dma_desc *dma_desc;
 591         bool st;
 592
 593         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 594         dma_desc = sgreq->dma_desc;
 595         dma_desc->bytes_transferred += sgreq->req_len;
 596
 597         /* Callback need to be call */
 598         if (!dma_desc->cb_count)
 599                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 600         dma_desc->cb_count++;
 601
 602         /* If not last req then put at end of pending list */
 603         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
 604                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
 605                 sgreq->configured = false;
 606                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
 607                 if (!st)
 608                         dma_desc->dma_status = DMA_ERROR;
 609         }
 610         return;
 611 }
 612
 613 static void tegra_dma_tasklet(unsigned long data)
 614 {
 615         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
 616         dma_async_tx_callback callback = NULL;
 617         void *callback_param = NULL;
 618         struct tegra_dma_desc *dma_desc;
 619         unsigned long flags;
 620         int cb_count;
 621
 622         spin_lock_irqsave(&tdc->lock, flags);
 623         while (!list_empty(&tdc->cb_desc)) {
 624                 dma_desc  = list_first_entry(&tdc->cb_desc,
 625                                         typeof(*dma_desc), cb_node);
 626                 list_del(&dma_desc->cb_node);
 627                 callback = dma_desc->txd.callback;
 628                 callback_param = dma_desc->txd.callback_param;
 629                 cb_count = dma_desc->cb_count;
 630                 dma_desc->cb_count = 0;
 631                 spin_unlock_irqrestore(&tdc->lock, flags);
 632                 while (cb_count-- && callback)
 633                         callback(callback_param);
 634                 spin_lock_irqsave(&tdc->lock, flags);
 635         }
 636         spin_unlock_irqrestore(&tdc->lock, flags);
 637 }
 638
 639 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
 640 {
 641         struct tegra_dma_channel *tdc = dev_id;
 642         unsigned long status;
 643         unsigned long flags;
 644
 645         spin_lock_irqsave(&tdc->lock, flags);
 646
 647         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 648         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 649                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 650                 tdc->isr_handler(tdc, false);
 651                 tasklet_schedule(&tdc->tasklet);
 652                 spin_unlock_irqrestore(&tdc->lock, flags);
 653                 return IRQ_HANDLED;
 654         }
 655
 656         spin_unlock_irqrestore(&tdc->lock, flags);
 657         dev_info(tdc2dev(tdc),
 658                 "Interrupt already served status 0x%08lx\n", status);
 659         return IRQ_NONE;
 660 }
 661
 662 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 663 {
 664         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 665         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
 666         unsigned long flags;
 667         dma_cookie_t cookie;
 668
 669         spin_lock_irqsave(&tdc->lock, flags);
 670         dma_desc->dma_status = DMA_IN_PROGRESS;
 671         cookie = dma_cookie_assign(&dma_desc->txd);
 672         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
 673         spin_unlock_irqrestore(&tdc->lock, flags);
 674         return cookie;
 675 }
 676
 677 static void tegra_dma_issue_pending(struct dma_chan *dc)
 678 {
 679         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 680         unsigned long flags;
 681
 682         spin_lock_irqsave(&tdc->lock, flags);
 683         if (list_empty(&tdc->pending_sg_req)) {
 684                 dev_err(tdc2dev(tdc), "No DMA request\n");
 685                 goto end;
 686         }
 687         if (!tdc->busy) {
 688                 tdc_start_head_req(tdc);
 689
 690                 /* Continuous single mode: Configure next req */
 691                 if (tdc->cyclic) {
 692                         /*
 693                          * Wait for 1 burst time for configure DMA for
 694                          * next transfer.
 695                          */
 696                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 697                         tdc_configure_next_head_desc(tdc);
 698                 }
 699         }
 700 end:
 701         spin_unlock_irqrestore(&tdc->lock, flags);
 702         return;
 703 }
 704
 705 static void tegra_dma_terminate_all(struct dma_chan *dc)
 706 {
 707         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 708         struct tegra_dma_sg_req *sgreq;
 709         struct tegra_dma_desc *dma_desc;
 710         unsigned long flags;
 711         unsigned long status;
 712         bool was_busy;
 713
 714         spin_lock_irqsave(&tdc->lock, flags);
 715         if (list_empty(&tdc->pending_sg_req)) {
 716                 spin_unlock_irqrestore(&tdc->lock, flags);
 717                 return;
 718         }
 719
 720         if (!tdc->busy)
 721                 goto skip_dma_stop;
 722
 723         /* Pause DMA before checking the queue status */
 724         tegra_dma_pause(tdc, true);
 725
 726         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 727         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 728                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
 729                 tdc->isr_handler(tdc, true);
 730                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 731         }
 732
 733         was_busy = tdc->busy;
 734         tegra_dma_stop(tdc);
 735
 736         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
 737                 sgreq = list_first_entry(&tdc->pending_sg_req,
 738                                         typeof(*sgreq), node);
 739                 sgreq->dma_desc->bytes_transferred +=
 740                                 get_current_xferred_count(tdc, sgreq, status);
 741         }
 742         tegra_dma_resume(tdc);
 743
 744 skip_dma_stop:
 745         tegra_dma_abort_all(tdc);
 746
 747         while (!list_empty(&tdc->cb_desc)) {
 748                 dma_desc  = list_first_entry(&tdc->cb_desc,
 749                                         typeof(*dma_desc), cb_node);
 750                 list_del(&dma_desc->cb_node);
 751                 dma_desc->cb_count = 0;
 752         }
 753         spin_unlock_irqrestore(&tdc->lock, flags);
 754 }
 755
 756 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
 757         dma_cookie_t cookie, struct dma_tx_state *txstate)
 758 {
 759         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 760         struct tegra_dma_desc *dma_desc;
 761         struct tegra_dma_sg_req *sg_req;
 762         enum dma_status ret;
 763         unsigned long flags;
 764         unsigned int residual;
 765
 766         spin_lock_irqsave(&tdc->lock, flags);
 767
 768         ret = dma_cookie_status(dc, cookie, txstate);
 769         if (ret == DMA_SUCCESS) {
 770                 spin_unlock_irqrestore(&tdc->lock, flags);
 771                 return ret;
 772         }
 773
 774         /* Check on wait_ack desc status */
 775         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 776                 if (dma_desc->txd.cookie == cookie) {
 777                         residual =  dma_desc->bytes_requested -
 778                                         (dma_desc->bytes_transferred %
 779                                                 dma_desc->bytes_requested);
 780                         dma_set_residue(txstate, residual);
 781                         ret = dma_desc->dma_status;
 782                         spin_unlock_irqrestore(&tdc->lock, flags);
 783                         return ret;
 784                 }
 785         }
 786
 787         /* Check in pending list */
 788         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
 789                 dma_desc = sg_req->dma_desc;
 790                 if (dma_desc->txd.cookie == cookie) {
 791                         residual =  dma_desc->bytes_requested -
 792                                         (dma_desc->bytes_transferred %
 793                                                 dma_desc->bytes_requested);
 794                         dma_set_residue(txstate, residual);
 795                         ret = dma_desc->dma_status;
 796                         spin_unlock_irqrestore(&tdc->lock, flags);
 797                         return ret;
 798                 }
 799         }
 800
 801         dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
 802         spin_unlock_irqrestore(&tdc->lock, flags);
 803         return ret;
 804 }
 805
 806 static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
 807                         unsigned long arg)
 808 {
 809         switch (cmd) {
 810         case DMA_SLAVE_CONFIG:
 811                 return tegra_dma_slave_config(dc,
 812                                 (struct dma_slave_config *)arg);
 813
 814         case DMA_TERMINATE_ALL:
 815                 tegra_dma_terminate_all(dc);
 816                 return 0;
 817
 818         default:
 819                 break;
 820         }
 821
 822         return -ENXIO;
 823 }
 824
 825 static inline int get_bus_width(struct tegra_dma_channel *tdc,
 826                 enum dma_slave_buswidth slave_bw)
 827 {
 828         switch (slave_bw) {
 829         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 830                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
 831         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 832                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 833         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 834                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 835         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 836                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
 837         default:
 838                 dev_warn(tdc2dev(tdc),
 839                         "slave bw is not supported, using 32bits\n");
 840                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 841         }
 842 }
 843
 844 static inline int get_burst_size(struct tegra_dma_channel *tdc,
 845         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
 846 {
 847         int burst_byte;
 848         int burst_ahb_width;
 849
 850         /*
 851          * burst_size from client is in terms of the bus_width.
 852          * convert them into AHB memory width which is 4 byte.
 853          */
 854         burst_byte = burst_size * slave_bw;
 855         burst_ahb_width = burst_byte / 4;
 856
 857         /* If burst size is 0 then calculate the burst size based on length */
 858         if (!burst_ahb_width) {
 859                 if (len & 0xF)
 860                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
 861                 else if ((len >> 4) & 0x1)
 862                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
 863                 else
 864                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
 865         }
 866         if (burst_ahb_width < 4)
 867                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
 868         else if (burst_ahb_width < 8)
 869                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
 870         else
 871                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
 872 }
 873
 874 static int get_transfer_param(struct tegra_dma_channel *tdc,
 875         enum dma_transfer_direction direction, unsigned long *apb_addr,
 876         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
 877         enum dma_slave_buswidth *slave_bw)
 878 {
 879
 880         switch (direction) {
 881         case DMA_MEM_TO_DEV:
 882                 *apb_addr = tdc->dma_sconfig.dst_addr;
 883                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
 884                 *burst_size = tdc->dma_sconfig.dst_maxburst;
 885                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
 886                 *csr = TEGRA_APBDMA_CSR_DIR;
 887                 return 0;
 888
 889         case DMA_DEV_TO_MEM:
 890                 *apb_addr = tdc->dma_sconfig.src_addr;
 891                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
 892                 *burst_size = tdc->dma_sconfig.src_maxburst;
 893                 *slave_bw = tdc->dma_sconfig.src_addr_width;
 894                 *csr = 0;
 895                 return 0;
 896
 897         default:
 898                 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
 899                 return -EINVAL;
 900         }
 901         return -EINVAL;
 902 }
 903
 904 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 905         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
 906         enum dma_transfer_direction direction, unsigned long flags,
 907         void *context)
 908 {
 909         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 910         struct tegra_dma_desc *dma_desc;
 911         unsigned int        i;
 912         struct scatterlist      *sg;
 913         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
 914         struct list_head req_list;
 915         struct tegra_dma_sg_req  *sg_req = NULL;
 916         u32 burst_size;
 917         enum dma_slave_buswidth slave_bw;
 918         int ret;
 919
 920         if (!tdc->config_init) {
 921                 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
 922                 return NULL;
 923         }
 924         if (sg_len < 1) {
 925                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
 926                 return NULL;
 927         }
 928
 929         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
 930                                 &burst_size, &slave_bw);
 931         if (ret < 0)
 932                 return NULL;
 933
 934         INIT_LIST_HEAD(&req_list);
 935
 936         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
 937         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
 938                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 939         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 940
 941         csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
 942         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 943         if (flags & DMA_PREP_INTERRUPT)
 944                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
 945
 946         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 947
 948         dma_desc = tegra_dma_desc_get(tdc);
 949         if (!dma_desc) {
 950                 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
 951                 return NULL;
 952         }
 953         INIT_LIST_HEAD(&dma_desc->tx_list);
 954         INIT_LIST_HEAD(&dma_desc->cb_node);
 955         dma_desc->cb_count = 0;
 956         dma_desc->bytes_requested = 0;
 957         dma_desc->bytes_transferred = 0;
 958         dma_desc->dma_status = DMA_IN_PROGRESS;
 959
 960         /* Make transfer requests */
 961         for_each_sg(sgl, sg, sg_len, i) {
 962                 u32 len, mem;
 963
 964                 mem = sg_dma_address(sg);
 965                 len = sg_dma_len(sg);
 966
 967                 if ((len & 3) || (mem & 3) ||
 968                                 (len > tdc->tdma->chip_data->max_dma_count)) {
 969                         dev_err(tdc2dev(tdc),
 970                                 "Dma length/memory address is not supported\n");
 971                         tegra_dma_desc_put(tdc, dma_desc);
 972                         return NULL;
 973                 }
 974
 975                 sg_req = tegra_dma_sg_req_get(tdc);
 976                 if (!sg_req) {
 977                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
 978                         tegra_dma_desc_put(tdc, dma_desc);
 979                         return NULL;
 980                 }
 981
 982                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
 983                 dma_desc->bytes_requested += len;
 984
 985                 sg_req->ch_regs.apb_ptr = apb_ptr;
 986                 sg_req->ch_regs.ahb_ptr = mem;
 987                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
 988                 sg_req->ch_regs.apb_seq = apb_seq;
 989                 sg_req->ch_regs.ahb_seq = ahb_seq;
 990                 sg_req->configured = false;
 991                 sg_req->last_sg = false;
 992                 sg_req->dma_desc = dma_desc;
 993                 sg_req->req_len = len;
 994
 995                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
 996         }
 997         sg_req->last_sg = true;
 998         if (flags & DMA_CTRL_ACK)
 999                 dma_desc->txd.flags = DMA_CTRL_ACK;
1000
1001         /*
1002          * Make sure that mode should not be conflicting with currently
1003          * configured mode.
1004          */
1005         if (!tdc->isr_handler) {
1006                 tdc->isr_handler = handle_once_dma_done;
1007                 tdc->cyclic = false;
1008         } else {
1009                 if (tdc->cyclic) {
1010                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1011                         tegra_dma_desc_put(tdc, dma_desc);
1012                         return NULL;
1013                 }
1014         }
1015
1016         return &dma_desc->txd;
1017 }
1018
1019 struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1020         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1021         size_t period_len, enum dma_transfer_direction direction,
1022         unsigned long flags, void *context)
1023 {
1024         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1025         struct tegra_dma_desc *dma_desc = NULL;
1026         struct tegra_dma_sg_req  *sg_req = NULL;
1027         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1028         int len;
1029         size_t remain_len;
1030         dma_addr_t mem = buf_addr;
1031         u32 burst_size;
1032         enum dma_slave_buswidth slave_bw;
1033         int ret;
1034
1035         if (!buf_len || !period_len) {
1036                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1037                 return NULL;
1038         }
1039
1040         if (!tdc->config_init) {
1041                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1042                 return NULL;
1043         }
1044
1045         /*
1046          * We allow to take more number of requests till DMA is
1047          * not started. The driver will loop over all requests.
1048          * Once DMA is started then new requests can be queued only after
1049          * terminating the DMA.
1050          */
1051         if (tdc->busy) {
1052                 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1053                 return NULL;
1054         }
1055
1056         /*
1057          * We only support cycle transfer when buf_len is multiple of
1058          * period_len.
1059          */
1060         if (buf_len % period_len) {
1061                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1062                 return NULL;
1063         }
1064
1065         len = period_len;
1066         if ((len & 3) || (buf_addr & 3) ||
1067                         (len > tdc->tdma->chip_data->max_dma_count)) {
1068                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1069                 return NULL;
1070         }
1071
1072         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1073                                 &burst_size, &slave_bw);
1074         if (ret < 0)
1075                 return NULL;
1076
1077
1078         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1079         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1080                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1081         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1082
1083         csr |= TEGRA_APBDMA_CSR_FLOW | TEGRA_APBDMA_CSR_IE_EOC;
1084         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1085
1086         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1087
1088         dma_desc = tegra_dma_desc_get(tdc);
1089         if (!dma_desc) {
1090                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1091                 return NULL;
1092         }
1093
1094         INIT_LIST_HEAD(&dma_desc->tx_list);
1095         INIT_LIST_HEAD(&dma_desc->cb_node);
1096         dma_desc->cb_count = 0;
1097
1098         dma_desc->bytes_transferred = 0;
1099         dma_desc->bytes_requested = buf_len;
1100         remain_len = buf_len;
1101
1102         /* Split transfer equal to period size */
1103         while (remain_len) {
1104                 sg_req = tegra_dma_sg_req_get(tdc);
1105                 if (!sg_req) {
1106                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1107                         tegra_dma_desc_put(tdc, dma_desc);
1108                         return NULL;
1109                 }
1110
1111                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1112                 sg_req->ch_regs.apb_ptr = apb_ptr;
1113                 sg_req->ch_regs.ahb_ptr = mem;
1114                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1115                 sg_req->ch_regs.apb_seq = apb_seq;
1116                 sg_req->ch_regs.ahb_seq = ahb_seq;
1117                 sg_req->configured = false;
1118                 sg_req->half_done = false;
1119                 sg_req->last_sg = false;
1120                 sg_req->dma_desc = dma_desc;
1121                 sg_req->req_len = len;
1122
1123                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1124                 remain_len -= len;
1125                 mem += len;
1126         }
1127         sg_req->last_sg = true;
1128         dma_desc->txd.flags = 0;
1129
1130         /*
1131          * Make sure that mode should not be conflicting with currently
1132          * configured mode.
1133          */
1134         if (!tdc->isr_handler) {
1135                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1136                 tdc->cyclic = true;
1137         } else {
1138                 if (!tdc->cyclic) {
1139                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1140                         tegra_dma_desc_put(tdc, dma_desc);
1141                         return NULL;
1142                 }
1143         }
1144
1145         return &dma_desc->txd;
1146 }
1147
1148 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1149 {
1150         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1151         struct tegra_dma *tdma = tdc->tdma;
1152         int ret;
1153
1154         dma_cookie_init(&tdc->dma_chan);
1155         tdc->config_init = false;
1156         ret = clk_prepare_enable(tdma->dma_clk);
1157         if (ret < 0)
1158                 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1159         return ret;
1160 }
1161
1162 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1163 {
1164         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1165         struct tegra_dma *tdma = tdc->tdma;
1166
1167         struct tegra_dma_desc *dma_desc;
1168         struct tegra_dma_sg_req *sg_req;
1169         struct list_head dma_desc_list;
1170         struct list_head sg_req_list;
1171         unsigned long flags;
1172
1173         INIT_LIST_HEAD(&dma_desc_list);
1174         INIT_LIST_HEAD(&sg_req_list);
1175
1176         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1177
1178         if (tdc->busy)
1179                 tegra_dma_terminate_all(dc);
1180
1181         spin_lock_irqsave(&tdc->lock, flags);
1182         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1183         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1184         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1185         INIT_LIST_HEAD(&tdc->cb_desc);
1186         tdc->config_init = false;
1187         spin_unlock_irqrestore(&tdc->lock, flags);
1188
1189         while (!list_empty(&dma_desc_list)) {
1190                 dma_desc = list_first_entry(&dma_desc_list,
1191                                         typeof(*dma_desc), node);
1192                 list_del(&dma_desc->node);
1193                 kfree(dma_desc);
1194         }
1195
1196         while (!list_empty(&sg_req_list)) {
1197                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1198                 list_del(&sg_req->node);
1199                 kfree(sg_req);
1200         }
1201         clk_disable_unprepare(tdma->dma_clk);
1202 }
1203
1204 /* Tegra20 specific DMA controller information */
1205 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1206         .nr_channels            = 16,
1207         .max_dma_count          = 1024UL * 64,
1208         .support_channel_pause  = false,
1209 };
1210
1211 #if defined(CONFIG_OF)
1212 /* Tegra30 specific DMA controller information */
1213 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1214         .nr_channels            = 32,
1215         .max_dma_count          = 1024UL * 64,
1216         .support_channel_pause  = false,
1217 };
1218
1219 /* Tegra114 specific DMA controller information */
1220 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1221         .nr_channels            = 32,
1222         .max_dma_count          = 1024UL * 64,
1223         .support_channel_pause  = true,
1224 };
1225
1226
1227 static const struct of_device_id tegra_dma_of_match[] = {
1228         {
1229                 .compatible = "nvidia,tegra114-apbdma",
1230                 .data = &tegra114_dma_chip_data,
1231         }, {
1232                 .compatible = "nvidia,tegra30-apbdma",
1233                 .data = &tegra30_dma_chip_data,
1234         }, {
1235                 .compatible = "nvidia,tegra20-apbdma",
1236                 .data = &tegra20_dma_chip_data,
1237         }, {
1238         },
1239 };
1240 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1241 #endif
1242
1243 static int tegra_dma_probe(struct platform_device *pdev)
1244 {
1245         struct resource *res;
1246         struct tegra_dma *tdma;
1247         int ret;
1248         int i;
1249         const struct tegra_dma_chip_data *cdata = NULL;
1250
1251         if (pdev->dev.of_node) {
1252                 const struct of_device_id *match;
1253                 match = of_match_device(of_match_ptr(tegra_dma_of_match),
1254                                         &pdev->dev);
1255                 if (!match) {
1256                         dev_err(&pdev->dev, "Error: No device match found\n");
1257                         return -ENODEV;
1258                 }
1259                 cdata = match->data;
1260         } else {
1261                 /* If no device tree then fallback to tegra20 */
1262                 cdata = &tegra20_dma_chip_data;
1263         }
1264
1265         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1266                         sizeof(struct tegra_dma_channel), GFP_KERNEL);
1267         if (!tdma) {
1268                 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1269                 return -ENOMEM;
1270         }
1271
1272         tdma->dev = &pdev->dev;
1273         tdma->chip_data = cdata;
1274         platform_set_drvdata(pdev, tdma);
1275
1276         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1277         if (!res) {
1278                 dev_err(&pdev->dev, "No mem resource for DMA\n");
1279                 return -EINVAL;
1280         }
1281
1282         tdma->base_addr = devm_request_and_ioremap(&pdev->dev, res);
1283         if (!tdma->base_addr) {
1284                 dev_err(&pdev->dev,
1285                         "Cannot request memregion/iomap dma address\n");
1286                 return -EADDRNOTAVAIL;
1287         }
1288
1289         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1290         if (IS_ERR(tdma->dma_clk)) {
1291                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1292                 return PTR_ERR(tdma->dma_clk);
1293         }
1294
1295         spin_lock_init(&tdma->global_lock);
1296
1297         pm_runtime_enable(&pdev->dev);
1298         if (!pm_runtime_enabled(&pdev->dev)) {
1299                 ret = tegra_dma_runtime_resume(&pdev->dev);
1300                 if (ret) {
1301                         dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1302                                 ret);
1303                         goto err_pm_disable;
1304                 }
1305         }
1306
1307         /* Enable clock before accessing registers */
1308         ret = clk_prepare_enable(tdma->dma_clk);
1309         if (ret < 0) {
1310                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1311                 goto err_pm_disable;
1312         }
1313
1314         /* Reset DMA controller */
1315         tegra_periph_reset_assert(tdma->dma_clk);
1316         udelay(2);
1317         tegra_periph_reset_deassert(tdma->dma_clk);
1318
1319         /* Enable global DMA registers */
1320         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1321         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1322         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1323
1324         clk_disable_unprepare(tdma->dma_clk);
1325
1326         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1327         for (i = 0; i < cdata->nr_channels; i++) {
1328                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1329
1330                 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1331                                         i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1332
1333                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1334                 if (!res) {
1335                         ret = -EINVAL;
1336                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1337                         goto err_irq;
1338                 }
1339                 tdc->irq = res->start;
1340                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1341                 ret = devm_request_irq(&pdev->dev, tdc->irq,
1342                                 tegra_dma_isr, 0, tdc->name, tdc);
1343                 if (ret) {
1344                         dev_err(&pdev->dev,
1345                                 "request_irq failed with err %d channel %d\n",
1346                                 i, ret);
1347                         goto err_irq;
1348                 }
1349
1350                 tdc->dma_chan.device = &tdma->dma_dev;
1351                 dma_cookie_init(&tdc->dma_chan);
1352                 list_add_tail(&tdc->dma_chan.device_node,
1353                                 &tdma->dma_dev.channels);
1354                 tdc->tdma = tdma;
1355                 tdc->id = i;
1356
1357                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1358                                 (unsigned long)tdc);
1359                 spin_lock_init(&tdc->lock);
1360
1361                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1362                 INIT_LIST_HEAD(&tdc->free_sg_req);
1363                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1364                 INIT_LIST_HEAD(&tdc->cb_desc);
1365         }
1366
1367         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1368         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1369         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1370
1371         tdma->dma_dev.dev = &pdev->dev;
1372         tdma->dma_dev.device_alloc_chan_resources =
1373                                         tegra_dma_alloc_chan_resources;
1374         tdma->dma_dev.device_free_chan_resources =
1375                                         tegra_dma_free_chan_resources;
1376         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1377         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1378         tdma->dma_dev.device_control = tegra_dma_device_control;
1379         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1380         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1381
1382         ret = dma_async_device_register(&tdma->dma_dev);
1383         if (ret < 0) {
1384                 dev_err(&pdev->dev,
1385                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1386                 goto err_irq;
1387         }
1388
1389         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1390                         cdata->nr_channels);
1391         return 0;
1392
1393 err_irq:
1394         while (--i >= 0) {
1395                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1396                 tasklet_kill(&tdc->tasklet);
1397         }
1398
1399 err_pm_disable:
1400         pm_runtime_disable(&pdev->dev);
1401         if (!pm_runtime_status_suspended(&pdev->dev))
1402                 tegra_dma_runtime_suspend(&pdev->dev);
1403         return ret;
1404 }
1405
1406 static int __devexit tegra_dma_remove(struct platform_device *pdev)
1407 {
1408         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1409         int i;
1410         struct tegra_dma_channel *tdc;
1411
1412         dma_async_device_unregister(&tdma->dma_dev);
1413
1414         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1415                 tdc = &tdma->channels[i];
1416                 tasklet_kill(&tdc->tasklet);
1417         }
1418
1419         pm_runtime_disable(&pdev->dev);
1420         if (!pm_runtime_status_suspended(&pdev->dev))
1421                 tegra_dma_runtime_suspend(&pdev->dev);
1422
1423         return 0;
1424 }
1425
1426 static int tegra_dma_runtime_suspend(struct device *dev)
1427 {
1428         struct platform_device *pdev = to_platform_device(dev);
1429         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1430
1431         clk_disable_unprepare(tdma->dma_clk);
1432         return 0;
1433 }
1434
1435 static int tegra_dma_runtime_resume(struct device *dev)
1436 {
1437         struct platform_device *pdev = to_platform_device(dev);
1438         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1439         int ret;
1440
1441         ret = clk_prepare_enable(tdma->dma_clk);
1442         if (ret < 0) {
1443                 dev_err(dev, "clk_enable failed: %d\n", ret);
1444                 return ret;
1445         }
1446         return 0;
1447 }
1448
1449 static const struct dev_pm_ops tegra_dma_dev_pm_ops __devinitconst = {
1450 #ifdef CONFIG_PM_RUNTIME
1451         .runtime_suspend = tegra_dma_runtime_suspend,
1452         .runtime_resume = tegra_dma_runtime_resume,
1453 #endif
1454 };
1455
1456 static struct platform_driver tegra_dmac_driver = {
1457         .driver = {
1458                 .name   = "tegra-apbdma",
1459                 .owner = THIS_MODULE,
1460                 .pm     = &tegra_dma_dev_pm_ops,
1461                 .of_match_table = of_match_ptr(tegra_dma_of_match),
1462         },
1463         .probe          = tegra_dma_probe,
1464         .remove         = tegra_dma_remove,
1465 };
1466
1467 module_platform_driver(tegra_dmac_driver);
1468
1469 MODULE_ALIAS("platform:tegra20-apbdma");
1470 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1471 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1472 MODULE_LICENSE("GPL v2");