drivers/dma/tegra20-apb-dma.c

   1 /*
   2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
   3  *
   4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_dma.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/reset.h>
  37 #include <linux/slab.h>
  38
  39 #include "dmaengine.h"
  40
  41 #define TEGRA_APBDMA_GENERAL                    0x0
  42 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
  43
  44 #define TEGRA_APBDMA_CONTROL                    0x010
  45 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
  46 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
  47
  48 /* CSR register */
  49 #define TEGRA_APBDMA_CHAN_CSR                   0x00
  50 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
  51 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
  52 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
  53 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
  54 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
  55 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
  56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
  57 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
  58
  59 /* STATUS register */
  60 #define TEGRA_APBDMA_CHAN_STATUS                0x004
  61 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
  62 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
  63 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
  64 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
  65 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
  66 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
  67
  68 #define TEGRA_APBDMA_CHAN_CSRE                  0x00C
  69 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE            (1 << 31)
  70
  71 /* AHB memory address */
  72 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
  73
  74 /* AHB sequence register */
  75 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
  76 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
  77 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
  78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
  79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
  80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
  81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
  82 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
  83 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
  84 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
  85 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
  86 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
  87 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
  88 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
  89
  90 /* APB address */
  91 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
  92
  93 /* APB sequence register */
  94 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
  95 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
  96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
  97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
  98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
  99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
 100 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
 101 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
 102
 103 /* Tegra148 specific registers */
 104 #define TEGRA_APBDMA_CHAN_WCOUNT                0x20
 105
 106 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER         0x24
 107
 108 /*
 109  * If any burst is in flight and DMA paused then this is the time to complete
 110  * on-flight burst and update DMA status register.
 111  */
 112 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
 113
 114 /* Channel base address offset from APBDMA base address */
 115 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
 116
 117 struct tegra_dma;
 118
 119 /*
 120  * tegra_dma_chip_data Tegra chip specific DMA data
 121  * @nr_channels: Number of channels available in the controller.
 122  * @channel_reg_size: Channel register size/stride.
 123  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 124  * @support_channel_pause: Support channel wise pause of dma.
 125  * @support_separate_wcount_reg: Support separate word count register.
 126  */
 127 struct tegra_dma_chip_data {
 128         int nr_channels;
 129         int channel_reg_size;
 130         int max_dma_count;
 131         bool support_channel_pause;
 132         bool support_separate_wcount_reg;
 133 };
 134
 135 /* DMA channel registers */
 136 struct tegra_dma_channel_regs {
 137         unsigned long   csr;
 138         unsigned long   ahb_ptr;
 139         unsigned long   apb_ptr;
 140         unsigned long   ahb_seq;
 141         unsigned long   apb_seq;
 142         unsigned long   wcount;
 143 };
 144
 145 /*
 146  * tegra_dma_sg_req: Dma request details to configure hardware. This
 147  * contains the details for one transfer to configure DMA hw.
 148  * The client's request for data transfer can be broken into multiple
 149  * sub-transfer as per requester details and hw support.
 150  * This sub transfer get added in the list of transfer and point to Tegra
 151  * DMA descriptor which manages the transfer details.
 152  */
 153 struct tegra_dma_sg_req {
 154         struct tegra_dma_channel_regs   ch_regs;
 155         int                             req_len;
 156         bool                            configured;
 157         bool                            last_sg;
 158         struct list_head                node;
 159         struct tegra_dma_desc           *dma_desc;
 160 };
 161
 162 /*
 163  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 164  * This descriptor keep track of transfer status, callbacks and request
 165  * counts etc.
 166  */
 167 struct tegra_dma_desc {
 168         struct dma_async_tx_descriptor  txd;
 169         int                             bytes_requested;
 170         int                             bytes_transferred;
 171         enum dma_status                 dma_status;
 172         struct list_head                node;
 173         struct list_head                tx_list;
 174         struct list_head                cb_node;
 175         int                             cb_count;
 176 };
 177
 178 struct tegra_dma_channel;
 179
 180 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
 181                                 bool to_terminate);
 182
 183 /* tegra_dma_channel: Channel specific information */
 184 struct tegra_dma_channel {
 185         struct dma_chan         dma_chan;
 186         char                    name[30];
 187         bool                    config_init;
 188         int                     id;
 189         int                     irq;
 190         unsigned long           chan_base_offset;
 191         spinlock_t              lock;
 192         bool                    busy;
 193         struct tegra_dma        *tdma;
 194         bool                    cyclic;
 195
 196         /* Different lists for managing the requests */
 197         struct list_head        free_sg_req;
 198         struct list_head        pending_sg_req;
 199         struct list_head        free_dma_desc;
 200         struct list_head        cb_desc;
 201
 202         /* ISR handler and tasklet for bottom half of isr handling */
 203         dma_isr_handler         isr_handler;
 204         struct tasklet_struct   tasklet;
 205
 206         /* Channel-slave specific configuration */
 207         unsigned int slave_id;
 208         struct dma_slave_config dma_sconfig;
 209         struct tegra_dma_channel_regs   channel_reg;
 210 };
 211
 212 /* tegra_dma: Tegra DMA specific information */
 213 struct tegra_dma {
 214         struct dma_device               dma_dev;
 215         struct device                   *dev;
 216         struct clk                      *dma_clk;
 217         struct reset_control            *rst;
 218         spinlock_t                      global_lock;
 219         void __iomem                    *base_addr;
 220         const struct tegra_dma_chip_data *chip_data;
 221
 222         /* Some register need to be cache before suspend */
 223         u32                             reg_gen;
 224
 225         /* Last member of the structure */
 226         struct tegra_dma_channel channels[0];
 227 };
 228
 229 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
 230 {
 231         writel(val, tdma->base_addr + reg);
 232 }
 233
 234 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
 235 {
 236         return readl(tdma->base_addr + reg);
 237 }
 238
 239 static inline void tdc_write(struct tegra_dma_channel *tdc,
 240                 u32 reg, u32 val)
 241 {
 242         writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 243 }
 244
 245 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
 246 {
 247         return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 248 }
 249
 250 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
 251 {
 252         return container_of(dc, struct tegra_dma_channel, dma_chan);
 253 }
 254
 255 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
 256                 struct dma_async_tx_descriptor *td)
 257 {
 258         return container_of(td, struct tegra_dma_desc, txd);
 259 }
 260
 261 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
 262 {
 263         return &tdc->dma_chan.dev->device;
 264 }
 265
 266 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
 267 static int tegra_dma_runtime_suspend(struct device *dev);
 268 static int tegra_dma_runtime_resume(struct device *dev);
 269
 270 /* Get DMA desc from free list, if not there then allocate it.  */
 271 static struct tegra_dma_desc *tegra_dma_desc_get(
 272                 struct tegra_dma_channel *tdc)
 273 {
 274         struct tegra_dma_desc *dma_desc;
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&tdc->lock, flags);
 278
 279         /* Do not allocate if desc are waiting for ack */
 280         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 281                 if (async_tx_test_ack(&dma_desc->txd)) {
 282                         list_del(&dma_desc->node);
 283                         spin_unlock_irqrestore(&tdc->lock, flags);
 284                         dma_desc->txd.flags = 0;
 285                         return dma_desc;
 286                 }
 287         }
 288
 289         spin_unlock_irqrestore(&tdc->lock, flags);
 290
 291         /* Allocate DMA desc */
 292         dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
 293         if (!dma_desc) {
 294                 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
 295                 return NULL;
 296         }
 297
 298         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 299         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
 300         dma_desc->txd.flags = 0;
 301         return dma_desc;
 302 }
 303
 304 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
 305                 struct tegra_dma_desc *dma_desc)
 306 {
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&tdc->lock, flags);
 310         if (!list_empty(&dma_desc->tx_list))
 311                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
 312         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 313         spin_unlock_irqrestore(&tdc->lock, flags);
 314 }
 315
 316 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
 317                 struct tegra_dma_channel *tdc)
 318 {
 319         struct tegra_dma_sg_req *sg_req = NULL;
 320         unsigned long flags;
 321
 322         spin_lock_irqsave(&tdc->lock, flags);
 323         if (!list_empty(&tdc->free_sg_req)) {
 324                 sg_req = list_first_entry(&tdc->free_sg_req,
 325                                         typeof(*sg_req), node);
 326                 list_del(&sg_req->node);
 327                 spin_unlock_irqrestore(&tdc->lock, flags);
 328                 return sg_req;
 329         }
 330         spin_unlock_irqrestore(&tdc->lock, flags);
 331
 332         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
 333         if (!sg_req)
 334                 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
 335         return sg_req;
 336 }
 337
 338 static int tegra_dma_slave_config(struct dma_chan *dc,
 339                 struct dma_slave_config *sconfig)
 340 {
 341         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 342
 343         if (!list_empty(&tdc->pending_sg_req)) {
 344                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
 345                 return -EBUSY;
 346         }
 347
 348         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
 349         if (!tdc->slave_id)
 350                 tdc->slave_id = sconfig->slave_id;
 351         tdc->config_init = true;
 352         return 0;
 353 }
 354
 355 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
 356         bool wait_for_burst_complete)
 357 {
 358         struct tegra_dma *tdma = tdc->tdma;
 359
 360         spin_lock(&tdma->global_lock);
 361         tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
 362         if (wait_for_burst_complete)
 363                 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 364 }
 365
 366 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
 367 {
 368         struct tegra_dma *tdma = tdc->tdma;
 369
 370         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
 371         spin_unlock(&tdma->global_lock);
 372 }
 373
 374 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
 375         bool wait_for_burst_complete)
 376 {
 377         struct tegra_dma *tdma = tdc->tdma;
 378
 379         if (tdma->chip_data->support_channel_pause) {
 380                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
 381                                 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
 382                 if (wait_for_burst_complete)
 383                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 384         } else {
 385                 tegra_dma_global_pause(tdc, wait_for_burst_complete);
 386         }
 387 }
 388
 389 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
 390 {
 391         struct tegra_dma *tdma = tdc->tdma;
 392
 393         if (tdma->chip_data->support_channel_pause) {
 394                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
 395         } else {
 396                 tegra_dma_global_resume(tdc);
 397         }
 398 }
 399
 400 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
 401 {
 402         u32 csr;
 403         u32 status;
 404
 405         /* Disable interrupts */
 406         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
 407         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
 408         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 409
 410         /* Disable DMA */
 411         csr &= ~TEGRA_APBDMA_CSR_ENB;
 412         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 413
 414         /* Clear interrupt status if it is there */
 415         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 416         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 417                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
 418                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 419         }
 420         tdc->busy = false;
 421 }
 422
 423 static void tegra_dma_start(struct tegra_dma_channel *tdc,
 424                 struct tegra_dma_sg_req *sg_req)
 425 {
 426         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
 427
 428         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
 429         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
 430         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
 431         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
 432         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
 433         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 434                 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
 435
 436         /* Start DMA */
 437         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 438                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
 439 }
 440
 441 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
 442                 struct tegra_dma_sg_req *nsg_req)
 443 {
 444         unsigned long status;
 445
 446         /*
 447          * The DMA controller reloads the new configuration for next transfer
 448          * after last burst of current transfer completes.
 449          * If there is no IEC status then this makes sure that last burst
 450          * has not be completed. There may be case that last burst is on
 451          * flight and so it can complete but because DMA is paused, it
 452          * will not generates interrupt as well as not reload the new
 453          * configuration.
 454          * If there is already IEC status then interrupt handler need to
 455          * load new configuration.
 456          */
 457         tegra_dma_pause(tdc, false);
 458         status  = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 459
 460         /*
 461          * If interrupt is pending then do nothing as the ISR will handle
 462          * the programing for new request.
 463          */
 464         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 465                 dev_err(tdc2dev(tdc),
 466                         "Skipping new configuration as interrupt is pending\n");
 467                 tegra_dma_resume(tdc);
 468                 return;
 469         }
 470
 471         /* Safe to program new configuration */
 472         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
 473         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
 474         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 475                 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
 476                                                 nsg_req->ch_regs.wcount);
 477         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 478                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
 479         nsg_req->configured = true;
 480
 481         tegra_dma_resume(tdc);
 482 }
 483
 484 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
 485 {
 486         struct tegra_dma_sg_req *sg_req;
 487
 488         if (list_empty(&tdc->pending_sg_req))
 489                 return;
 490
 491         sg_req = list_first_entry(&tdc->pending_sg_req,
 492                                         typeof(*sg_req), node);
 493         tegra_dma_start(tdc, sg_req);
 494         sg_req->configured = true;
 495         tdc->busy = true;
 496 }
 497
 498 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
 499 {
 500         struct tegra_dma_sg_req *hsgreq;
 501         struct tegra_dma_sg_req *hnsgreq;
 502
 503         if (list_empty(&tdc->pending_sg_req))
 504                 return;
 505
 506         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 507         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
 508                 hnsgreq = list_first_entry(&hsgreq->node,
 509                                         typeof(*hnsgreq), node);
 510                 tegra_dma_configure_for_next(tdc, hnsgreq);
 511         }
 512 }
 513
 514 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
 515         struct tegra_dma_sg_req *sg_req, unsigned long status)
 516 {
 517         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
 518 }
 519
 520 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
 521 {
 522         struct tegra_dma_sg_req *sgreq;
 523         struct tegra_dma_desc *dma_desc;
 524
 525         while (!list_empty(&tdc->pending_sg_req)) {
 526                 sgreq = list_first_entry(&tdc->pending_sg_req,
 527                                                 typeof(*sgreq), node);
 528                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
 529                 if (sgreq->last_sg) {
 530                         dma_desc = sgreq->dma_desc;
 531                         dma_desc->dma_status = DMA_ERROR;
 532                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 533
 534                         /* Add in cb list if it is not there. */
 535                         if (!dma_desc->cb_count)
 536                                 list_add_tail(&dma_desc->cb_node,
 537                                                         &tdc->cb_desc);
 538                         dma_desc->cb_count++;
 539                 }
 540         }
 541         tdc->isr_handler = NULL;
 542 }
 543
 544 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
 545                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
 546 {
 547         struct tegra_dma_sg_req *hsgreq = NULL;
 548
 549         if (list_empty(&tdc->pending_sg_req)) {
 550                 dev_err(tdc2dev(tdc), "Dma is running without req\n");
 551                 tegra_dma_stop(tdc);
 552                 return false;
 553         }
 554
 555         /*
 556          * Check that head req on list should be in flight.
 557          * If it is not in flight then abort transfer as
 558          * looping of transfer can not continue.
 559          */
 560         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 561         if (!hsgreq->configured) {
 562                 tegra_dma_stop(tdc);
 563                 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
 564                 tegra_dma_abort_all(tdc);
 565                 return false;
 566         }
 567
 568         /* Configure next request */
 569         if (!to_terminate)
 570                 tdc_configure_next_head_desc(tdc);
 571         return true;
 572 }
 573
 574 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
 575         bool to_terminate)
 576 {
 577         struct tegra_dma_sg_req *sgreq;
 578         struct tegra_dma_desc *dma_desc;
 579
 580         tdc->busy = false;
 581         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 582         dma_desc = sgreq->dma_desc;
 583         dma_desc->bytes_transferred += sgreq->req_len;
 584
 585         list_del(&sgreq->node);
 586         if (sgreq->last_sg) {
 587                 dma_desc->dma_status = DMA_COMPLETE;
 588                 dma_cookie_complete(&dma_desc->txd);
 589                 if (!dma_desc->cb_count)
 590                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 591                 dma_desc->cb_count++;
 592                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 593         }
 594         list_add_tail(&sgreq->node, &tdc->free_sg_req);
 595
 596         /* Do not start DMA if it is going to be terminate */
 597         if (to_terminate || list_empty(&tdc->pending_sg_req))
 598                 return;
 599
 600         tdc_start_head_req(tdc);
 601         return;
 602 }
 603
 604 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
 605                 bool to_terminate)
 606 {
 607         struct tegra_dma_sg_req *sgreq;
 608         struct tegra_dma_desc *dma_desc;
 609         bool st;
 610
 611         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 612         dma_desc = sgreq->dma_desc;
 613         dma_desc->bytes_transferred += sgreq->req_len;
 614
 615         /* Callback need to be call */
 616         if (!dma_desc->cb_count)
 617                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 618         dma_desc->cb_count++;
 619
 620         /* If not last req then put at end of pending list */
 621         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
 622                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
 623                 sgreq->configured = false;
 624                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
 625                 if (!st)
 626                         dma_desc->dma_status = DMA_ERROR;
 627         }
 628         return;
 629 }
 630
 631 static void tegra_dma_tasklet(unsigned long data)
 632 {
 633         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
 634         dma_async_tx_callback callback = NULL;
 635         void *callback_param = NULL;
 636         struct tegra_dma_desc *dma_desc;
 637         unsigned long flags;
 638         int cb_count;
 639
 640         spin_lock_irqsave(&tdc->lock, flags);
 641         while (!list_empty(&tdc->cb_desc)) {
 642                 dma_desc  = list_first_entry(&tdc->cb_desc,
 643                                         typeof(*dma_desc), cb_node);
 644                 list_del(&dma_desc->cb_node);
 645                 callback = dma_desc->txd.callback;
 646                 callback_param = dma_desc->txd.callback_param;
 647                 cb_count = dma_desc->cb_count;
 648                 dma_desc->cb_count = 0;
 649                 spin_unlock_irqrestore(&tdc->lock, flags);
 650                 while (cb_count-- && callback)
 651                         callback(callback_param);
 652                 spin_lock_irqsave(&tdc->lock, flags);
 653         }
 654         spin_unlock_irqrestore(&tdc->lock, flags);
 655 }
 656
 657 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
 658 {
 659         struct tegra_dma_channel *tdc = dev_id;
 660         unsigned long status;
 661         unsigned long flags;
 662
 663         spin_lock_irqsave(&tdc->lock, flags);
 664
 665         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 666         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 667                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 668                 tdc->isr_handler(tdc, false);
 669                 tasklet_schedule(&tdc->tasklet);
 670                 spin_unlock_irqrestore(&tdc->lock, flags);
 671                 return IRQ_HANDLED;
 672         }
 673
 674         spin_unlock_irqrestore(&tdc->lock, flags);
 675         dev_info(tdc2dev(tdc),
 676                 "Interrupt already served status 0x%08lx\n", status);
 677         return IRQ_NONE;
 678 }
 679
 680 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 681 {
 682         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 683         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
 684         unsigned long flags;
 685         dma_cookie_t cookie;
 686
 687         spin_lock_irqsave(&tdc->lock, flags);
 688         dma_desc->dma_status = DMA_IN_PROGRESS;
 689         cookie = dma_cookie_assign(&dma_desc->txd);
 690         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
 691         spin_unlock_irqrestore(&tdc->lock, flags);
 692         return cookie;
 693 }
 694
 695 static void tegra_dma_issue_pending(struct dma_chan *dc)
 696 {
 697         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 698         unsigned long flags;
 699
 700         spin_lock_irqsave(&tdc->lock, flags);
 701         if (list_empty(&tdc->pending_sg_req)) {
 702                 dev_err(tdc2dev(tdc), "No DMA request\n");
 703                 goto end;
 704         }
 705         if (!tdc->busy) {
 706                 tdc_start_head_req(tdc);
 707
 708                 /* Continuous single mode: Configure next req */
 709                 if (tdc->cyclic) {
 710                         /*
 711                          * Wait for 1 burst time for configure DMA for
 712                          * next transfer.
 713                          */
 714                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 715                         tdc_configure_next_head_desc(tdc);
 716                 }
 717         }
 718 end:
 719         spin_unlock_irqrestore(&tdc->lock, flags);
 720         return;
 721 }
 722
 723 static int tegra_dma_terminate_all(struct dma_chan *dc)
 724 {
 725         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 726         struct tegra_dma_sg_req *sgreq;
 727         struct tegra_dma_desc *dma_desc;
 728         unsigned long flags;
 729         unsigned long status;
 730         unsigned long wcount;
 731         bool was_busy;
 732
 733         spin_lock_irqsave(&tdc->lock, flags);
 734         if (list_empty(&tdc->pending_sg_req)) {
 735                 spin_unlock_irqrestore(&tdc->lock, flags);
 736                 return 0;
 737         }
 738
 739         if (!tdc->busy)
 740                 goto skip_dma_stop;
 741
 742         /* Pause DMA before checking the queue status */
 743         tegra_dma_pause(tdc, true);
 744
 745         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 746         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 747                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
 748                 tdc->isr_handler(tdc, true);
 749                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 750         }
 751         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 752                 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
 753         else
 754                 wcount = status;
 755
 756         was_busy = tdc->busy;
 757         tegra_dma_stop(tdc);
 758
 759         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
 760                 sgreq = list_first_entry(&tdc->pending_sg_req,
 761                                         typeof(*sgreq), node);
 762                 sgreq->dma_desc->bytes_transferred +=
 763                                 get_current_xferred_count(tdc, sgreq, wcount);
 764         }
 765         tegra_dma_resume(tdc);
 766
 767 skip_dma_stop:
 768         tegra_dma_abort_all(tdc);
 769
 770         while (!list_empty(&tdc->cb_desc)) {
 771                 dma_desc  = list_first_entry(&tdc->cb_desc,
 772                                         typeof(*dma_desc), cb_node);
 773                 list_del(&dma_desc->cb_node);
 774                 dma_desc->cb_count = 0;
 775         }
 776         spin_unlock_irqrestore(&tdc->lock, flags);
 777         return 0;
 778 }
 779
 780 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
 781         dma_cookie_t cookie, struct dma_tx_state *txstate)
 782 {
 783         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 784         struct tegra_dma_desc *dma_desc;
 785         struct tegra_dma_sg_req *sg_req;
 786         enum dma_status ret;
 787         unsigned long flags;
 788         unsigned int residual;
 789
 790         ret = dma_cookie_status(dc, cookie, txstate);
 791         if (ret == DMA_COMPLETE)
 792                 return ret;
 793
 794         spin_lock_irqsave(&tdc->lock, flags);
 795
 796         /* Check on wait_ack desc status */
 797         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 798                 if (dma_desc->txd.cookie == cookie) {
 799                         residual =  dma_desc->bytes_requested -
 800                                         (dma_desc->bytes_transferred %
 801                                                 dma_desc->bytes_requested);
 802                         dma_set_residue(txstate, residual);
 803                         ret = dma_desc->dma_status;
 804                         spin_unlock_irqrestore(&tdc->lock, flags);
 805                         return ret;
 806                 }
 807         }
 808
 809         /* Check in pending list */
 810         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
 811                 dma_desc = sg_req->dma_desc;
 812                 if (dma_desc->txd.cookie == cookie) {
 813                         residual =  dma_desc->bytes_requested -
 814                                         (dma_desc->bytes_transferred %
 815                                                 dma_desc->bytes_requested);
 816                         dma_set_residue(txstate, residual);
 817                         ret = dma_desc->dma_status;
 818                         spin_unlock_irqrestore(&tdc->lock, flags);
 819                         return ret;
 820                 }
 821         }
 822
 823         dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
 824         spin_unlock_irqrestore(&tdc->lock, flags);
 825         return ret;
 826 }
 827
 828 static inline int get_bus_width(struct tegra_dma_channel *tdc,
 829                 enum dma_slave_buswidth slave_bw)
 830 {
 831         switch (slave_bw) {
 832         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 833                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
 834         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 835                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 836         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 837                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 838         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 839                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
 840         default:
 841                 dev_warn(tdc2dev(tdc),
 842                         "slave bw is not supported, using 32bits\n");
 843                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 844         }
 845 }
 846
 847 static inline int get_burst_size(struct tegra_dma_channel *tdc,
 848         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
 849 {
 850         int burst_byte;
 851         int burst_ahb_width;
 852
 853         /*
 854          * burst_size from client is in terms of the bus_width.
 855          * convert them into AHB memory width which is 4 byte.
 856          */
 857         burst_byte = burst_size * slave_bw;
 858         burst_ahb_width = burst_byte / 4;
 859
 860         /* If burst size is 0 then calculate the burst size based on length */
 861         if (!burst_ahb_width) {
 862                 if (len & 0xF)
 863                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
 864                 else if ((len >> 4) & 0x1)
 865                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
 866                 else
 867                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
 868         }
 869         if (burst_ahb_width < 4)
 870                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
 871         else if (burst_ahb_width < 8)
 872                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
 873         else
 874                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
 875 }
 876
 877 static int get_transfer_param(struct tegra_dma_channel *tdc,
 878         enum dma_transfer_direction direction, unsigned long *apb_addr,
 879         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
 880         enum dma_slave_buswidth *slave_bw)
 881 {
 882
 883         switch (direction) {
 884         case DMA_MEM_TO_DEV:
 885                 *apb_addr = tdc->dma_sconfig.dst_addr;
 886                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
 887                 *burst_size = tdc->dma_sconfig.dst_maxburst;
 888                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
 889                 *csr = TEGRA_APBDMA_CSR_DIR;
 890                 return 0;
 891
 892         case DMA_DEV_TO_MEM:
 893                 *apb_addr = tdc->dma_sconfig.src_addr;
 894                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
 895                 *burst_size = tdc->dma_sconfig.src_maxburst;
 896                 *slave_bw = tdc->dma_sconfig.src_addr_width;
 897                 *csr = 0;
 898                 return 0;
 899
 900         default:
 901                 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
 902                 return -EINVAL;
 903         }
 904         return -EINVAL;
 905 }
 906
 907 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
 908         struct tegra_dma_channel_regs *ch_regs, u32 len)
 909 {
 910         u32 len_field = (len - 4) & 0xFFFC;
 911
 912         if (tdc->tdma->chip_data->support_separate_wcount_reg)
 913                 ch_regs->wcount = len_field;
 914         else
 915                 ch_regs->csr |= len_field;
 916 }
 917
 918 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 919         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
 920         enum dma_transfer_direction direction, unsigned long flags,
 921         void *context)
 922 {
 923         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 924         struct tegra_dma_desc *dma_desc;
 925         unsigned int        i;
 926         struct scatterlist      *sg;
 927         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
 928         struct list_head req_list;
 929         struct tegra_dma_sg_req  *sg_req = NULL;
 930         u32 burst_size;
 931         enum dma_slave_buswidth slave_bw;
 932         int ret;
 933
 934         if (!tdc->config_init) {
 935                 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
 936                 return NULL;
 937         }
 938         if (sg_len < 1) {
 939                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
 940                 return NULL;
 941         }
 942
 943         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
 944                                 &burst_size, &slave_bw);
 945         if (ret < 0)
 946                 return NULL;
 947
 948         INIT_LIST_HEAD(&req_list);
 949
 950         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
 951         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
 952                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 953         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 954
 955         csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
 956         csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 957         if (flags & DMA_PREP_INTERRUPT)
 958                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
 959
 960         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 961
 962         dma_desc = tegra_dma_desc_get(tdc);
 963         if (!dma_desc) {
 964                 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
 965                 return NULL;
 966         }
 967         INIT_LIST_HEAD(&dma_desc->tx_list);
 968         INIT_LIST_HEAD(&dma_desc->cb_node);
 969         dma_desc->cb_count = 0;
 970         dma_desc->bytes_requested = 0;
 971         dma_desc->bytes_transferred = 0;
 972         dma_desc->dma_status = DMA_IN_PROGRESS;
 973
 974         /* Make transfer requests */
 975         for_each_sg(sgl, sg, sg_len, i) {
 976                 u32 len, mem;
 977
 978                 mem = sg_dma_address(sg);
 979                 len = sg_dma_len(sg);
 980
 981                 if ((len & 3) || (mem & 3) ||
 982                                 (len > tdc->tdma->chip_data->max_dma_count)) {
 983                         dev_err(tdc2dev(tdc),
 984                                 "Dma length/memory address is not supported\n");
 985                         tegra_dma_desc_put(tdc, dma_desc);
 986                         return NULL;
 987                 }
 988
 989                 sg_req = tegra_dma_sg_req_get(tdc);
 990                 if (!sg_req) {
 991                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
 992                         tegra_dma_desc_put(tdc, dma_desc);
 993                         return NULL;
 994                 }
 995
 996                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
 997                 dma_desc->bytes_requested += len;
 998
 999                 sg_req->ch_regs.apb_ptr = apb_ptr;
1000                 sg_req->ch_regs.ahb_ptr = mem;
1001                 sg_req->ch_regs.csr = csr;
1002                 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1003                 sg_req->ch_regs.apb_seq = apb_seq;
1004                 sg_req->ch_regs.ahb_seq = ahb_seq;
1005                 sg_req->configured = false;
1006                 sg_req->last_sg = false;
1007                 sg_req->dma_desc = dma_desc;
1008                 sg_req->req_len = len;
1009
1010                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1011         }
1012         sg_req->last_sg = true;
1013         if (flags & DMA_CTRL_ACK)
1014                 dma_desc->txd.flags = DMA_CTRL_ACK;
1015
1016         /*
1017          * Make sure that mode should not be conflicting with currently
1018          * configured mode.
1019          */
1020         if (!tdc->isr_handler) {
1021                 tdc->isr_handler = handle_once_dma_done;
1022                 tdc->cyclic = false;
1023         } else {
1024                 if (tdc->cyclic) {
1025                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1026                         tegra_dma_desc_put(tdc, dma_desc);
1027                         return NULL;
1028                 }
1029         }
1030
1031         return &dma_desc->txd;
1032 }
1033
1034 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1035         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1036         size_t period_len, enum dma_transfer_direction direction,
1037         unsigned long flags)
1038 {
1039         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1040         struct tegra_dma_desc *dma_desc = NULL;
1041         struct tegra_dma_sg_req  *sg_req = NULL;
1042         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1043         int len;
1044         size_t remain_len;
1045         dma_addr_t mem = buf_addr;
1046         u32 burst_size;
1047         enum dma_slave_buswidth slave_bw;
1048         int ret;
1049
1050         if (!buf_len || !period_len) {
1051                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1052                 return NULL;
1053         }
1054
1055         if (!tdc->config_init) {
1056                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1057                 return NULL;
1058         }
1059
1060         /*
1061          * We allow to take more number of requests till DMA is
1062          * not started. The driver will loop over all requests.
1063          * Once DMA is started then new requests can be queued only after
1064          * terminating the DMA.
1065          */
1066         if (tdc->busy) {
1067                 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1068                 return NULL;
1069         }
1070
1071         /*
1072          * We only support cycle transfer when buf_len is multiple of
1073          * period_len.
1074          */
1075         if (buf_len % period_len) {
1076                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1077                 return NULL;
1078         }
1079
1080         len = period_len;
1081         if ((len & 3) || (buf_addr & 3) ||
1082                         (len > tdc->tdma->chip_data->max_dma_count)) {
1083                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1084                 return NULL;
1085         }
1086
1087         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1088                                 &burst_size, &slave_bw);
1089         if (ret < 0)
1090                 return NULL;
1091
1092
1093         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1094         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1095                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1096         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1097
1098         csr |= TEGRA_APBDMA_CSR_FLOW;
1099         if (flags & DMA_PREP_INTERRUPT)
1100                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1101         csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1102
1103         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1104
1105         dma_desc = tegra_dma_desc_get(tdc);
1106         if (!dma_desc) {
1107                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1108                 return NULL;
1109         }
1110
1111         INIT_LIST_HEAD(&dma_desc->tx_list);
1112         INIT_LIST_HEAD(&dma_desc->cb_node);
1113         dma_desc->cb_count = 0;
1114
1115         dma_desc->bytes_transferred = 0;
1116         dma_desc->bytes_requested = buf_len;
1117         remain_len = buf_len;
1118
1119         /* Split transfer equal to period size */
1120         while (remain_len) {
1121                 sg_req = tegra_dma_sg_req_get(tdc);
1122                 if (!sg_req) {
1123                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1124                         tegra_dma_desc_put(tdc, dma_desc);
1125                         return NULL;
1126                 }
1127
1128                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1129                 sg_req->ch_regs.apb_ptr = apb_ptr;
1130                 sg_req->ch_regs.ahb_ptr = mem;
1131                 sg_req->ch_regs.csr = csr;
1132                 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1133                 sg_req->ch_regs.apb_seq = apb_seq;
1134                 sg_req->ch_regs.ahb_seq = ahb_seq;
1135                 sg_req->configured = false;
1136                 sg_req->last_sg = false;
1137                 sg_req->dma_desc = dma_desc;
1138                 sg_req->req_len = len;
1139
1140                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1141                 remain_len -= len;
1142                 mem += len;
1143         }
1144         sg_req->last_sg = true;
1145         if (flags & DMA_CTRL_ACK)
1146                 dma_desc->txd.flags = DMA_CTRL_ACK;
1147
1148         /*
1149          * Make sure that mode should not be conflicting with currently
1150          * configured mode.
1151          */
1152         if (!tdc->isr_handler) {
1153                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1154                 tdc->cyclic = true;
1155         } else {
1156                 if (!tdc->cyclic) {
1157                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1158                         tegra_dma_desc_put(tdc, dma_desc);
1159                         return NULL;
1160                 }
1161         }
1162
1163         return &dma_desc->txd;
1164 }
1165
1166 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1167 {
1168         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1169         struct tegra_dma *tdma = tdc->tdma;
1170         int ret;
1171
1172         dma_cookie_init(&tdc->dma_chan);
1173         tdc->config_init = false;
1174         ret = clk_prepare_enable(tdma->dma_clk);
1175         if (ret < 0)
1176                 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1177         return ret;
1178 }
1179
1180 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1181 {
1182         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1183         struct tegra_dma *tdma = tdc->tdma;
1184
1185         struct tegra_dma_desc *dma_desc;
1186         struct tegra_dma_sg_req *sg_req;
1187         struct list_head dma_desc_list;
1188         struct list_head sg_req_list;
1189         unsigned long flags;
1190
1191         INIT_LIST_HEAD(&dma_desc_list);
1192         INIT_LIST_HEAD(&sg_req_list);
1193
1194         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1195
1196         if (tdc->busy)
1197                 tegra_dma_terminate_all(dc);
1198
1199         spin_lock_irqsave(&tdc->lock, flags);
1200         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1201         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1202         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1203         INIT_LIST_HEAD(&tdc->cb_desc);
1204         tdc->config_init = false;
1205         tdc->isr_handler = NULL;
1206         spin_unlock_irqrestore(&tdc->lock, flags);
1207
1208         while (!list_empty(&dma_desc_list)) {
1209                 dma_desc = list_first_entry(&dma_desc_list,
1210                                         typeof(*dma_desc), node);
1211                 list_del(&dma_desc->node);
1212                 kfree(dma_desc);
1213         }
1214
1215         while (!list_empty(&sg_req_list)) {
1216                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1217                 list_del(&sg_req->node);
1218                 kfree(sg_req);
1219         }
1220         clk_disable_unprepare(tdma->dma_clk);
1221
1222         tdc->slave_id = 0;
1223 }
1224
1225 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1226                                            struct of_dma *ofdma)
1227 {
1228         struct tegra_dma *tdma = ofdma->of_dma_data;
1229         struct dma_chan *chan;
1230         struct tegra_dma_channel *tdc;
1231
1232         chan = dma_get_any_slave_channel(&tdma->dma_dev);
1233         if (!chan)
1234                 return NULL;
1235
1236         tdc = to_tegra_dma_chan(chan);
1237         tdc->slave_id = dma_spec->args[0];
1238
1239         return chan;
1240 }
1241
1242 /* Tegra20 specific DMA controller information */
1243 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1244         .nr_channels            = 16,
1245         .channel_reg_size       = 0x20,
1246         .max_dma_count          = 1024UL * 64,
1247         .support_channel_pause  = false,
1248         .support_separate_wcount_reg = false,
1249 };
1250
1251 /* Tegra30 specific DMA controller information */
1252 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1253         .nr_channels            = 32,
1254         .channel_reg_size       = 0x20,
1255         .max_dma_count          = 1024UL * 64,
1256         .support_channel_pause  = false,
1257         .support_separate_wcount_reg = false,
1258 };
1259
1260 /* Tegra114 specific DMA controller information */
1261 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1262         .nr_channels            = 32,
1263         .channel_reg_size       = 0x20,
1264         .max_dma_count          = 1024UL * 64,
1265         .support_channel_pause  = true,
1266         .support_separate_wcount_reg = false,
1267 };
1268
1269 /* Tegra148 specific DMA controller information */
1270 static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1271         .nr_channels            = 32,
1272         .channel_reg_size       = 0x40,
1273         .max_dma_count          = 1024UL * 64,
1274         .support_channel_pause  = true,
1275         .support_separate_wcount_reg = true,
1276 };
1277
1278
1279 static const struct of_device_id tegra_dma_of_match[] = {
1280         {
1281                 .compatible = "nvidia,tegra148-apbdma",
1282                 .data = &tegra148_dma_chip_data,
1283         }, {
1284                 .compatible = "nvidia,tegra114-apbdma",
1285                 .data = &tegra114_dma_chip_data,
1286         }, {
1287                 .compatible = "nvidia,tegra30-apbdma",
1288                 .data = &tegra30_dma_chip_data,
1289         }, {
1290                 .compatible = "nvidia,tegra20-apbdma",
1291                 .data = &tegra20_dma_chip_data,
1292         }, {
1293         },
1294 };
1295 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1296
1297 static int tegra_dma_probe(struct platform_device *pdev)
1298 {
1299         struct resource *res;
1300         struct tegra_dma *tdma;
1301         int ret;
1302         int i;
1303         const struct tegra_dma_chip_data *cdata = NULL;
1304         const struct of_device_id *match;
1305
1306         match = of_match_device(tegra_dma_of_match, &pdev->dev);
1307         if (!match) {
1308                 dev_err(&pdev->dev, "Error: No device match found\n");
1309                 return -ENODEV;
1310         }
1311         cdata = match->data;
1312
1313         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1314                         sizeof(struct tegra_dma_channel), GFP_KERNEL);
1315         if (!tdma) {
1316                 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1317                 return -ENOMEM;
1318         }
1319
1320         tdma->dev = &pdev->dev;
1321         tdma->chip_data = cdata;
1322         platform_set_drvdata(pdev, tdma);
1323
1324         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1325         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1326         if (IS_ERR(tdma->base_addr))
1327                 return PTR_ERR(tdma->base_addr);
1328
1329         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1330         if (IS_ERR(tdma->dma_clk)) {
1331                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1332                 return PTR_ERR(tdma->dma_clk);
1333         }
1334
1335         tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1336         if (IS_ERR(tdma->rst)) {
1337                 dev_err(&pdev->dev, "Error: Missing reset\n");
1338                 return PTR_ERR(tdma->rst);
1339         }
1340
1341         spin_lock_init(&tdma->global_lock);
1342
1343         pm_runtime_enable(&pdev->dev);
1344         if (!pm_runtime_enabled(&pdev->dev)) {
1345                 ret = tegra_dma_runtime_resume(&pdev->dev);
1346                 if (ret) {
1347                         dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1348                                 ret);
1349                         goto err_pm_disable;
1350                 }
1351         }
1352
1353         /* Enable clock before accessing registers */
1354         ret = clk_prepare_enable(tdma->dma_clk);
1355         if (ret < 0) {
1356                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1357                 goto err_pm_disable;
1358         }
1359
1360         /* Reset DMA controller */
1361         reset_control_assert(tdma->rst);
1362         udelay(2);
1363         reset_control_deassert(tdma->rst);
1364
1365         /* Enable global DMA registers */
1366         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1367         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1368         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1369
1370         clk_disable_unprepare(tdma->dma_clk);
1371
1372         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1373         for (i = 0; i < cdata->nr_channels; i++) {
1374                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1375
1376                 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1377                                         i * cdata->channel_reg_size;
1378
1379                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1380                 if (!res) {
1381                         ret = -EINVAL;
1382                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1383                         goto err_irq;
1384                 }
1385                 tdc->irq = res->start;
1386                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1387                 ret = devm_request_irq(&pdev->dev, tdc->irq,
1388                                 tegra_dma_isr, 0, tdc->name, tdc);
1389                 if (ret) {
1390                         dev_err(&pdev->dev,
1391                                 "request_irq failed with err %d channel %d\n",
1392                                 ret, i);
1393                         goto err_irq;
1394                 }
1395
1396                 tdc->dma_chan.device = &tdma->dma_dev;
1397                 dma_cookie_init(&tdc->dma_chan);
1398                 list_add_tail(&tdc->dma_chan.device_node,
1399                                 &tdma->dma_dev.channels);
1400                 tdc->tdma = tdma;
1401                 tdc->id = i;
1402
1403                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1404                                 (unsigned long)tdc);
1405                 spin_lock_init(&tdc->lock);
1406
1407                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1408                 INIT_LIST_HEAD(&tdc->free_sg_req);
1409                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1410                 INIT_LIST_HEAD(&tdc->cb_desc);
1411         }
1412
1413         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1414         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1415         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1416
1417         tdma->dma_dev.dev = &pdev->dev;
1418         tdma->dma_dev.device_alloc_chan_resources =
1419                                         tegra_dma_alloc_chan_resources;
1420         tdma->dma_dev.device_free_chan_resources =
1421                                         tegra_dma_free_chan_resources;
1422         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1423         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1424         tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1425                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1426                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1427                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1428         tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1429                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1430                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1431                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1432         tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1433         /*
1434          * XXX The hardware appears to support
1435          * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1436          * only used by this driver during tegra_dma_terminate_all()
1437          */
1438         tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1439         tdma->dma_dev.device_config = tegra_dma_slave_config;
1440         tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1441         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1442         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1443
1444         ret = dma_async_device_register(&tdma->dma_dev);
1445         if (ret < 0) {
1446                 dev_err(&pdev->dev,
1447                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1448                 goto err_irq;
1449         }
1450
1451         ret = of_dma_controller_register(pdev->dev.of_node,
1452                                          tegra_dma_of_xlate, tdma);
1453         if (ret < 0) {
1454                 dev_err(&pdev->dev,
1455                         "Tegra20 APB DMA OF registration failed %d\n", ret);
1456                 goto err_unregister_dma_dev;
1457         }
1458
1459         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1460                         cdata->nr_channels);
1461         return 0;
1462
1463 err_unregister_dma_dev:
1464         dma_async_device_unregister(&tdma->dma_dev);
1465 err_irq:
1466         while (--i >= 0) {
1467                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1468                 tasklet_kill(&tdc->tasklet);
1469         }
1470
1471 err_pm_disable:
1472         pm_runtime_disable(&pdev->dev);
1473         if (!pm_runtime_status_suspended(&pdev->dev))
1474                 tegra_dma_runtime_suspend(&pdev->dev);
1475         return ret;
1476 }
1477
1478 static int tegra_dma_remove(struct platform_device *pdev)
1479 {
1480         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1481         int i;
1482         struct tegra_dma_channel *tdc;
1483
1484         dma_async_device_unregister(&tdma->dma_dev);
1485
1486         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1487                 tdc = &tdma->channels[i];
1488                 tasklet_kill(&tdc->tasklet);
1489         }
1490
1491         pm_runtime_disable(&pdev->dev);
1492         if (!pm_runtime_status_suspended(&pdev->dev))
1493                 tegra_dma_runtime_suspend(&pdev->dev);
1494
1495         return 0;
1496 }
1497
1498 static int tegra_dma_runtime_suspend(struct device *dev)
1499 {
1500         struct platform_device *pdev = to_platform_device(dev);
1501         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1502
1503         clk_disable_unprepare(tdma->dma_clk);
1504         return 0;
1505 }
1506
1507 static int tegra_dma_runtime_resume(struct device *dev)
1508 {
1509         struct platform_device *pdev = to_platform_device(dev);
1510         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1511         int ret;
1512
1513         ret = clk_prepare_enable(tdma->dma_clk);
1514         if (ret < 0) {
1515                 dev_err(dev, "clk_enable failed: %d\n", ret);
1516                 return ret;
1517         }
1518         return 0;
1519 }
1520
1521 #ifdef CONFIG_PM_SLEEP
1522 static int tegra_dma_pm_suspend(struct device *dev)
1523 {
1524         struct tegra_dma *tdma = dev_get_drvdata(dev);
1525         int i;
1526         int ret;
1527
1528         /* Enable clock before accessing register */
1529         ret = tegra_dma_runtime_resume(dev);
1530         if (ret < 0)
1531                 return ret;
1532
1533         tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1534         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1535                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1536                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1537
1538                 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1539                 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1540                 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1541                 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1542                 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1543         }
1544
1545         /* Disable clock */
1546         tegra_dma_runtime_suspend(dev);
1547         return 0;
1548 }
1549
1550 static int tegra_dma_pm_resume(struct device *dev)
1551 {
1552         struct tegra_dma *tdma = dev_get_drvdata(dev);
1553         int i;
1554         int ret;
1555
1556         /* Enable clock before accessing register */
1557         ret = tegra_dma_runtime_resume(dev);
1558         if (ret < 0)
1559                 return ret;
1560
1561         tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1562         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1563         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1564
1565         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1566                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1567                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1568
1569                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1570                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1571                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1572                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1573                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1574                         (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1575         }
1576
1577         /* Disable clock */
1578         tegra_dma_runtime_suspend(dev);
1579         return 0;
1580 }
1581 #endif
1582
1583 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1584 #ifdef CONFIG_PM
1585         .runtime_suspend = tegra_dma_runtime_suspend,
1586         .runtime_resume = tegra_dma_runtime_resume,
1587 #endif
1588         SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
1589 };
1590
1591 static struct platform_driver tegra_dmac_driver = {
1592         .driver = {
1593                 .name   = "tegra-apbdma",
1594                 .pm     = &tegra_dma_dev_pm_ops,
1595                 .of_match_table = tegra_dma_of_match,
1596         },
1597         .probe          = tegra_dma_probe,
1598         .remove         = tegra_dma_remove,
1599 };
1600
1601 module_platform_driver(tegra_dmac_driver);
1602
1603 MODULE_ALIAS("platform:tegra20-apbdma");
1604 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1605 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1606 MODULE_LICENSE("GPL v2");