1 #include "amd64_edac.h"
4 * accept a hex value and store it into the virtual error register file, field:
5 * nbeal and nbeah. Assume virtual error values have already been set for: NBSL,
6 * NBSH and NBCFG. Then proceed to map the error values to a MC, CSROW and
9 static ssize_t amd64_nbea_store(struct mem_ctl_info *mci, const char *data,
12 struct amd64_pvt *pvt = mci->pvt_info;
17 ret = strict_strtoull(data, 16, &value);
19 struct err_regs *regs = &pvt->ctl_error_info;
21 debugf0("received NBEA= 0x%llx\n", value);
23 /* place the value into the virtual error packet */
24 pvt->ctl_error_info.nbeal = (u32) value;
26 pvt->ctl_error_info.nbeah = (u32) value;
29 m.status = regs->nbsl | ((u64)regs->nbsh << 32);
31 /* Process the Mapping request */
32 /* TODO: Add race prevention */
33 amd_decode_nb_mce(pvt->mc_node_id, &m, regs->nbcfg);
40 /* display back what the last NBEA (MCA NB Address (MC4_ADDR)) was written */
41 static ssize_t amd64_nbea_show(struct mem_ctl_info *mci, char *data)
43 struct amd64_pvt *pvt = mci->pvt_info;
46 value = pvt->ctl_error_info.nbeah;
48 value |= pvt->ctl_error_info.nbeal;
50 return sprintf(data, "%llx\n", value);
53 /* store the NBSL (MCA NB Status Low (MC4_STATUS)) value user desires */
54 static ssize_t amd64_nbsl_store(struct mem_ctl_info *mci, const char *data,
57 struct amd64_pvt *pvt = mci->pvt_info;
61 ret = strict_strtoul(data, 16, &value);
63 debugf0("received NBSL= 0x%lx\n", value);
65 pvt->ctl_error_info.nbsl = (u32) value;
72 /* display back what the last NBSL value written */
73 static ssize_t amd64_nbsl_show(struct mem_ctl_info *mci, char *data)
75 struct amd64_pvt *pvt = mci->pvt_info;
78 value = pvt->ctl_error_info.nbsl;
80 return sprintf(data, "%x\n", value);
83 /* store the NBSH (MCA NB Status High) value user desires */
84 static ssize_t amd64_nbsh_store(struct mem_ctl_info *mci, const char *data,
87 struct amd64_pvt *pvt = mci->pvt_info;
91 ret = strict_strtoul(data, 16, &value);
93 debugf0("received NBSH= 0x%lx\n", value);
95 pvt->ctl_error_info.nbsh = (u32) value;
102 /* display back what the last NBSH value written */
103 static ssize_t amd64_nbsh_show(struct mem_ctl_info *mci, char *data)
105 struct amd64_pvt *pvt = mci->pvt_info;
108 value = pvt->ctl_error_info.nbsh;
110 return sprintf(data, "%x\n", value);
113 /* accept and store the NBCFG (MCA NB Configuration) value user desires */
114 static ssize_t amd64_nbcfg_store(struct mem_ctl_info *mci,
115 const char *data, size_t count)
117 struct amd64_pvt *pvt = mci->pvt_info;
121 ret = strict_strtoul(data, 16, &value);
122 if (ret != -EINVAL) {
123 debugf0("received NBCFG= 0x%lx\n", value);
125 pvt->ctl_error_info.nbcfg = (u32) value;
132 /* various show routines for the controls of a MCI */
133 static ssize_t amd64_nbcfg_show(struct mem_ctl_info *mci, char *data)
135 struct amd64_pvt *pvt = mci->pvt_info;
137 return sprintf(data, "%x\n", pvt->ctl_error_info.nbcfg);
141 static ssize_t amd64_dhar_show(struct mem_ctl_info *mci, char *data)
143 struct amd64_pvt *pvt = mci->pvt_info;
145 return sprintf(data, "%x\n", pvt->dhar);
149 static ssize_t amd64_dbam_show(struct mem_ctl_info *mci, char *data)
151 struct amd64_pvt *pvt = mci->pvt_info;
153 return sprintf(data, "%x\n", pvt->dbam0);
157 static ssize_t amd64_topmem_show(struct mem_ctl_info *mci, char *data)
159 struct amd64_pvt *pvt = mci->pvt_info;
161 return sprintf(data, "%llx\n", pvt->top_mem);
165 static ssize_t amd64_topmem2_show(struct mem_ctl_info *mci, char *data)
167 struct amd64_pvt *pvt = mci->pvt_info;
169 return sprintf(data, "%llx\n", pvt->top_mem2);
172 static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
178 amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
180 return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
185 * update NUM_DBG_ATTRS in case you add new members
187 struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
192 .mode = (S_IRUGO | S_IWUSR)
194 .show = amd64_nbea_show,
195 .store = amd64_nbea_store,
200 .mode = (S_IRUGO | S_IWUSR)
202 .show = amd64_nbsl_show,
203 .store = amd64_nbsl_store,
208 .mode = (S_IRUGO | S_IWUSR)
210 .show = amd64_nbsh_show,
211 .store = amd64_nbsh_store,
216 .mode = (S_IRUGO | S_IWUSR)
218 .show = amd64_nbcfg_show,
219 .store = amd64_nbcfg_store,
226 .show = amd64_dhar_show,
234 .show = amd64_dbam_show,
242 .show = amd64_topmem_show,
250 .show = amd64_topmem2_show,
258 .show = amd64_hole_show,