2 * Intel 3200/3210 Memory Controller kernel module
3 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
4 * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
6 * This file may be distributed under the terms of the
7 * GNU General Public License.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/pci.h>
13 #include <linux/pci_ids.h>
14 #include <linux/edac.h>
16 #include "edac_core.h"
18 #include <asm-generic/io-64-nonatomic-lo-hi.h>
20 #define I3200_REVISION "1.1"
22 #define EDAC_MOD_STR "i3200_edac"
24 #define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0
27 #define I3200_RANKS_PER_CHANNEL 4
28 #define I3200_CHANNELS 2
30 /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
32 #define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
33 #define I3200_MCHBAR_HIGH 0x4c
34 #define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
35 #define I3200_MMR_WINDOW_SIZE 16384
37 #define I3200_TOM 0xa0 /* Top of Memory (16b)
40 * 9:0 total populated physical memory
42 #define I3200_TOM_MASK 0x3ff /* bits 9:0 */
43 #define I3200_TOM_SHIFT 26 /* 64MiB grain */
45 #define I3200_ERRSTS 0xc8 /* Error Status Register (16b)
48 * 14 Isochronous TBWRR Run Behind FIFO Full
50 * 13 Isochronous TBWRR Run Behind FIFO Put
53 * 11 MCH Thermal Sensor Event
54 * for SMI/SCI/SERR (GTSE)
56 * 9 LOCK to non-DRAM Memory Flag (LCKF)
58 * 7 DRAM Throttle Flag (DTF)
60 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
61 * 0 Single-bit DRAM ECC Error Flag (DSERR)
63 #define I3200_ERRSTS_UE 0x0002
64 #define I3200_ERRSTS_CE 0x0001
65 #define I3200_ERRSTS_BITS (I3200_ERRSTS_UE | I3200_ERRSTS_CE)
68 /* Intel MMIO register space - device 0 function 0 - MMR space */
70 #define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
73 * 9:0 Channel 0 DRAM Rank Boundary Address
75 #define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
76 #define I3200_DRB_MASK 0x3ff /* bits 9:0 */
77 #define I3200_DRB_SHIFT 26 /* 64MiB grain */
79 #define I3200_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
81 * 63:48 Error Column Address (ERRCOL)
82 * 47:32 Error Row Address (ERRROW)
83 * 31:29 Error Bank Address (ERRBANK)
84 * 28:27 Error Rank Address (ERRRANK)
86 * 23:16 Error Syndrome (ERRSYND)
88 * 1 Multiple Bit Error Status (MERRSTS)
89 * 0 Correctable Error Status (CERRSTS)
91 #define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */
92 #define I3200_ECCERRLOG_CE 0x1
93 #define I3200_ECCERRLOG_UE 0x2
94 #define I3200_ECCERRLOG_RANK_BITS 0x18000000
95 #define I3200_ECCERRLOG_RANK_SHIFT 27
96 #define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000
97 #define I3200_ECCERRLOG_SYNDROME_SHIFT 16
98 #define I3200_CAPID0 0xe0 /* P.95 of spec for details */
101 void __iomem *window;
104 static int nr_channels;
106 static int how_many_channels(struct pci_dev *pdev)
108 unsigned char capid0_8b; /* 8th byte of CAPID0 */
110 pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
111 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
112 debugf0("In single channel mode.\n");
115 debugf0("In dual channel mode.\n");
120 static unsigned long eccerrlog_syndrome(u64 log)
122 return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
123 I3200_ECCERRLOG_SYNDROME_SHIFT;
126 static int eccerrlog_row(int channel, u64 log)
128 u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
129 I3200_ECCERRLOG_RANK_SHIFT);
130 return rank | (channel * I3200_RANKS_PER_CHANNEL);
137 struct i3200_dev_info {
138 const char *ctl_name;
141 struct i3200_error_info {
144 u64 eccerrlog[I3200_CHANNELS];
147 static const struct i3200_dev_info i3200_devs[] = {
153 static struct pci_dev *mci_pdev;
154 static int i3200_registered = 1;
157 static void i3200_clear_error_info(struct mem_ctl_info *mci)
159 struct pci_dev *pdev;
161 pdev = to_pci_dev(mci->dev);
164 * Clear any error bits.
165 * (Yes, we really clear bits by writing 1 to them.)
167 pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
171 static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
172 struct i3200_error_info *info)
174 struct pci_dev *pdev;
175 struct i3200_priv *priv = mci->pvt_info;
176 void __iomem *window = priv->window;
178 pdev = to_pci_dev(mci->dev);
181 * This is a mess because there is no atomic way to read all the
182 * registers at once and the registers can transition from CE being
185 pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
186 if (!(info->errsts & I3200_ERRSTS_BITS))
189 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
190 if (nr_channels == 2)
191 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
193 pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
196 * If the error is the same for both reads then the first set
197 * of reads is valid. If there is a change then there is a CE
198 * with no info and the second set of reads is valid and
201 if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
202 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
203 if (nr_channels == 2)
204 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
207 i3200_clear_error_info(mci);
210 static void i3200_process_error_info(struct mem_ctl_info *mci,
211 struct i3200_error_info *info)
216 if (!(info->errsts & I3200_ERRSTS_BITS))
219 if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
220 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
221 info->errsts = info->errsts2;
224 for (channel = 0; channel < nr_channels; channel++) {
225 log = info->eccerrlog[channel];
226 if (log & I3200_ECCERRLOG_UE) {
227 edac_mc_handle_ue(mci, 0, 0,
228 eccerrlog_row(channel, log),
230 } else if (log & I3200_ECCERRLOG_CE) {
231 edac_mc_handle_ce(mci, 0, 0,
232 eccerrlog_syndrome(log),
233 eccerrlog_row(channel, log), 0,
239 static void i3200_check(struct mem_ctl_info *mci)
241 struct i3200_error_info info;
243 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
244 i3200_get_and_clear_error_info(mci, &info);
245 i3200_process_error_info(mci, &info);
249 void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
258 void __iomem *window;
260 pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
261 pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
262 u.mchbar &= I3200_MCHBAR_MASK;
264 if (u.mchbar != (resource_size_t)u.mchbar) {
266 "i3200: mmio space beyond accessible range (0x%llx)\n",
267 (unsigned long long)u.mchbar);
271 window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
273 printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
274 (unsigned long long)u.mchbar);
280 static void i3200_get_drbs(void __iomem *window,
281 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
285 for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
286 drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
287 drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
291 static bool i3200_is_stacked(struct pci_dev *pdev,
292 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
296 pci_read_config_word(pdev, I3200_TOM, &tom);
297 tom &= I3200_TOM_MASK;
299 return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
302 static unsigned long drb_to_nr_pages(
303 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
304 int channel, int rank)
308 n = drbs[channel][rank];
310 n -= drbs[channel][rank - 1];
311 if (stacked && (channel == 1) &&
312 drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
313 n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
315 n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
319 static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
323 struct mem_ctl_info *mci = NULL;
324 unsigned long last_page;
325 u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
327 void __iomem *window;
328 struct i3200_priv *priv;
330 debugf0("MC: %s()\n", __func__);
332 window = i3200_map_mchbar(pdev);
336 i3200_get_drbs(window, drbs);
337 nr_channels = how_many_channels(pdev);
339 mci = edac_mc_alloc(sizeof(struct i3200_priv), I3200_RANKS,
344 debugf3("MC: %s(): init mci\n", __func__);
346 mci->dev = &pdev->dev;
347 mci->mtype_cap = MEM_FLAG_DDR2;
349 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
350 mci->edac_cap = EDAC_FLAG_SECDED;
352 mci->mod_name = EDAC_MOD_STR;
353 mci->mod_ver = I3200_REVISION;
354 mci->ctl_name = i3200_devs[dev_idx].ctl_name;
355 mci->dev_name = pci_name(pdev);
356 mci->edac_check = i3200_check;
357 mci->ctl_page_to_phys = NULL;
358 priv = mci->pvt_info;
359 priv->window = window;
361 stacked = i3200_is_stacked(pdev, drbs);
364 * The dram rank boundary (DRB) reg values are boundary addresses
365 * for each DRAM rank with a granularity of 64MB. DRB regs are
366 * cumulative; the last one will contain the total memory
367 * contained in all ranks.
370 for (i = 0; i < mci->nr_csrows; i++) {
371 unsigned long nr_pages;
372 struct csrow_info *csrow = &mci->csrows[i];
374 nr_pages = drb_to_nr_pages(drbs, stacked,
375 i / I3200_RANKS_PER_CHANNEL,
376 i % I3200_RANKS_PER_CHANNEL);
379 csrow->mtype = MEM_EMPTY;
383 csrow->first_page = last_page + 1;
384 last_page += nr_pages;
385 csrow->last_page = last_page;
386 csrow->nr_pages = nr_pages;
388 csrow->grain = nr_pages << PAGE_SHIFT;
389 csrow->mtype = MEM_DDR2;
390 csrow->dtype = DEV_UNKNOWN;
391 csrow->edac_mode = EDAC_UNKNOWN;
394 i3200_clear_error_info(mci);
397 if (edac_mc_add_mc(mci)) {
398 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
402 /* get this far and it's successful */
403 debugf3("MC: %s(): success\n", __func__);
414 static int __devinit i3200_init_one(struct pci_dev *pdev,
415 const struct pci_device_id *ent)
419 debugf0("MC: %s()\n", __func__);
421 if (pci_enable_device(pdev) < 0)
424 rc = i3200_probe1(pdev, ent->driver_data);
426 mci_pdev = pci_dev_get(pdev);
431 static void __devexit i3200_remove_one(struct pci_dev *pdev)
433 struct mem_ctl_info *mci;
434 struct i3200_priv *priv;
436 debugf0("%s()\n", __func__);
438 mci = edac_mc_del_mc(&pdev->dev);
442 priv = mci->pvt_info;
443 iounmap(priv->window);
448 static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
450 PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
454 } /* 0 terminated list. */
457 MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
459 static struct pci_driver i3200_driver = {
460 .name = EDAC_MOD_STR,
461 .probe = i3200_init_one,
462 .remove = __devexit_p(i3200_remove_one),
463 .id_table = i3200_pci_tbl,
466 static int __init i3200_init(void)
470 debugf3("MC: %s()\n", __func__);
472 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
475 pci_rc = pci_register_driver(&i3200_driver);
480 i3200_registered = 0;
481 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
482 PCI_DEVICE_ID_INTEL_3200_HB, NULL);
484 debugf0("i3200 pci_get_device fail\n");
489 pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
491 debugf0("i3200 init fail\n");
500 pci_unregister_driver(&i3200_driver);
504 pci_dev_put(mci_pdev);
509 static void __exit i3200_exit(void)
511 debugf3("MC: %s()\n", __func__);
513 pci_unregister_driver(&i3200_driver);
514 if (!i3200_registered) {
515 i3200_remove_one(mci_pdev);
516 pci_dev_put(mci_pdev);
520 module_init(i3200_init);
521 module_exit(i3200_exit);
523 MODULE_LICENSE("GPL");
524 MODULE_AUTHOR("Akamai Technologies, Inc.");
525 MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
527 module_param(edac_op_state, int, 0444);
528 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");