drivers/edac/i5000_edac.c

   1 /*
   2  * Intel 5000(P/V/X) class Memory Controllers kernel module
   3  *
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Douglas Thompson Linux Networx (http://lnxi.com)
   8  *      norsk5@xmission.com
   9  *
  10  * This module is based on the following document:
  11  *
  12  * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
  13  *      http://developer.intel.com/design/chipsets/datashts/313070.htm
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <linux/pci_ids.h>
  21 #include <linux/slab.h>
  22 #include <linux/edac.h>
  23 #include <asm/mmzone.h>
  24
  25 #include "edac_core.h"
  26
  27 /*
  28  * Alter this version for the I5000 module when modifications are made
  29  */
  30 #define I5000_REVISION    " Ver: 2.0.12"
  31 #define EDAC_MOD_STR      "i5000_edac"
  32
  33 #define i5000_printk(level, fmt, arg...) \
  34         edac_printk(level, "i5000", fmt, ##arg)
  35
  36 #define i5000_mc_printk(mci, level, fmt, arg...) \
  37         edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
  38
  39 #ifndef PCI_DEVICE_ID_INTEL_FBD_0
  40 #define PCI_DEVICE_ID_INTEL_FBD_0       0x25F5
  41 #endif
  42 #ifndef PCI_DEVICE_ID_INTEL_FBD_1
  43 #define PCI_DEVICE_ID_INTEL_FBD_1       0x25F6
  44 #endif
  45
  46 /* Device 16,
  47  * Function 0: System Address
  48  * Function 1: Memory Branch Map, Control, Errors Register
  49  * Function 2: FSB Error Registers
  50  *
  51  * All 3 functions of Device 16 (0,1,2) share the SAME DID
  52  */
  53 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
  54
  55 /* OFFSETS for Function 0 */
  56
  57 /* OFFSETS for Function 1 */
  58 #define         AMBASE                  0x48
  59 #define         MAXCH                   0x56
  60 #define         MAXDIMMPERCH            0x57
  61 #define         TOLM                    0x6C
  62 #define         REDMEMB                 0x7C
  63 #define                 RED_ECC_LOCATOR(x)      ((x) & 0x3FFFF)
  64 #define                 REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
  65 #define                 REC_ECC_LOCATOR_ODD(x)  ((x) & 0x3FE00)
  66 #define         MIR0                    0x80
  67 #define         MIR1                    0x84
  68 #define         MIR2                    0x88
  69 #define         AMIR0                   0x8C
  70 #define         AMIR1                   0x90
  71 #define         AMIR2                   0x94
  72
  73 #define         FERR_FAT_FBD            0x98
  74 #define         NERR_FAT_FBD            0x9C
  75 #define                 EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
  76 #define                 FERR_FAT_FBDCHAN 0x30000000
  77 #define                 FERR_FAT_M3ERR  0x00000004
  78 #define                 FERR_FAT_M2ERR  0x00000002
  79 #define                 FERR_FAT_M1ERR  0x00000001
  80 #define                 FERR_FAT_MASK   (FERR_FAT_M1ERR | \
  81                                                 FERR_FAT_M2ERR | \
  82                                                 FERR_FAT_M3ERR)
  83
  84 #define         FERR_NF_FBD             0xA0
  85
  86 /* Thermal and SPD or BFD errors */
  87 #define                 FERR_NF_M28ERR  0x01000000
  88 #define                 FERR_NF_M27ERR  0x00800000
  89 #define                 FERR_NF_M26ERR  0x00400000
  90 #define                 FERR_NF_M25ERR  0x00200000
  91 #define                 FERR_NF_M24ERR  0x00100000
  92 #define                 FERR_NF_M23ERR  0x00080000
  93 #define                 FERR_NF_M22ERR  0x00040000
  94 #define                 FERR_NF_M21ERR  0x00020000
  95
  96 /* Correctable errors */
  97 #define                 FERR_NF_M20ERR  0x00010000
  98 #define                 FERR_NF_M19ERR  0x00008000
  99 #define                 FERR_NF_M18ERR  0x00004000
 100 #define                 FERR_NF_M17ERR  0x00002000
 101
 102 /* Non-Retry or redundant Retry errors */
 103 #define                 FERR_NF_M16ERR  0x00001000
 104 #define                 FERR_NF_M15ERR  0x00000800
 105 #define                 FERR_NF_M14ERR  0x00000400
 106 #define                 FERR_NF_M13ERR  0x00000200
 107
 108 /* Uncorrectable errors */
 109 #define                 FERR_NF_M12ERR  0x00000100
 110 #define                 FERR_NF_M11ERR  0x00000080
 111 #define                 FERR_NF_M10ERR  0x00000040
 112 #define                 FERR_NF_M9ERR   0x00000020
 113 #define                 FERR_NF_M8ERR   0x00000010
 114 #define                 FERR_NF_M7ERR   0x00000008
 115 #define                 FERR_NF_M6ERR   0x00000004
 116 #define                 FERR_NF_M5ERR   0x00000002
 117 #define                 FERR_NF_M4ERR   0x00000001
 118
 119 #define                 FERR_NF_UNCORRECTABLE   (FERR_NF_M12ERR | \
 120                                                         FERR_NF_M11ERR | \
 121                                                         FERR_NF_M10ERR | \
 122                                                         FERR_NF_M9ERR | \
 123                                                         FERR_NF_M8ERR | \
 124                                                         FERR_NF_M7ERR | \
 125                                                         FERR_NF_M6ERR | \
 126                                                         FERR_NF_M5ERR | \
 127                                                         FERR_NF_M4ERR)
 128 #define                 FERR_NF_CORRECTABLE     (FERR_NF_M20ERR | \
 129                                                         FERR_NF_M19ERR | \
 130                                                         FERR_NF_M18ERR | \
 131                                                         FERR_NF_M17ERR)
 132 #define                 FERR_NF_DIMM_SPARE      (FERR_NF_M27ERR | \
 133                                                         FERR_NF_M28ERR)
 134 #define                 FERR_NF_THERMAL         (FERR_NF_M26ERR | \
 135                                                         FERR_NF_M25ERR | \
 136                                                         FERR_NF_M24ERR | \
 137                                                         FERR_NF_M23ERR)
 138 #define                 FERR_NF_SPD_PROTOCOL    (FERR_NF_M22ERR)
 139 #define                 FERR_NF_NORTH_CRC       (FERR_NF_M21ERR)
 140 #define                 FERR_NF_NON_RETRY       (FERR_NF_M13ERR | \
 141                                                         FERR_NF_M14ERR | \
 142                                                         FERR_NF_M15ERR)
 143
 144 #define         NERR_NF_FBD             0xA4
 145 #define                 FERR_NF_MASK            (FERR_NF_UNCORRECTABLE | \
 146                                                         FERR_NF_CORRECTABLE | \
 147                                                         FERR_NF_DIMM_SPARE | \
 148                                                         FERR_NF_THERMAL | \
 149                                                         FERR_NF_SPD_PROTOCOL | \
 150                                                         FERR_NF_NORTH_CRC | \
 151                                                         FERR_NF_NON_RETRY)
 152
 153 #define         EMASK_FBD               0xA8
 154 #define                 EMASK_FBD_M28ERR        0x08000000
 155 #define                 EMASK_FBD_M27ERR        0x04000000
 156 #define                 EMASK_FBD_M26ERR        0x02000000
 157 #define                 EMASK_FBD_M25ERR        0x01000000
 158 #define                 EMASK_FBD_M24ERR        0x00800000
 159 #define                 EMASK_FBD_M23ERR        0x00400000
 160 #define                 EMASK_FBD_M22ERR        0x00200000
 161 #define                 EMASK_FBD_M21ERR        0x00100000
 162 #define                 EMASK_FBD_M20ERR        0x00080000
 163 #define                 EMASK_FBD_M19ERR        0x00040000
 164 #define                 EMASK_FBD_M18ERR        0x00020000
 165 #define                 EMASK_FBD_M17ERR        0x00010000
 166
 167 #define                 EMASK_FBD_M15ERR        0x00004000
 168 #define                 EMASK_FBD_M14ERR        0x00002000
 169 #define                 EMASK_FBD_M13ERR        0x00001000
 170 #define                 EMASK_FBD_M12ERR        0x00000800
 171 #define                 EMASK_FBD_M11ERR        0x00000400
 172 #define                 EMASK_FBD_M10ERR        0x00000200
 173 #define                 EMASK_FBD_M9ERR         0x00000100
 174 #define                 EMASK_FBD_M8ERR         0x00000080
 175 #define                 EMASK_FBD_M7ERR         0x00000040
 176 #define                 EMASK_FBD_M6ERR         0x00000020
 177 #define                 EMASK_FBD_M5ERR         0x00000010
 178 #define                 EMASK_FBD_M4ERR         0x00000008
 179 #define                 EMASK_FBD_M3ERR         0x00000004
 180 #define                 EMASK_FBD_M2ERR         0x00000002
 181 #define                 EMASK_FBD_M1ERR         0x00000001
 182
 183 #define                 ENABLE_EMASK_FBD_FATAL_ERRORS   (EMASK_FBD_M1ERR | \
 184                                                         EMASK_FBD_M2ERR | \
 185                                                         EMASK_FBD_M3ERR)
 186
 187 #define                 ENABLE_EMASK_FBD_UNCORRECTABLE  (EMASK_FBD_M4ERR | \
 188                                                         EMASK_FBD_M5ERR | \
 189                                                         EMASK_FBD_M6ERR | \
 190                                                         EMASK_FBD_M7ERR | \
 191                                                         EMASK_FBD_M8ERR | \
 192                                                         EMASK_FBD_M9ERR | \
 193                                                         EMASK_FBD_M10ERR | \
 194                                                         EMASK_FBD_M11ERR | \
 195                                                         EMASK_FBD_M12ERR)
 196 #define                 ENABLE_EMASK_FBD_CORRECTABLE    (EMASK_FBD_M17ERR | \
 197                                                         EMASK_FBD_M18ERR | \
 198                                                         EMASK_FBD_M19ERR | \
 199                                                         EMASK_FBD_M20ERR)
 200 #define                 ENABLE_EMASK_FBD_DIMM_SPARE     (EMASK_FBD_M27ERR | \
 201                                                         EMASK_FBD_M28ERR)
 202 #define                 ENABLE_EMASK_FBD_THERMALS       (EMASK_FBD_M26ERR | \
 203                                                         EMASK_FBD_M25ERR | \
 204                                                         EMASK_FBD_M24ERR | \
 205                                                         EMASK_FBD_M23ERR)
 206 #define                 ENABLE_EMASK_FBD_SPD_PROTOCOL   (EMASK_FBD_M22ERR)
 207 #define                 ENABLE_EMASK_FBD_NORTH_CRC      (EMASK_FBD_M21ERR)
 208 #define                 ENABLE_EMASK_FBD_NON_RETRY      (EMASK_FBD_M15ERR | \
 209                                                         EMASK_FBD_M14ERR | \
 210                                                         EMASK_FBD_M13ERR)
 211
 212 #define         ENABLE_EMASK_ALL        (ENABLE_EMASK_FBD_NON_RETRY | \
 213                                         ENABLE_EMASK_FBD_NORTH_CRC | \
 214                                         ENABLE_EMASK_FBD_SPD_PROTOCOL | \
 215                                         ENABLE_EMASK_FBD_THERMALS | \
 216                                         ENABLE_EMASK_FBD_DIMM_SPARE | \
 217                                         ENABLE_EMASK_FBD_FATAL_ERRORS | \
 218                                         ENABLE_EMASK_FBD_CORRECTABLE | \
 219                                         ENABLE_EMASK_FBD_UNCORRECTABLE)
 220
 221 #define         ERR0_FBD                0xAC
 222 #define         ERR1_FBD                0xB0
 223 #define         ERR2_FBD                0xB4
 224 #define         MCERR_FBD               0xB8
 225 #define         NRECMEMA                0xBE
 226 #define                 NREC_BANK(x)            (((x)>>12) & 0x7)
 227 #define                 NREC_RDWR(x)            (((x)>>11) & 1)
 228 #define                 NREC_RANK(x)            (((x)>>8) & 0x7)
 229 #define         NRECMEMB                0xC0
 230 #define                 NREC_CAS(x)             (((x)>>16) & 0xFFFFFF)
 231 #define                 NREC_RAS(x)             ((x) & 0x7FFF)
 232 #define         NRECFGLOG               0xC4
 233 #define         NREEECFBDA              0xC8
 234 #define         NREEECFBDB              0xCC
 235 #define         NREEECFBDC              0xD0
 236 #define         NREEECFBDD              0xD4
 237 #define         NREEECFBDE              0xD8
 238 #define         REDMEMA                 0xDC
 239 #define         RECMEMA                 0xE2
 240 #define                 REC_BANK(x)             (((x)>>12) & 0x7)
 241 #define                 REC_RDWR(x)             (((x)>>11) & 1)
 242 #define                 REC_RANK(x)             (((x)>>8) & 0x7)
 243 #define         RECMEMB                 0xE4
 244 #define                 REC_CAS(x)              (((x)>>16) & 0xFFFFFF)
 245 #define                 REC_RAS(x)              ((x) & 0x7FFF)
 246 #define         RECFGLOG                0xE8
 247 #define         RECFBDA                 0xEC
 248 #define         RECFBDB                 0xF0
 249 #define         RECFBDC                 0xF4
 250 #define         RECFBDD                 0xF8
 251 #define         RECFBDE                 0xFC
 252
 253 /* OFFSETS for Function 2 */
 254
 255 /*
 256  * Device 21,
 257  * Function 0: Memory Map Branch 0
 258  *
 259  * Device 22,
 260  * Function 0: Memory Map Branch 1
 261  */
 262 #define PCI_DEVICE_ID_I5000_BRANCH_0    0x25F5
 263 #define PCI_DEVICE_ID_I5000_BRANCH_1    0x25F6
 264
 265 #define AMB_PRESENT_0   0x64
 266 #define AMB_PRESENT_1   0x66
 267 #define MTR0            0x80
 268 #define MTR1            0x84
 269 #define MTR2            0x88
 270 #define MTR3            0x8C
 271
 272 #define NUM_MTRS                4
 273 #define CHANNELS_PER_BRANCH     (2)
 274
 275 /* Defines to extract the vaious fields from the
 276  *      MTRx - Memory Technology Registers
 277  */
 278 #define MTR_DIMMS_PRESENT(mtr)          ((mtr) & (0x1 << 8))
 279 #define MTR_DRAM_WIDTH(mtr)             ((((mtr) >> 6) & 0x1) ? 8 : 4)
 280 #define MTR_DRAM_BANKS(mtr)             ((((mtr) >> 5) & 0x1) ? 8 : 4)
 281 #define MTR_DRAM_BANKS_ADDR_BITS(mtr)   ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
 282 #define MTR_DIMM_RANK(mtr)              (((mtr) >> 4) & 0x1)
 283 #define MTR_DIMM_RANK_ADDR_BITS(mtr)    (MTR_DIMM_RANK(mtr) ? 2 : 1)
 284 #define MTR_DIMM_ROWS(mtr)              (((mtr) >> 2) & 0x3)
 285 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)    (MTR_DIMM_ROWS(mtr) + 13)
 286 #define MTR_DIMM_COLS(mtr)              ((mtr) & 0x3)
 287 #define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
 288
 289 #ifdef CONFIG_EDAC_DEBUG
 290 static char *numrow_toString[] = {
 291         "8,192 - 13 rows",
 292         "16,384 - 14 rows",
 293         "32,768 - 15 rows",
 294         "reserved"
 295 };
 296
 297 static char *numcol_toString[] = {
 298         "1,024 - 10 columns",
 299         "2,048 - 11 columns",
 300         "4,096 - 12 columns",
 301         "reserved"
 302 };
 303 #endif
 304
 305 /* enables the report of miscellaneous messages as CE errors - default off */
 306 static int misc_messages;
 307
 308 /* Enumeration of supported devices */
 309 enum i5000_chips {
 310         I5000P = 0,
 311         I5000V = 1,             /* future */
 312         I5000X = 2              /* future */
 313 };
 314
 315 /* Device name and register DID (Device ID) */
 316 struct i5000_dev_info {
 317         const char *ctl_name;   /* name for this device */
 318         u16 fsb_mapping_errors; /* DID for the branchmap,control */
 319 };
 320
 321 /* Table of devices attributes supported by this driver */
 322 static const struct i5000_dev_info i5000_devs[] = {
 323         [I5000P] = {
 324                 .ctl_name = "I5000",
 325                 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
 326         },
 327 };
 328
 329 struct i5000_dimm_info {
 330         int megabytes;          /* size, 0 means not present  */
 331         int dual_rank;
 332 };
 333
 334 #define MAX_CHANNELS    6       /* max possible channels */
 335 #define MAX_CSROWS      (8*2)   /* max possible csrows per channel */
 336
 337 /* driver private data structure */
 338 struct i5000_pvt {
 339         struct pci_dev *system_address; /* 16.0 */
 340         struct pci_dev *branchmap_werrors;      /* 16.1 */
 341         struct pci_dev *fsb_error_regs; /* 16.2 */
 342         struct pci_dev *branch_0;       /* 21.0 */
 343         struct pci_dev *branch_1;       /* 22.0 */
 344
 345         u16 tolm;               /* top of low memory */
 346         u64 ambase;             /* AMB BAR */
 347
 348         u16 mir0, mir1, mir2;
 349
 350         u16 b0_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
 351         u16 b0_ambpresent0;     /* Branch 0, Channel 0 */
 352         u16 b0_ambpresent1;     /* Brnach 0, Channel 1 */
 353
 354         u16 b1_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
 355         u16 b1_ambpresent0;     /* Branch 1, Channel 8 */
 356         u16 b1_ambpresent1;     /* Branch 1, Channel 1 */
 357
 358         /* DIMM information matrix, allocating architecture maximums */
 359         struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
 360
 361         /* Actual values for this controller */
 362         int maxch;              /* Max channels */
 363         int maxdimmperch;       /* Max DIMMs per channel */
 364 };
 365
 366 /* I5000 MCH error information retrieved from Hardware */
 367 struct i5000_error_info {
 368
 369         /* These registers are always read from the MC */
 370         u32 ferr_fat_fbd;       /* First Errors Fatal */
 371         u32 nerr_fat_fbd;       /* Next Errors Fatal */
 372         u32 ferr_nf_fbd;        /* First Errors Non-Fatal */
 373         u32 nerr_nf_fbd;        /* Next Errors Non-Fatal */
 374
 375         /* These registers are input ONLY if there was a Recoverable  Error */
 376         u32 redmemb;            /* Recoverable Mem Data Error log B */
 377         u16 recmema;            /* Recoverable Mem Error log A */
 378         u32 recmemb;            /* Recoverable Mem Error log B */
 379
 380         /* These registers are input ONLY if there was a
 381          * Non-Recoverable Error */
 382         u16 nrecmema;           /* Non-Recoverable Mem log A */
 383         u16 nrecmemb;           /* Non-Recoverable Mem log B */
 384
 385 };
 386
 387 static struct edac_pci_ctl_info *i5000_pci;
 388
 389 /*
 390  *      i5000_get_error_info    Retrieve the hardware error information from
 391  *                              the hardware and cache it in the 'info'
 392  *                              structure
 393  */
 394 static void i5000_get_error_info(struct mem_ctl_info *mci,
 395                                  struct i5000_error_info *info)
 396 {
 397         struct i5000_pvt *pvt;
 398         u32 value;
 399
 400         pvt = mci->pvt_info;
 401
 402         /* read in the 1st FATAL error register */
 403         pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
 404
 405         /* Mask only the bits that the doc says are valid
 406          */
 407         value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
 408
 409         /* If there is an error, then read in the */
 410         /* NEXT FATAL error register and the Memory Error Log Register A */
 411         if (value & FERR_FAT_MASK) {
 412                 info->ferr_fat_fbd = value;
 413
 414                 /* harvest the various error data we need */
 415                 pci_read_config_dword(pvt->branchmap_werrors,
 416                                 NERR_FAT_FBD, &info->nerr_fat_fbd);
 417                 pci_read_config_word(pvt->branchmap_werrors,
 418                                 NRECMEMA, &info->nrecmema);
 419                 pci_read_config_word(pvt->branchmap_werrors,
 420                                 NRECMEMB, &info->nrecmemb);
 421
 422                 /* Clear the error bits, by writing them back */
 423                 pci_write_config_dword(pvt->branchmap_werrors,
 424                                 FERR_FAT_FBD, value);
 425         } else {
 426                 info->ferr_fat_fbd = 0;
 427                 info->nerr_fat_fbd = 0;
 428                 info->nrecmema = 0;
 429                 info->nrecmemb = 0;
 430         }
 431
 432         /* read in the 1st NON-FATAL error register */
 433         pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
 434
 435         /* If there is an error, then read in the 1st NON-FATAL error
 436          * register as well */
 437         if (value & FERR_NF_MASK) {
 438                 info->ferr_nf_fbd = value;
 439
 440                 /* harvest the various error data we need */
 441                 pci_read_config_dword(pvt->branchmap_werrors,
 442                                 NERR_NF_FBD, &info->nerr_nf_fbd);
 443                 pci_read_config_word(pvt->branchmap_werrors,
 444                                 RECMEMA, &info->recmema);
 445                 pci_read_config_dword(pvt->branchmap_werrors,
 446                                 RECMEMB, &info->recmemb);
 447                 pci_read_config_dword(pvt->branchmap_werrors,
 448                                 REDMEMB, &info->redmemb);
 449
 450                 /* Clear the error bits, by writing them back */
 451                 pci_write_config_dword(pvt->branchmap_werrors,
 452                                 FERR_NF_FBD, value);
 453         } else {
 454                 info->ferr_nf_fbd = 0;
 455                 info->nerr_nf_fbd = 0;
 456                 info->recmema = 0;
 457                 info->recmemb = 0;
 458                 info->redmemb = 0;
 459         }
 460 }
 461
 462 /*
 463  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
 464  *                                      struct i5000_error_info *info,
 465  *                                      int handle_errors);
 466  *
 467  *      handle the Intel FATAL errors, if any
 468  */
 469 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
 470                                         struct i5000_error_info *info,
 471                                         int handle_errors)
 472 {
 473         char msg[EDAC_MC_LABEL_LEN + 1 + 160];
 474         char *specific = NULL;
 475         u32 allErrors;
 476         int branch;
 477         int channel;
 478         int bank;
 479         int rank;
 480         int rdwr;
 481         int ras, cas;
 482
 483         /* mask off the Error bits that are possible */
 484         allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
 485         if (!allErrors)
 486                 return;         /* if no error, return now */
 487
 488         branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
 489         channel = branch;
 490
 491         /* Use the NON-Recoverable macros to extract data */
 492         bank = NREC_BANK(info->nrecmema);
 493         rank = NREC_RANK(info->nrecmema);
 494         rdwr = NREC_RDWR(info->nrecmema);
 495         ras = NREC_RAS(info->nrecmemb);
 496         cas = NREC_CAS(info->nrecmemb);
 497
 498         debugf0("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
 499                 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
 500                 rank, channel, channel + 1, branch >> 1, bank,
 501                 rdwr ? "Write" : "Read", ras, cas);
 502
 503         /* Only 1 bit will be on */
 504         switch (allErrors) {
 505         case FERR_FAT_M1ERR:
 506                 specific = "Alert on non-redundant retry or fast "
 507                                 "reset timeout";
 508                 break;
 509         case FERR_FAT_M2ERR:
 510                 specific = "Northbound CRC error on non-redundant "
 511                                 "retry";
 512                 break;
 513         case FERR_FAT_M3ERR:
 514                 {
 515                 static int done;
 516
 517                 /*
 518                  * This error is generated to inform that the intelligent
 519                  * throttling is disabled and the temperature passed the
 520                  * specified middle point. Since this is something the BIOS
 521                  * should take care of, we'll warn only once to avoid
 522                  * worthlessly flooding the log.
 523                  */
 524                 if (done)
 525                         return;
 526                 done++;
 527
 528                 specific = ">Tmid Thermal event with intelligent "
 529                            "throttling disabled";
 530                 }
 531                 break;
 532         }
 533
 534         /* Form out message */
 535         snprintf(msg, sizeof(msg),
 536                  "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
 537                  bank, ras, cas, allErrors, specific);
 538
 539         /* Call the helper to output message */
 540         edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
 541                              branch >> 1, -1, rank,
 542                              rdwr ? "Write error" : "Read error",
 543                              msg, NULL);
 544 }
 545
 546 /*
 547  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
 548  *                              struct i5000_error_info *info,
 549  *                              int handle_errors);
 550  *
 551  *      handle the Intel NON-FATAL errors, if any
 552  */
 553 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
 554                                         struct i5000_error_info *info,
 555                                         int handle_errors)
 556 {
 557         char msg[EDAC_MC_LABEL_LEN + 1 + 170];
 558         char *specific = NULL;
 559         u32 allErrors;
 560         u32 ue_errors;
 561         u32 ce_errors;
 562         u32 misc_errors;
 563         int branch;
 564         int channel;
 565         int bank;
 566         int rank;
 567         int rdwr;
 568         int ras, cas;
 569
 570         /* mask off the Error bits that are possible */
 571         allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
 572         if (!allErrors)
 573                 return;         /* if no error, return now */
 574
 575         /* ONLY ONE of the possible error bits will be set, as per the docs */
 576         ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
 577         if (ue_errors) {
 578                 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
 579
 580                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 581
 582                 /*
 583                  * According with i5000 datasheet, bit 28 has no significance
 584                  * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
 585                  */
 586                 channel = branch & 2;
 587
 588                 bank = NREC_BANK(info->nrecmema);
 589                 rank = NREC_RANK(info->nrecmema);
 590                 rdwr = NREC_RDWR(info->nrecmema);
 591                 ras = NREC_RAS(info->nrecmemb);
 592                 cas = NREC_CAS(info->nrecmemb);
 593
 594                 debugf0
 595                         ("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
 596                         "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
 597                         rank, channel, channel + 1, branch >> 1, bank,
 598                         rdwr ? "Write" : "Read", ras, cas);
 599
 600                 switch (ue_errors) {
 601                 case FERR_NF_M12ERR:
 602                         specific = "Non-Aliased Uncorrectable Patrol Data ECC";
 603                         break;
 604                 case FERR_NF_M11ERR:
 605                         specific = "Non-Aliased Uncorrectable Spare-Copy "
 606                                         "Data ECC";
 607                         break;
 608                 case FERR_NF_M10ERR:
 609                         specific = "Non-Aliased Uncorrectable Mirrored Demand "
 610                                         "Data ECC";
 611                         break;
 612                 case FERR_NF_M9ERR:
 613                         specific = "Non-Aliased Uncorrectable Non-Mirrored "
 614                                         "Demand Data ECC";
 615                         break;
 616                 case FERR_NF_M8ERR:
 617                         specific = "Aliased Uncorrectable Patrol Data ECC";
 618                         break;
 619                 case FERR_NF_M7ERR:
 620                         specific = "Aliased Uncorrectable Spare-Copy Data ECC";
 621                         break;
 622                 case FERR_NF_M6ERR:
 623                         specific = "Aliased Uncorrectable Mirrored Demand "
 624                                         "Data ECC";
 625                         break;
 626                 case FERR_NF_M5ERR:
 627                         specific = "Aliased Uncorrectable Non-Mirrored Demand "
 628                                         "Data ECC";
 629                         break;
 630                 case FERR_NF_M4ERR:
 631                         specific = "Uncorrectable Data ECC on Replay";
 632                         break;
 633                 }
 634
 635                 /* Form out message */
 636                 snprintf(msg, sizeof(msg),
 637                          "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
 638                          rank, bank, ras, cas, ue_errors, specific);
 639
 640                 /* Call the helper to output message */
 641                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
 642                                 channel >> 1, -1, rank,
 643                                 rdwr ? "Write error" : "Read error",
 644                                 msg, NULL);
 645         }
 646
 647         /* Check correctable errors */
 648         ce_errors = allErrors & FERR_NF_CORRECTABLE;
 649         if (ce_errors) {
 650                 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
 651
 652                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 653
 654                 channel = 0;
 655                 if (REC_ECC_LOCATOR_ODD(info->redmemb))
 656                         channel = 1;
 657
 658                 /* Convert channel to be based from zero, instead of
 659                  * from branch base of 0 */
 660                 channel += branch;
 661
 662                 bank = REC_BANK(info->recmema);
 663                 rank = REC_RANK(info->recmema);
 664                 rdwr = REC_RDWR(info->recmema);
 665                 ras = REC_RAS(info->recmemb);
 666                 cas = REC_CAS(info->recmemb);
 667
 668                 debugf0("\t\tCSROW= %d Channel= %d  (Branch %d "
 669                         "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
 670                         rank, channel, branch >> 1, bank,
 671                         rdwr ? "Write" : "Read", ras, cas);
 672
 673                 switch (ce_errors) {
 674                 case FERR_NF_M17ERR:
 675                         specific = "Correctable Non-Mirrored Demand Data ECC";
 676                         break;
 677                 case FERR_NF_M18ERR:
 678                         specific = "Correctable Mirrored Demand Data ECC";
 679                         break;
 680                 case FERR_NF_M19ERR:
 681                         specific = "Correctable Spare-Copy Data ECC";
 682                         break;
 683                 case FERR_NF_M20ERR:
 684                         specific = "Correctable Patrol Data ECC";
 685                         break;
 686                 }
 687
 688                 /* Form out message */
 689                 snprintf(msg, sizeof(msg),
 690                          "Rank=%d Bank=%d RDWR=%s RAS=%d "
 691                          "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
 692                          rdwr ? "Write" : "Read", ras, cas, ce_errors,
 693                          specific);
 694
 695                 /* Call the helper to output message */
 696                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
 697                                 channel >> 1, channel % 2, rank,
 698                                 rdwr ? "Write error" : "Read error",
 699                                 msg, NULL);
 700         }
 701
 702         if (!misc_messages)
 703                 return;
 704
 705         misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
 706                                    FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
 707         if (misc_errors) {
 708                 switch (misc_errors) {
 709                 case FERR_NF_M13ERR:
 710                         specific = "Non-Retry or Redundant Retry FBD Memory "
 711                                         "Alert or Redundant Fast Reset Timeout";
 712                         break;
 713                 case FERR_NF_M14ERR:
 714                         specific = "Non-Retry or Redundant Retry FBD "
 715                                         "Configuration Alert";
 716                         break;
 717                 case FERR_NF_M15ERR:
 718                         specific = "Non-Retry or Redundant Retry FBD "
 719                                         "Northbound CRC error on read data";
 720                         break;
 721                 case FERR_NF_M21ERR:
 722                         specific = "FBD Northbound CRC error on "
 723                                         "FBD Sync Status";
 724                         break;
 725                 case FERR_NF_M22ERR:
 726                         specific = "SPD protocol error";
 727                         break;
 728                 case FERR_NF_M27ERR:
 729                         specific = "DIMM-spare copy started";
 730                         break;
 731                 case FERR_NF_M28ERR:
 732                         specific = "DIMM-spare copy completed";
 733                         break;
 734                 }
 735                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 736
 737                 /* Form out message */
 738                 snprintf(msg, sizeof(msg),
 739                          "Err=%#x (%s)", misc_errors, specific);
 740
 741                 /* Call the helper to output message */
 742                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
 743                                 branch >> 1, -1, -1,
 744                                 "Misc error", msg, NULL);
 745         }
 746 }
 747
 748 /*
 749  *      i5000_process_error_info        Process the error info that is
 750  *      in the 'info' structure, previously retrieved from hardware
 751  */
 752 static void i5000_process_error_info(struct mem_ctl_info *mci,
 753                                 struct i5000_error_info *info,
 754                                 int handle_errors)
 755 {
 756         /* First handle any fatal errors that occurred */
 757         i5000_process_fatal_error_info(mci, info, handle_errors);
 758
 759         /* now handle any non-fatal errors that occurred */
 760         i5000_process_nonfatal_error_info(mci, info, handle_errors);
 761 }
 762
 763 /*
 764  *      i5000_clear_error       Retrieve any error from the hardware
 765  *                              but do NOT process that error.
 766  *                              Used for 'clearing' out of previous errors
 767  *                              Called by the Core module.
 768  */
 769 static void i5000_clear_error(struct mem_ctl_info *mci)
 770 {
 771         struct i5000_error_info info;
 772
 773         i5000_get_error_info(mci, &info);
 774 }
 775
 776 /*
 777  *      i5000_check_error       Retrieve and process errors reported by the
 778  *                              hardware. Called by the Core module.
 779  */
 780 static void i5000_check_error(struct mem_ctl_info *mci)
 781 {
 782         struct i5000_error_info info;
 783         debugf4("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
 784         i5000_get_error_info(mci, &info);
 785         i5000_process_error_info(mci, &info, 1);
 786 }
 787
 788 /*
 789  *      i5000_get_devices       Find and perform 'get' operation on the MCH's
 790  *                      device/functions we want to reference for this driver
 791  *
 792  *                      Need to 'get' device 16 func 1 and func 2
 793  */
 794 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
 795 {
 796         //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
 797         struct i5000_pvt *pvt;
 798         struct pci_dev *pdev;
 799
 800         pvt = mci->pvt_info;
 801
 802         /* Attempt to 'get' the MCH register we want */
 803         pdev = NULL;
 804         while (1) {
 805                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 806                                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
 807
 808                 /* End of list, leave */
 809                 if (pdev == NULL) {
 810                         i5000_printk(KERN_ERR,
 811                                 "'system address,Process Bus' "
 812                                 "device not found:"
 813                                 "vendor 0x%x device 0x%x FUNC 1 "
 814                                 "(broken BIOS?)\n",
 815                                 PCI_VENDOR_ID_INTEL,
 816                                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
 817
 818                         return 1;
 819                 }
 820
 821                 /* Scan for device 16 func 1 */
 822                 if (PCI_FUNC(pdev->devfn) == 1)
 823                         break;
 824         }
 825
 826         pvt->branchmap_werrors = pdev;
 827
 828         /* Attempt to 'get' the MCH register we want */
 829         pdev = NULL;
 830         while (1) {
 831                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 832                                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
 833
 834                 if (pdev == NULL) {
 835                         i5000_printk(KERN_ERR,
 836                                 "MC: 'branchmap,control,errors' "
 837                                 "device not found:"
 838                                 "vendor 0x%x device 0x%x Func 2 "
 839                                 "(broken BIOS?)\n",
 840                                 PCI_VENDOR_ID_INTEL,
 841                                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
 842
 843                         pci_dev_put(pvt->branchmap_werrors);
 844                         return 1;
 845                 }
 846
 847                 /* Scan for device 16 func 1 */
 848                 if (PCI_FUNC(pdev->devfn) == 2)
 849                         break;
 850         }
 851
 852         pvt->fsb_error_regs = pdev;
 853
 854         debugf1("System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
 855                 pci_name(pvt->system_address),
 856                 pvt->system_address->vendor, pvt->system_address->device);
 857         debugf1("Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
 858                 pci_name(pvt->branchmap_werrors),
 859                 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
 860         debugf1("FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
 861                 pci_name(pvt->fsb_error_regs),
 862                 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
 863
 864         pdev = NULL;
 865         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 866                         PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
 867
 868         if (pdev == NULL) {
 869                 i5000_printk(KERN_ERR,
 870                         "MC: 'BRANCH 0' device not found:"
 871                         "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
 872                         PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
 873
 874                 pci_dev_put(pvt->branchmap_werrors);
 875                 pci_dev_put(pvt->fsb_error_regs);
 876                 return 1;
 877         }
 878
 879         pvt->branch_0 = pdev;
 880
 881         /* If this device claims to have more than 2 channels then
 882          * fetch Branch 1's information
 883          */
 884         if (pvt->maxch >= CHANNELS_PER_BRANCH) {
 885                 pdev = NULL;
 886                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 887                                 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
 888
 889                 if (pdev == NULL) {
 890                         i5000_printk(KERN_ERR,
 891                                 "MC: 'BRANCH 1' device not found:"
 892                                 "vendor 0x%x device 0x%x Func 0 "
 893                                 "(broken BIOS?)\n",
 894                                 PCI_VENDOR_ID_INTEL,
 895                                 PCI_DEVICE_ID_I5000_BRANCH_1);
 896
 897                         pci_dev_put(pvt->branchmap_werrors);
 898                         pci_dev_put(pvt->fsb_error_regs);
 899                         pci_dev_put(pvt->branch_0);
 900                         return 1;
 901                 }
 902
 903                 pvt->branch_1 = pdev;
 904         }
 905
 906         return 0;
 907 }
 908
 909 /*
 910  *      i5000_put_devices       'put' all the devices that we have
 911  *                              reserved via 'get'
 912  */
 913 static void i5000_put_devices(struct mem_ctl_info *mci)
 914 {
 915         struct i5000_pvt *pvt;
 916
 917         pvt = mci->pvt_info;
 918
 919         pci_dev_put(pvt->branchmap_werrors);    /* FUNC 1 */
 920         pci_dev_put(pvt->fsb_error_regs);       /* FUNC 2 */
 921         pci_dev_put(pvt->branch_0);     /* DEV 21 */
 922
 923         /* Only if more than 2 channels do we release the second branch */
 924         if (pvt->maxch >= CHANNELS_PER_BRANCH)
 925                 pci_dev_put(pvt->branch_1);     /* DEV 22 */
 926 }
 927
 928 /*
 929  *      determine_amb_resent
 930  *
 931  *              the information is contained in NUM_MTRS different registers
 932  *              determineing which of the NUM_MTRS requires knowing
 933  *              which channel is in question
 934  *
 935  *      2 branches, each with 2 channels
 936  *              b0_ambpresent0 for channel '0'
 937  *              b0_ambpresent1 for channel '1'
 938  *              b1_ambpresent0 for channel '2'
 939  *              b1_ambpresent1 for channel '3'
 940  */
 941 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
 942 {
 943         int amb_present;
 944
 945         if (channel < CHANNELS_PER_BRANCH) {
 946                 if (channel & 0x1)
 947                         amb_present = pvt->b0_ambpresent1;
 948                 else
 949                         amb_present = pvt->b0_ambpresent0;
 950         } else {
 951                 if (channel & 0x1)
 952                         amb_present = pvt->b1_ambpresent1;
 953                 else
 954                         amb_present = pvt->b1_ambpresent0;
 955         }
 956
 957         return amb_present;
 958 }
 959
 960 /*
 961  * determine_mtr(pvt, csrow, channel)
 962  *
 963  *      return the proper MTR register as determine by the csrow and channel desired
 964  */
 965 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
 966 {
 967         int mtr;
 968
 969         if (channel < CHANNELS_PER_BRANCH)
 970                 mtr = pvt->b0_mtr[csrow >> 1];
 971         else
 972                 mtr = pvt->b1_mtr[csrow >> 1];
 973
 974         return mtr;
 975 }
 976
 977 /*
 978  */
 979 static void decode_mtr(int slot_row, u16 mtr)
 980 {
 981         int ans;
 982
 983         ans = MTR_DIMMS_PRESENT(mtr);
 984
 985         debugf2("\tMTR%d=0x%x:  DIMMs are %s\n", slot_row, mtr,
 986                 ans ? "Present" : "NOT Present");
 987         if (!ans)
 988                 return;
 989
 990         debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
 991         debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
 992         debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
 993         debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
 994         debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
 995 }
 996
 997 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
 998                         struct i5000_dimm_info *dinfo)
 999 {
1000         int mtr;
1001         int amb_present_reg;
1002         int addrBits;
1003
1004         mtr = determine_mtr(pvt, csrow, channel);
1005         if (MTR_DIMMS_PRESENT(mtr)) {
1006                 amb_present_reg = determine_amb_present_reg(pvt, channel);
1007
1008                 /* Determine if there is  a  DIMM present in this DIMM slot */
1009                 if (amb_present_reg & (1 << (csrow >> 1))) {
1010                         dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1011
1012                         if (!((dinfo->dual_rank == 0) &&
1013                                 ((csrow & 0x1) == 0x1))) {
1014                                 /* Start with the number of bits for a Bank
1015                                  * on the DRAM */
1016                                 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1017                                 /* Add thenumber of ROW bits */
1018                                 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1019                                 /* add the number of COLUMN bits */
1020                                 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1021
1022                                 addrBits += 6;  /* add 64 bits per DIMM */
1023                                 addrBits -= 20; /* divide by 2^^20 */
1024                                 addrBits -= 3;  /* 8 bits per bytes */
1025
1026                                 dinfo->megabytes = 1 << addrBits;
1027                         }
1028                 }
1029         }
1030 }
1031
1032 /*
1033  *      calculate_dimm_size
1034  *
1035  *      also will output a DIMM matrix map, if debug is enabled, for viewing
1036  *      how the DIMMs are populated
1037  */
1038 static void calculate_dimm_size(struct i5000_pvt *pvt)
1039 {
1040         struct i5000_dimm_info *dinfo;
1041         int csrow, max_csrows;
1042         char *p, *mem_buffer;
1043         int space, n;
1044         int channel;
1045
1046         /* ================= Generate some debug output ================= */
1047         space = PAGE_SIZE;
1048         mem_buffer = p = kmalloc(space, GFP_KERNEL);
1049         if (p == NULL) {
1050                 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
1051                         __FILE__, __func__);
1052                 return;
1053         }
1054
1055         n = snprintf(p, space, "\n");
1056         p += n;
1057         space -= n;
1058
1059         /* Scan all the actual CSROWS (which is # of DIMMS * 2)
1060          * and calculate the information for each DIMM
1061          * Start with the highest csrow first, to display it first
1062          * and work toward the 0th csrow
1063          */
1064         max_csrows = pvt->maxdimmperch * 2;
1065         for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
1066
1067                 /* on an odd csrow, first output a 'boundary' marker,
1068                  * then reset the message buffer  */
1069                 if (csrow & 0x1) {
1070                         n = snprintf(p, space, "---------------------------"
1071                                 "--------------------------------");
1072                         p += n;
1073                         space -= n;
1074                         debugf2("%s\n", mem_buffer);
1075                         p = mem_buffer;
1076                         space = PAGE_SIZE;
1077                 }
1078                 n = snprintf(p, space, "csrow %2d    ", csrow);
1079                 p += n;
1080                 space -= n;
1081
1082                 for (channel = 0; channel < pvt->maxch; channel++) {
1083                         dinfo = &pvt->dimm_info[csrow][channel];
1084                         handle_channel(pvt, csrow, channel, dinfo);
1085                         n = snprintf(p, space, "%4d MB   | ", dinfo->megabytes);
1086                         p += n;
1087                         space -= n;
1088                 }
1089                 n = snprintf(p, space, "\n");
1090                 p += n;
1091                 space -= n;
1092         }
1093
1094         /* Output the last bottom 'boundary' marker */
1095         n = snprintf(p, space, "---------------------------"
1096                 "--------------------------------\n");
1097         p += n;
1098         space -= n;
1099
1100         /* now output the 'channel' labels */
1101         n = snprintf(p, space, "            ");
1102         p += n;
1103         space -= n;
1104         for (channel = 0; channel < pvt->maxch; channel++) {
1105                 n = snprintf(p, space, "channel %d | ", channel);
1106                 p += n;
1107                 space -= n;
1108         }
1109         n = snprintf(p, space, "\n");
1110         p += n;
1111         space -= n;
1112
1113         /* output the last message and free buffer */
1114         debugf2("%s\n", mem_buffer);
1115         kfree(mem_buffer);
1116 }
1117
1118 /*
1119  *      i5000_get_mc_regs       read in the necessary registers and
1120  *                              cache locally
1121  *
1122  *                      Fills in the private data members
1123  */
1124 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1125 {
1126         struct i5000_pvt *pvt;
1127         u32 actual_tolm;
1128         u16 limit;
1129         int slot_row;
1130         int maxch;
1131         int maxdimmperch;
1132         int way0, way1;
1133
1134         pvt = mci->pvt_info;
1135
1136         pci_read_config_dword(pvt->system_address, AMBASE,
1137                         (u32 *) & pvt->ambase);
1138         pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1139                         ((u32 *) & pvt->ambase) + sizeof(u32));
1140
1141         maxdimmperch = pvt->maxdimmperch;
1142         maxch = pvt->maxch;
1143
1144         debugf2("AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",
1145                 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1146
1147         /* Get the Branch Map regs */
1148         pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1149         pvt->tolm >>= 12;
1150         debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1151                 pvt->tolm);
1152
1153         actual_tolm = pvt->tolm << 28;
1154         debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1155
1156         pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1157         pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1158         pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1159
1160         /* Get the MIR[0-2] regs */
1161         limit = (pvt->mir0 >> 4) & 0x0FFF;
1162         way0 = pvt->mir0 & 0x1;
1163         way1 = pvt->mir0 & 0x2;
1164         debugf2("MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1165         limit = (pvt->mir1 >> 4) & 0x0FFF;
1166         way0 = pvt->mir1 & 0x1;
1167         way1 = pvt->mir1 & 0x2;
1168         debugf2("MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1169         limit = (pvt->mir2 >> 4) & 0x0FFF;
1170         way0 = pvt->mir2 & 0x1;
1171         way1 = pvt->mir2 & 0x2;
1172         debugf2("MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1173
1174         /* Get the MTR[0-3] regs */
1175         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1176                 int where = MTR0 + (slot_row * sizeof(u32));
1177
1178                 pci_read_config_word(pvt->branch_0, where,
1179                                 &pvt->b0_mtr[slot_row]);
1180
1181                 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1182                         pvt->b0_mtr[slot_row]);
1183
1184                 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1185                         pci_read_config_word(pvt->branch_1, where,
1186                                         &pvt->b1_mtr[slot_row]);
1187                         debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1188                                 where, pvt->b1_mtr[slot_row]);
1189                 } else {
1190                         pvt->b1_mtr[slot_row] = 0;
1191                 }
1192         }
1193
1194         /* Read and dump branch 0's MTRs */
1195         debugf2("\nMemory Technology Registers:\n");
1196         debugf2("   Branch 0:\n");
1197         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1198                 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1199         }
1200         pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1201                         &pvt->b0_ambpresent0);
1202         debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1203         pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1204                         &pvt->b0_ambpresent1);
1205         debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1206
1207         /* Only if we have 2 branchs (4 channels) */
1208         if (pvt->maxch < CHANNELS_PER_BRANCH) {
1209                 pvt->b1_ambpresent0 = 0;
1210                 pvt->b1_ambpresent1 = 0;
1211         } else {
1212                 /* Read and dump  branch 1's MTRs */
1213                 debugf2("   Branch 1:\n");
1214                 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1215                         decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1216                 }
1217                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1218                                 &pvt->b1_ambpresent0);
1219                 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1220                         pvt->b1_ambpresent0);
1221                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1222                                 &pvt->b1_ambpresent1);
1223                 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1224                         pvt->b1_ambpresent1);
1225         }
1226
1227         /* Go and determine the size of each DIMM and place in an
1228          * orderly matrix */
1229         calculate_dimm_size(pvt);
1230 }
1231
1232 /*
1233  *      i5000_init_csrows       Initialize the 'csrows' table within
1234  *                              the mci control structure with the
1235  *                              addressing of memory.
1236  *
1237  *      return:
1238  *              0       success
1239  *              1       no actual memory found on this MC
1240  */
1241 static int i5000_init_csrows(struct mem_ctl_info *mci)
1242 {
1243         struct i5000_pvt *pvt;
1244         struct csrow_info *p_csrow;
1245         struct dimm_info *dimm;
1246         int empty, channel_count;
1247         int max_csrows;
1248         int mtr, mtr1;
1249         int csrow_megs;
1250         int channel;
1251         int csrow;
1252
1253         pvt = mci->pvt_info;
1254
1255         channel_count = pvt->maxch;
1256         max_csrows = pvt->maxdimmperch * 2;
1257
1258         empty = 1;              /* Assume NO memory */
1259
1260         /*
1261          * TODO: it would be better to not use csrow here, filling
1262          * directly the dimm_info structs, based on branch, channel, dim number
1263          */
1264         for (csrow = 0; csrow < max_csrows; csrow++) {
1265                 p_csrow = &mci->csrows[csrow];
1266
1267                 p_csrow->csrow_idx = csrow;
1268
1269                 /* use branch 0 for the basis */
1270                 mtr = pvt->b0_mtr[csrow >> 1];
1271                 mtr1 = pvt->b1_mtr[csrow >> 1];
1272
1273                 /* if no DIMMS on this row, continue */
1274                 if (!MTR_DIMMS_PRESENT(mtr) && !MTR_DIMMS_PRESENT(mtr1))
1275                         continue;
1276
1277                 csrow_megs = 0;
1278                 for (channel = 0; channel < pvt->maxch; channel++) {
1279                         dimm = p_csrow->channels[channel].dimm;
1280                         csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1281                         dimm->grain = 8;
1282
1283                         /* Assume DDR2 for now */
1284                         dimm->mtype = MEM_FB_DDR2;
1285
1286                         /* ask what device type on this row */
1287                         if (MTR_DRAM_WIDTH(mtr))
1288                                 dimm->dtype = DEV_X8;
1289                         else
1290                                 dimm->dtype = DEV_X4;
1291
1292                         dimm->edac_mode = EDAC_S8ECD8ED;
1293                         dimm->nr_pages = (csrow_megs << 8) / pvt->maxch;
1294                 }
1295
1296                 empty = 0;
1297         }
1298
1299         return empty;
1300 }
1301
1302 /*
1303  *      i5000_enable_error_reporting
1304  *                      Turn on the memory reporting features of the hardware
1305  */
1306 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1307 {
1308         struct i5000_pvt *pvt;
1309         u32 fbd_error_mask;
1310
1311         pvt = mci->pvt_info;
1312
1313         /* Read the FBD Error Mask Register */
1314         pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1315                         &fbd_error_mask);
1316
1317         /* Enable with a '0' */
1318         fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1319
1320         pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1321                         fbd_error_mask);
1322 }
1323
1324 /*
1325  * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
1326  *
1327  *      ask the device how many channels are present and how many CSROWS
1328  *       as well
1329  */
1330 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1331                                         int *num_dimms_per_channel,
1332                                         int *num_channels)
1333 {
1334         u8 value;
1335
1336         /* Need to retrieve just how many channels and dimms per channel are
1337          * supported on this memory controller
1338          */
1339         pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1340         *num_dimms_per_channel = (int)value *2;
1341
1342         pci_read_config_byte(pdev, MAXCH, &value);
1343         *num_channels = (int)value;
1344 }
1345
1346 /*
1347  *      i5000_probe1    Probe for ONE instance of device to see if it is
1348  *                      present.
1349  *      return:
1350  *              0 for FOUND a device
1351  *              < 0 for error code
1352  */
1353 static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1354 {
1355         struct mem_ctl_info *mci;
1356         struct edac_mc_layer layers[3];
1357         struct i5000_pvt *pvt;
1358         int num_channels;
1359         int num_dimms_per_channel;
1360
1361         debugf0("MC: %s: %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1362                 __FILE__, __func__,
1363                 pdev->bus->number,
1364                 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1365
1366         /* We only are looking for func 0 of the set */
1367         if (PCI_FUNC(pdev->devfn) != 0)
1368                 return -ENODEV;
1369
1370         /* Ask the devices for the number of CSROWS and CHANNELS so
1371          * that we can calculate the memory resources, etc
1372          *
1373          * The Chipset will report what it can handle which will be greater
1374          * or equal to what the motherboard manufacturer will implement.
1375          *
1376          * As we don't have a motherboard identification routine to determine
1377          * actual number of slots/dimms per channel, we thus utilize the
1378          * resource as specified by the chipset. Thus, we might have
1379          * have more DIMMs per channel than actually on the mobo, but this
1380          * allows the driver to support up to the chipset max, without
1381          * some fancy mobo determination.
1382          */
1383         i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1384                                         &num_channels);
1385
1386         debugf0("MC: %s(): Number of Branches=2 Channels= %d  DIMMS= %d\n",
1387                 __func__, num_channels, num_dimms_per_channel);
1388
1389         /* allocate a new MC control structure */
1390         layers[0].type = EDAC_MC_LAYER_BRANCH;
1391         layers[0].size = 2;
1392         layers[0].is_virt_csrow = true;
1393         layers[1].type = EDAC_MC_LAYER_CHANNEL;
1394         layers[1].size = num_channels;
1395         layers[1].is_virt_csrow = false;
1396         layers[2].type = EDAC_MC_LAYER_SLOT;
1397         layers[2].size = num_dimms_per_channel;
1398         layers[2].is_virt_csrow = true;
1399         mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1400
1401         if (mci == NULL)
1402                 return -ENOMEM;
1403
1404         kobject_get(&mci->edac_mci_kobj);
1405         debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
1406
1407         mci->dev = &pdev->dev;  /* record ptr  to the generic device */
1408
1409         pvt = mci->pvt_info;
1410         pvt->system_address = pdev;     /* Record this device in our private */
1411         pvt->maxch = num_channels;
1412         pvt->maxdimmperch = num_dimms_per_channel;
1413
1414         /* 'get' the pci devices we want to reserve for our use */
1415         if (i5000_get_devices(mci, dev_idx))
1416                 goto fail0;
1417
1418         /* Time to get serious */
1419         i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1420
1421         mci->mc_idx = 0;
1422         mci->mtype_cap = MEM_FLAG_FB_DDR2;
1423         mci->edac_ctl_cap = EDAC_FLAG_NONE;
1424         mci->edac_cap = EDAC_FLAG_NONE;
1425         mci->mod_name = "i5000_edac.c";
1426         mci->mod_ver = I5000_REVISION;
1427         mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1428         mci->dev_name = pci_name(pdev);
1429         mci->ctl_page_to_phys = NULL;
1430
1431         /* Set the function pointer to an actual operation function */
1432         mci->edac_check = i5000_check_error;
1433
1434         /* initialize the MC control structure 'csrows' table
1435          * with the mapping and control information */
1436         if (i5000_init_csrows(mci)) {
1437                 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1438                         "    because i5000_init_csrows() returned nonzero "
1439                         "value\n");
1440                 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1441         } else {
1442                 debugf1("MC: Enable error reporting now\n");
1443                 i5000_enable_error_reporting(mci);
1444         }
1445
1446         /* add this new MC control structure to EDAC's list of MCs */
1447         if (edac_mc_add_mc(mci)) {
1448                 debugf0("MC: %s: %s(): failed edac_mc_add_mc()\n",
1449                         __FILE__, __func__);
1450                 /* FIXME: perhaps some code should go here that disables error
1451                  * reporting if we just enabled it
1452                  */
1453                 goto fail1;
1454         }
1455
1456         i5000_clear_error(mci);
1457
1458         /* allocating generic PCI control info */
1459         i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1460         if (!i5000_pci) {
1461                 printk(KERN_WARNING
1462                         "%s(): Unable to create PCI control\n",
1463                         __func__);
1464                 printk(KERN_WARNING
1465                         "%s(): PCI error report via EDAC not setup\n",
1466                         __func__);
1467         }
1468
1469         return 0;
1470
1471         /* Error exit unwinding stack */
1472 fail1:
1473
1474         i5000_put_devices(mci);
1475
1476 fail0:
1477         kobject_put(&mci->edac_mci_kobj);
1478         edac_mc_free(mci);
1479         return -ENODEV;
1480 }
1481
1482 /*
1483  *      i5000_init_one  constructor for one instance of device
1484  *
1485  *      returns:
1486  *              negative on error
1487  *              count (>= 0)
1488  */
1489 static int __devinit i5000_init_one(struct pci_dev *pdev,
1490                                 const struct pci_device_id *id)
1491 {
1492         int rc;
1493
1494         debugf0("MC: %s: %s()\n", __FILE__, __func__);
1495
1496         /* wake up device */
1497         rc = pci_enable_device(pdev);
1498         if (rc)
1499                 return rc;
1500
1501         /* now probe and enable the device */
1502         return i5000_probe1(pdev, id->driver_data);
1503 }
1504
1505 /*
1506  *      i5000_remove_one        destructor for one instance of device
1507  *
1508  */
1509 static void __devexit i5000_remove_one(struct pci_dev *pdev)
1510 {
1511         struct mem_ctl_info *mci;
1512
1513         debugf0("%s: %s()\n", __FILE__, __func__);
1514
1515         if (i5000_pci)
1516                 edac_pci_release_generic_ctl(i5000_pci);
1517
1518         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1519                 return;
1520
1521         /* retrieve references to resources, and free those resources */
1522         i5000_put_devices(mci);
1523         kobject_put(&mci->edac_mci_kobj);
1524         edac_mc_free(mci);
1525 }
1526
1527 /*
1528  *      pci_device_id   table for which devices we are looking for
1529  *
1530  *      The "E500P" device is the first device supported.
1531  */
1532 static DEFINE_PCI_DEVICE_TABLE(i5000_pci_tbl) = {
1533         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1534          .driver_data = I5000P},
1535
1536         {0,}                    /* 0 terminated list. */
1537 };
1538
1539 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1540
1541 /*
1542  *      i5000_driver    pci_driver structure for this module
1543  *
1544  */
1545 static struct pci_driver i5000_driver = {
1546         .name = KBUILD_BASENAME,
1547         .probe = i5000_init_one,
1548         .remove = __devexit_p(i5000_remove_one),
1549         .id_table = i5000_pci_tbl,
1550 };
1551
1552 /*
1553  *      i5000_init              Module entry function
1554  *                      Try to initialize this module for its devices
1555  */
1556 static int __init i5000_init(void)
1557 {
1558         int pci_rc;
1559
1560         debugf2("MC: %s: %s()\n", __FILE__, __func__);
1561
1562        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1563        opstate_init();
1564
1565         pci_rc = pci_register_driver(&i5000_driver);
1566
1567         return (pci_rc < 0) ? pci_rc : 0;
1568 }
1569
1570 /*
1571  *      i5000_exit()    Module exit function
1572  *                      Unregister the driver
1573  */
1574 static void __exit i5000_exit(void)
1575 {
1576         debugf2("MC: %s: %s()\n", __FILE__, __func__);
1577         pci_unregister_driver(&i5000_driver);
1578 }
1579
1580 module_init(i5000_init);
1581 module_exit(i5000_exit);
1582
1583 MODULE_LICENSE("GPL");
1584 MODULE_AUTHOR
1585     ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1586 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1587                 I5000_REVISION);
1588
1589 module_param(edac_op_state, int, 0444);
1590 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1591 module_param(misc_messages, int, 0444);
1592 MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1593