2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
10 * Red Hat Inc. http://www.redhat.com
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/pci_ids.h>
25 #include <linux/slab.h>
26 #include <linux/edac.h>
27 #include <linux/mmzone.h>
29 #include "edac_core.h"
32 * Alter this version for the I7300 module when modifications are made
34 #define I7300_REVISION " Ver: 1.0.0 " __DATE__
36 #define EDAC_MOD_STR "i7300_edac"
38 #define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
41 #define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
45 * Memory topology is organized as:
46 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
47 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
48 * Each channel can have to 8 DIMM sets (called as SLOTS)
49 * Slots should generally be filled in pairs
50 * Except on Single Channel mode of operation
51 * just slot 0/channel0 filled on this mode
52 * On normal operation mode, the two channels on a branch should be
53 * filled together for the same SLOT#
54 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
55 * channels on both branches should be filled
58 /* Limits for i7300 */
60 #define MAX_BRANCHES 2
61 #define MAX_CH_PER_BRANCH 2
62 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
65 #define to_channel(ch, branch) ((((branch)) << 1) | (ch))
67 #define to_csrow(slot, ch, branch) \
68 (to_channel(ch, branch) | ((slot) << 2))
72 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
73 * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
74 * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
75 * for device 21 (0,1).
78 /****************************************************
79 * i7300 Register definitions for memory enumberation
80 ****************************************************/
84 * Function 0: System Address (not documented)
85 * Function 1: Memory Branch Map, Control, Errors Register
88 /* OFFSETS for Function 0 */
89 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
90 #define MAXCH 0x56 /* Max Channel Number */
91 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
93 /* OFFSETS for Function 1 */
94 #define MC_SETTINGS 0x40
104 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
105 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
106 * seems that we cannot use this information directly for the same usage.
107 * Each memory slot may have up to 2 AMB interfaces, one for income and another
108 * for outcome interface to the next slot.
109 * For now, the driver just stores the AMB present registers, but rely only at
110 * the MTR info to detect memory.
111 * Datasheet is also not clear about how to map each AMBPRESENT registers to
112 * one of the 4 available channels.
114 #define AMBPRESENT_0 0x64
115 #define AMBPRESENT_1 0x66
117 const static u16 mtr_regs [MAX_SLOTS] = {
118 0x80, 0x84, 0x88, 0x8c,
119 0x82, 0x86, 0x8a, 0x8e
122 /* Defines to extract the vaious fields from the
123 * MTRx - Memory Technology Registers
125 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
126 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
127 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
128 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
129 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
130 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
131 #define MTR_DRAM_BANKS_ADDR_BITS 2
132 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
133 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
134 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
136 #ifdef CONFIG_EDAC_DEBUG
138 static const char *numrow_toString[] = {
146 static const char *numcol_toString[] = {
147 "1,024 - 10 columns",
148 "2,048 - 11 columns",
149 "4,096 - 12 columns",
154 /************************************************
155 * i7300 Register definitions for error detection
156 ************************************************/
158 * Device 16.2: Global Error Registers
161 #define FERR_GLOBAL_LO 0x40
162 static const char *ferr_global_name[] = {
163 [31] = "Internal MCH Fatal Error",
164 [30] = "Intel QuickData Technology Device Fatal Error",
165 [29] = "FSB1 Fatal Error",
166 [28] = "FSB0 Fatal Error",
167 [27] = "FBD Channel 3 Fatal Error",
168 [26] = "FBD Channel 2 Fatal Error",
169 [25] = "FBD Channel 1 Fatal Error",
170 [24] = "FBD Channel 0 Fatal Error",
171 [23] = "PCI Express Device 7Fatal Error",
172 [22] = "PCI Express Device 6 Fatal Error",
173 [21] = "PCI Express Device 5 Fatal Error",
174 [20] = "PCI Express Device 4 Fatal Error",
175 [19] = "PCI Express Device 3 Fatal Error",
176 [18] = "PCI Express Device 2 Fatal Error",
177 [17] = "PCI Express Device 1 Fatal Error",
178 [16] = "ESI Fatal Error",
179 [15] = "Internal MCH Non-Fatal Error",
180 [14] = "Intel QuickData Technology Device Non Fatal Error",
181 [13] = "FSB1 Non-Fatal Error",
182 [12] = "FSB 0 Non-Fatal Error",
183 [11] = "FBD Channel 3 Non-Fatal Error",
184 [10] = "FBD Channel 2 Non-Fatal Error",
185 [9] = "FBD Channel 1 Non-Fatal Error",
186 [8] = "FBD Channel 0 Non-Fatal Error",
187 [7] = "PCI Express Device 7 Non-Fatal Error",
188 [6] = "PCI Express Device 6 Non-Fatal Error",
189 [5] = "PCI Express Device 5 Non-Fatal Error",
190 [4] = "PCI Express Device 4 Non-Fatal Error",
191 [3] = "PCI Express Device 3 Non-Fatal Error",
192 [2] = "PCI Express Device 2 Non-Fatal Error",
193 [1] = "PCI Express Device 1 Non-Fatal Error",
194 [0] = "ESI Non-Fatal Error",
197 #define NERR_GLOBAL 0x44
198 static const char *nerr_global_name[] = {
199 [31] = "Internal MCH Fatal Error",
200 [30] = "Intel QuickData Technology Device Fatal Error",
201 [29] = "FSB1 Fatal Error",
202 [28] = "FSB0 Fatal Error",
203 [27] = "FSB2 Fatal Error",
204 [26] = "FSB3 Fatal Error",
206 [24] = "FBD Channel 0,1,2 or 3 Fatal Error",
207 [23] = "PCI Express Device 7 Fatal Error",
208 [22] = "PCI Express Device 6 Fatal Error",
209 [21] = "PCI Express Device 5 Fatal Error",
210 [20] = "PCI Express Device 4 Fatal Error",
211 [19] = "PCI Express Device 3 Fatal Error",
212 [18] = "PCI Express Device 2 Fatal Error",
213 [17] = "PCI Express Device 1 Fatal Error",
214 [16] = "ESI Fatal Error",
215 [15] = "Internal MCH Non-Fatal Error",
216 [14] = "Intel QuickData Technology Device Non Fatal Error",
217 [13] = "FSB1 Non-Fatal Error",
218 [12] = "FSB0 Non-Fatal Error",
219 [11] = "FSB2 Non-Fatal Error",
220 [10] = "FSB3 Non-Fatal Error",
222 [8] = "FBD Channel 0,1, 2 or 3 Non-Fatal Error",
223 [7] = "PCI Express Device 7 Non-Fatal Error",
224 [6] = "PCI Express Device 6 Non-Fatal Error",
225 [5] = "PCI Express Device 5 Non-Fatal Error",
226 [4] = "PCI Express Device 4 Non-Fatal Error",
227 [3] = "PCI Express Device 3 Non-Fatal Error",
228 [2] = "PCI Express Device 2 Non-Fatal Error",
229 [1] = "PCI Express Device 1 Non-Fatal Error",
230 [0] = "ESI Non-Fatal Error",
236 * Error indicator bits and masks
237 * Error masks are according with Table 5-17 of i7300 datasheet
241 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
242 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
243 EMASK_M3 = 1<<2, /* Reserved */
244 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
245 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
246 EMASK_M6 = 1<<5, /* Unsupported on i7300 */
247 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
248 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
249 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
250 EMASK_M10 = 1<<9, /* Unsupported on i7300 */
251 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
252 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
253 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
254 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
255 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
256 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
257 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
258 EMASK_M18 = 1<<17, /* Unsupported on i7300 */
259 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
260 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
261 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
262 EMASK_M22 = 1<<21, /* SPD protocol Error */
263 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
264 EMASK_M24 = 1<<23, /* Refresh error */
265 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
266 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
267 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
268 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
269 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
273 * Names to translate bit error into something useful
275 static const char *error_name[] = {
276 [0] = "Memory Write error on non-redundant retry",
277 [1] = "Memory or FB-DIMM configuration CRC read error",
279 [3] = "Uncorrectable Data ECC on Replay",
280 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
281 /* M6 Unsupported on i7300 */
282 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
283 [7] = "Aliased Uncorrectable Patrol Data ECC",
284 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
285 /* M10 Unsupported on i7300 */
286 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
287 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
288 [12] = "Memory Write error on first attempt",
289 [13] = "FB-DIMM Configuration Write error on first attempt",
290 [14] = "Memory or FB-DIMM configuration CRC read error",
291 [15] = "Channel Failed-Over Occurred",
292 [16] = "Correctable Non-Mirrored Demand Data ECC",
293 /* M18 Unsupported on i7300 */
294 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
295 [19] = "Correctable Patrol Data ECC",
296 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
297 [21] = "SPD protocol Error",
298 [22] = "Non-Redundant Fast Reset Timeout",
299 [23] = "Refresh error",
300 [24] = "Memory Write error on redundant retry",
301 [25] = "Redundant Fast Reset Timeout",
302 [26] = "Correctable Counter Threshold Exceeded",
303 [27] = "DIMM-Spare Copy Completed",
304 [28] = "DIMM-Isolation Completed",
308 #define ERROR_FAT_MASK (EMASK_M1 | \
312 /* Correctable errors */
313 #define ERROR_NF_CORRECTABLE (EMASK_M27 | \
319 #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
321 #define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
322 #define ERROR_NF_NORTH_CRC (EMASK_M21)
324 /* Recoverable errors */
325 #define ERROR_NF_RECOVERABLE (EMASK_M26 | \
338 /* uncorrectable errors */
339 #define ERROR_NF_UNCORRECTABLE (EMASK_M4)
341 /* mask to all non-fatal errors */
342 #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
343 ERROR_NF_UNCORRECTABLE | \
344 ERROR_NF_RECOVERABLE | \
345 ERROR_NF_DIMM_SPARE | \
346 ERROR_NF_SPD_PROTOCOL | \
350 * Define error masks for the several registers
353 /* Enable all fatal and non fatal errors */
354 #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
356 /* mask for fatal error registers */
357 #define FERR_FAT_MASK ERROR_FAT_MASK
359 /* masks for non-fatal error register */
360 static inline int to_nf_mask(unsigned int mask)
362 return (mask & EMASK_M29) | (mask >> 3);
365 static inline int from_nf_ferr(unsigned int mask)
367 return (mask & EMASK_M29) | /* Bit 28 */
368 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
371 #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
372 #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
373 #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
374 #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
375 #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
376 #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
377 #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
381 /* Device name and register DID (Device ID) */
382 struct i7300_dev_info {
383 const char *ctl_name; /* name for this device */
384 u16 fsb_mapping_errors; /* DID for the branchmap,control */
387 /* Table of devices attributes supported by this driver */
388 static const struct i7300_dev_info i7300_devs[] = {
391 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
395 struct i7300_dimm_info {
396 int megabytes; /* size, 0 means not present */
399 /* driver private data structure */
401 struct pci_dev *system_address; /* 16.0 */
402 struct pci_dev *branchmap_werrors; /* 16.1 */
403 struct pci_dev *fsb_error_regs; /* 16.2 */
404 struct pci_dev *branch_pci[MAX_BRANCHES]; /* 21.0 and 22.0 */
406 u16 tolm; /* top of low memory */
407 u64 ambase; /* AMB BAR */
412 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
413 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
415 /* DIMM information matrix, allocating architecture maximums */
416 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
420 /* I7300 MCH error information retrieved from Hardware */
421 struct i7300_error_info {
422 /* These registers are always read from the MC */
423 u32 ferr_fat_fbd; /* First Errors Fatal */
424 u32 nerr_fat_fbd; /* Next Errors Fatal */
425 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
426 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
428 /* These registers are input ONLY if there was a Recoverable Error */
429 u32 redmemb; /* Recoverable Mem Data Error log B */
430 u16 recmema; /* Recoverable Mem Error log A */
431 u32 recmemb; /* Recoverable Mem Error log B */
433 /* These registers are input ONLY if there was a Non-Rec Error */
434 u16 nrecmema; /* Non-Recoverable Mem log A */
435 u16 nrecmemb; /* Non-Recoverable Mem log B */
440 /* FIXME: Why do we need to have this static? */
441 static struct edac_pci_ctl_info *i7300_pci;
445 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
446 5400 better to use an inline function than a macro in this case */
447 static inline int nrec_bank(struct i7300_error_info *info)
449 return ((info->nrecmema) >> 12) & 0x7;
451 static inline int nrec_rank(struct i7300_error_info *info)
453 return ((info->nrecmema) >> 8) & 0xf;
455 static inline int nrec_buf_id(struct i7300_error_info *info)
457 return ((info->nrecmema)) & 0xff;
459 static inline int nrec_rdwr(struct i7300_error_info *info)
461 return (info->nrecmemb) >> 31;
463 /* This applies to both NREC and REC string so it can be used with nrec_rdwr
465 static inline const char *rdwr_str(int rdwr)
467 return rdwr ? "Write" : "Read";
469 static inline int nrec_cas(struct i7300_error_info *info)
471 return ((info->nrecmemb) >> 16) & 0x1fff;
473 static inline int nrec_ras(struct i7300_error_info *info)
475 return (info->nrecmemb) & 0xffff;
477 static inline int rec_bank(struct i7300_error_info *info)
479 return ((info->recmema) >> 12) & 0x7;
481 static inline int rec_rank(struct i7300_error_info *info)
483 return ((info->recmema) >> 8) & 0xf;
485 static inline int rec_rdwr(struct i7300_error_info *info)
487 return (info->recmemb) >> 31;
489 static inline int rec_cas(struct i7300_error_info *info)
491 return ((info->recmemb) >> 16) & 0x1fff;
493 static inline int rec_ras(struct i7300_error_info *info)
495 return (info->recmemb) & 0xffff;
499 * i7300_get_error_info Retrieve the hardware error information from
500 * the hardware and cache it in the 'info'
503 static void i7300_get_error_info(struct mem_ctl_info *mci,
504 struct i7300_error_info *info)
506 struct i7300_pvt *pvt;
511 /* read in the 1st FATAL error register */
512 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
514 /* Mask only the bits that the doc says are valid
516 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
518 /* If there is an error, then read in the
519 NEXT FATAL error register and the Memory Error Log Register A
521 if (value & FERR_FAT_MASK) {
522 info->ferr_fat_fbd = value;
524 /* harvest the various error data we need */
525 pci_read_config_dword(pvt->branchmap_werrors,
526 NERR_FAT_FBD, &info->nerr_fat_fbd);
527 pci_read_config_word(pvt->branchmap_werrors,
528 NRECMEMA, &info->nrecmema);
529 pci_read_config_word(pvt->branchmap_werrors,
530 NRECMEMB, &info->nrecmemb);
532 /* Clear the error bits, by writing them back */
533 pci_write_config_dword(pvt->branchmap_werrors,
534 FERR_FAT_FBD, value);
536 info->ferr_fat_fbd = 0;
537 info->nerr_fat_fbd = 0;
542 /* read in the 1st NON-FATAL error register */
543 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
545 /* If there is an error, then read in the 1st NON-FATAL error
546 * register as well */
547 if (value & FERR_NF_MASK) {
548 info->ferr_nf_fbd = value;
550 /* harvest the various error data we need */
551 pci_read_config_dword(pvt->branchmap_werrors,
552 NERR_NF_FBD, &info->nerr_nf_fbd);
553 pci_read_config_word(pvt->branchmap_werrors,
554 RECMEMA, &info->recmema);
555 pci_read_config_dword(pvt->branchmap_werrors,
556 RECMEMB, &info->recmemb);
557 pci_read_config_dword(pvt->branchmap_werrors,
558 REDMEMB, &info->redmemb);
560 /* Clear the error bits, by writing them back */
561 pci_write_config_dword(pvt->branchmap_werrors,
564 info->ferr_nf_fbd = 0;
565 info->nerr_nf_fbd = 0;
573 * i7300_proccess_non_recoverable_info(struct mem_ctl_info *mci,
574 * struct i7300_error_info *info,
575 * int handle_errors);
577 * handle the Intel FATAL and unrecoverable errors, if any
579 static void i7300_proccess_non_recoverable_info(struct mem_ctl_info *mci,
580 struct i7300_error_info *info,
581 unsigned long allErrors)
583 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
595 return; /* if no error, return now */
597 if (allErrors & ERROR_FAT_MASK)
599 else if (allErrors & FERR_NF_UNCORRECTABLE)
600 type = "NON-FATAL uncorrected";
602 type = "NON-FATAL recoverable";
604 /* ONLY ONE of the possible error bits will be set, as per the docs */
606 branch = extract_fbdchan_indx(info->ferr_fat_fbd);
609 /* Use the NON-Recoverable macros to extract data */
610 bank = nrec_bank(info);
611 rank = nrec_rank(info);
612 buf_id = nrec_buf_id(info);
613 rdwr = nrec_rdwr(info);
614 ras = nrec_ras(info);
615 cas = nrec_cas(info);
617 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
618 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
619 rank, channel, channel + 1, branch >> 1, bank,
620 buf_id, rdwr_str(rdwr), ras, cas);
622 /* Only 1 bit will be on */
623 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
625 /* Form out message */
626 snprintf(msg, sizeof(msg),
627 "%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
628 "RAS=%d CAS=%d %s Err=0x%lx (%s))",
629 type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
630 type, allErrors, error_name[errnum]);
632 /* Call the helper to output message */
633 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
637 * i7300_process_fatal_error_info(struct mem_ctl_info *mci,
638 * struct i7300_error_info *info,
639 * int handle_errors);
641 * handle the Intel NON-FATAL errors, if any
643 static void i7300_process_nonfatal_error_info(struct mem_ctl_info *mci,
644 struct i7300_error_info *info)
646 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
647 unsigned long allErrors;
656 /* mask off the Error bits that are possible */
657 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
659 return; /* if no error, return now */
661 /* ONLY ONE of the possible error bits will be set, as per the docs */
663 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
664 i7300_proccess_non_recoverable_info(mci, info, allErrors);
668 /* Correctable errors */
669 if (allErrors & ERROR_NF_CORRECTABLE) {
670 debugf0("\tCorrected bits= 0x%lx\n", allErrors);
672 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
675 if (REC_ECC_LOCATOR_ODD(info->redmemb))
678 /* Convert channel to be based from zero, instead of
679 * from branch base of 0 */
682 bank = rec_bank(info);
683 rank = rec_rank(info);
684 rdwr = rec_rdwr(info);
688 /* Only 1 bit will be on */
689 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
691 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
692 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
693 rank, channel, branch >> 1, bank,
694 rdwr_str(rdwr), ras, cas);
696 /* Form out message */
697 snprintf(msg, sizeof(msg),
698 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
699 "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
700 branch >> 1, bank, rdwr_str(rdwr), ras, cas,
701 allErrors, error_name[errnum]);
703 /* Call the helper to output message */
704 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
709 /* Miscelaneous errors */
710 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
712 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
714 i7300_mc_printk(mci, KERN_EMERG,
715 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
716 branch >> 1, allErrors, error_name[errnum]);
720 * i7300_process_error_info Process the error info that is
721 * in the 'info' structure, previously retrieved from hardware
723 static void i7300_process_error_info(struct mem_ctl_info *mci,
724 struct i7300_error_info *info)
727 /* First handle any fatal errors that occurred */
728 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
729 i7300_proccess_non_recoverable_info(mci, info, allErrors);
731 /* now handle any non-fatal errors that occurred */
732 i7300_process_nonfatal_error_info(mci, info);
736 * i7300_clear_error Retrieve any error from the hardware
737 * but do NOT process that error.
738 * Used for 'clearing' out of previous errors
739 * Called by the Core module.
741 static void i7300_clear_error(struct mem_ctl_info *mci)
743 struct i7300_error_info info;
745 i7300_get_error_info(mci, &info);
749 * i7300_check_error Retrieve and process errors reported by the
750 * hardware. Called by the Core module.
752 static void i7300_check_error(struct mem_ctl_info *mci)
754 struct i7300_error_info info;
755 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
756 i7300_get_error_info(mci, &info);
757 i7300_process_error_info(mci, &info);
761 * i7300_enable_error_reporting
762 * Turn on the memory reporting features of the hardware
764 static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
766 struct i7300_pvt *pvt;
771 /* Read the FBD Error Mask Register */
772 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
775 /* Enable with a '0' */
776 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
778 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
784 * determine_mtr(pvt, csrow, channel)
786 * return the proper MTR register as determine by the csrow and desired channel
788 static int decode_mtr(struct i7300_pvt *pvt,
789 int slot, int ch, int branch,
790 struct i7300_dimm_info *dinfo,
791 struct csrow_info *p_csrow)
793 int mtr, ans, addrBits, channel;
795 channel = to_channel(ch, branch);
797 mtr = pvt->mtr[slot][branch];
798 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
800 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
802 ans ? "Present" : "NOT Present");
804 /* Determine if there is a DIMM present in this DIMM slot */
807 if (!amb_present || !ans)
814 /* Start with the number of bits for a Bank
816 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
817 /* Add thenumber of ROW bits */
818 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
819 /* add the number of COLUMN bits */
820 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
821 /* add the number of RANK bits */
822 addrBits += MTR_DIMM_RANKS(mtr);
824 addrBits += 6; /* add 64 bits per DIMM */
825 addrBits -= 20; /* divide by 2^^20 */
826 addrBits -= 3; /* 8 bits per bytes */
828 dinfo->megabytes = 1 << addrBits;
830 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
832 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
833 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
835 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
836 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
837 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
838 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
839 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
842 p_csrow->nr_pages = dinfo->megabytes << 8;
843 p_csrow->mtype = MEM_FB_DDR2;
844 p_csrow->edac_mode = EDAC_S8ECD8ED;
846 /* ask what device type on this row */
847 if (MTR_DRAM_WIDTH(mtr))
848 p_csrow->dtype = DEV_X8;
850 p_csrow->dtype = DEV_X4;
858 * also will output a DIMM matrix map, if debug is enabled, for viewing
859 * how the DIMMs are populated
861 static void print_dimm_size(struct i7300_pvt *pvt)
863 struct i7300_dimm_info *dinfo;
864 char *p, *mem_buffer;
869 mem_buffer = p = kmalloc(space, GFP_KERNEL);
871 i7300_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
876 n = snprintf(p, space, " ");
879 for (channel = 0; channel < MAX_CHANNELS; channel++) {
880 n = snprintf(p, space, "channel %d | ", channel);
884 debugf2("%s\n", mem_buffer);
887 n = snprintf(p, space, "-------------------------------"
888 "------------------------------");
891 debugf2("%s\n", mem_buffer);
895 for (slot = 0; slot < MAX_SLOTS; slot++) {
896 n = snprintf(p, space, "csrow/SLOT %d ", slot);
900 for (channel = 0; channel < MAX_CHANNELS; channel++) {
901 dinfo = &pvt->dimm_info[slot][channel];
902 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
907 debugf2("%s\n", mem_buffer);
912 n = snprintf(p, space, "-------------------------------"
913 "------------------------------");
916 debugf2("%s\n", mem_buffer);
924 * i7300_init_csrows Initialize the 'csrows' table within
925 * the mci control structure with the
926 * addressing of memory.
930 * 1 no actual memory found on this MC
932 static int i7300_init_csrows(struct mem_ctl_info *mci)
934 struct i7300_pvt *pvt;
935 struct i7300_dimm_info *dinfo;
936 struct csrow_info *p_csrow;
939 int ch, branch, slot, channel;
943 empty = 1; /* Assume NO memory */
945 debugf2("Memory Technology Registers:\n");
947 /* Get the AMB present registers for the four channels */
948 for (branch = 0; branch < MAX_BRANCHES; branch++) {
949 /* Read and dump branch 0's MTRs */
950 channel = to_channel(0, branch);
951 pci_read_config_word(pvt->branch_pci[branch], AMBPRESENT_0,
952 &pvt->ambpresent[channel]);
953 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
954 channel, pvt->ambpresent[channel]);
956 channel = to_channel(1, branch);
957 pci_read_config_word(pvt->branch_pci[branch], AMBPRESENT_1,
958 &pvt->ambpresent[channel]);
959 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
960 channel, pvt->ambpresent[channel]);
963 /* Get the set of MTR[0-7] regs by each branch */
964 for (slot = 0; slot < MAX_SLOTS; slot++) {
965 int where = mtr_regs[slot];
966 for (branch = 0; branch < MAX_BRANCHES; branch++) {
967 pci_read_config_word(pvt->branch_pci[branch],
969 &pvt->mtr[slot][branch]);
970 for (ch = 0; ch < MAX_BRANCHES; ch++) {
971 int channel = to_channel(ch, branch);
973 dinfo = &pvt->dimm_info[slot][channel];
974 p_csrow = &mci->csrows[slot];
976 mtr = decode_mtr(pvt, slot, ch, branch,
978 /* if no DIMMS on this row, continue */
979 if (!MTR_DIMMS_PRESENT(mtr))
982 p_csrow->csrow_idx = slot;
984 /* FAKE OUT VALUES, FIXME */
985 p_csrow->first_page = 0 + slot * 20;
986 p_csrow->last_page = 9 + slot * 20;
987 p_csrow->page_mask = 0xfff;
997 static void decode_mir(int mir_no, u16 mir[MAX_MIR])
1000 debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
1002 (mir[mir_no] >> 4) & 0xfff,
1003 (mir[mir_no] & 1) ? "B0" : "",
1004 (mir[mir_no] & 2) ? "B1": "");
1008 * i7300_get_mc_regs read in the necessary registers and
1011 * Fills in the private data members
1013 static int i7300_get_mc_regs(struct mem_ctl_info *mci)
1015 struct i7300_pvt *pvt;
1019 pvt = mci->pvt_info;
1021 pci_read_config_dword(pvt->system_address, AMBASE,
1022 (u32 *) &pvt->ambase);
1024 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
1026 /* Get the Branch Map regs */
1027 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1029 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1032 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1033 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1034 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1036 /* Get memory controller settings */
1037 pci_read_config_dword(pvt->branchmap_werrors, MC_SETTINGS,
1039 debugf0("Memory controller operating on %s mode\n",
1040 pvt->mc_settings & (1 << 16)? "mirrored" : "non-mirrored");
1041 debugf0("Error detection is %s\n",
1042 pvt->mc_settings & (1 << 5)? "enabled" : "disabled");
1044 /* Get Memory Interleave Range registers */
1045 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir[0]);
1046 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir[1]);
1047 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir[2]);
1049 /* Decode the MIR regs */
1050 for (i = 0; i < MAX_MIR; i++)
1051 decode_mir(i, pvt->mir);
1053 rc = i7300_init_csrows(mci);
1057 /* Go and determine the size of each DIMM and place in an
1059 print_dimm_size(pvt);
1065 * i7300_put_devices 'put' all the devices that we have
1066 * reserved via 'get'
1068 static void i7300_put_devices(struct mem_ctl_info *mci)
1070 struct i7300_pvt *pvt;
1073 pvt = mci->pvt_info;
1075 /* Decrement usage count for devices */
1076 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
1077 pci_dev_put(pvt->branch_pci[branch]);
1078 pci_dev_put(pvt->fsb_error_regs);
1079 pci_dev_put(pvt->branchmap_werrors);
1083 * i7300_get_devices Find and perform 'get' operation on the MCH's
1084 * device/functions we want to reference for this driver
1086 * Need to 'get' device 16 func 1 and func 2
1088 static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx)
1090 struct i7300_pvt *pvt;
1091 struct pci_dev *pdev;
1093 pvt = mci->pvt_info;
1095 /* Attempt to 'get' the MCH register we want */
1097 while (!pvt->branchmap_werrors || !pvt->fsb_error_regs) {
1098 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1099 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
1101 /* End of list, leave */
1102 i7300_printk(KERN_ERR,
1103 "'system address,Process Bus' "
1105 "vendor 0x%x device 0x%x ERR funcs "
1107 PCI_VENDOR_ID_INTEL,
1108 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
1112 /* Store device 16 funcs 1 and 2 */
1113 switch (PCI_FUNC(pdev->devfn)) {
1115 pvt->branchmap_werrors = pdev;
1118 pvt->fsb_error_regs = pdev;
1123 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
1124 pci_name(pvt->system_address),
1125 pvt->system_address->vendor, pvt->system_address->device);
1126 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
1127 pci_name(pvt->branchmap_werrors),
1128 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
1129 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
1130 pci_name(pvt->fsb_error_regs),
1131 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
1133 pvt->branch_pci[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
1134 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
1136 if (!pvt->branch_pci[0]) {
1137 i7300_printk(KERN_ERR,
1138 "MC: 'BRANCH 0' device not found:"
1139 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
1140 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
1144 pvt->branch_pci[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
1145 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
1147 if (!pvt->branch_pci[1]) {
1148 i7300_printk(KERN_ERR,
1149 "MC: 'BRANCH 1' device not found:"
1150 "vendor 0x%x device 0x%x Func 0 "
1152 PCI_VENDOR_ID_INTEL,
1153 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
1160 i7300_put_devices(mci);
1165 * i7300_probe1 Probe for ONE instance of device to see if it is
1168 * 0 for FOUND a device
1169 * < 0 for error code
1171 static int i7300_probe1(struct pci_dev *pdev, int dev_idx)
1173 struct mem_ctl_info *mci;
1174 struct i7300_pvt *pvt;
1176 int num_dimms_per_channel;
1179 if (dev_idx >= ARRAY_SIZE(i7300_devs))
1182 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1185 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1187 /* We only are looking for func 0 of the set */
1188 if (PCI_FUNC(pdev->devfn) != 0)
1191 /* As we don't have a motherboard identification routine to determine
1192 * actual number of slots/dimms per channel, we thus utilize the
1193 * resource as specified by the chipset. Thus, we might have
1194 * have more DIMMs per channel than actually on the mobo, but this
1195 * allows the driver to support upto the chipset max, without
1196 * some fancy mobo determination.
1198 num_dimms_per_channel = MAX_SLOTS;
1199 num_channels = MAX_CHANNELS;
1200 num_csrows = MAX_SLOTS * MAX_CHANNELS;
1202 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1203 __func__, num_channels, num_dimms_per_channel, num_csrows);
1205 /* allocate a new MC control structure */
1206 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1211 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1213 mci->dev = &pdev->dev; /* record ptr to the generic device */
1215 pvt = mci->pvt_info;
1216 pvt->system_address = pdev; /* Record this device in our private */
1218 /* 'get' the pci devices we want to reserve for our use */
1219 if (i7300_get_devices(mci, dev_idx))
1223 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1224 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1225 mci->edac_cap = EDAC_FLAG_NONE;
1226 mci->mod_name = "i7300_edac.c";
1227 mci->mod_ver = I7300_REVISION;
1228 mci->ctl_name = i7300_devs[dev_idx].ctl_name;
1229 mci->dev_name = pci_name(pdev);
1230 mci->ctl_page_to_phys = NULL;
1233 /* Set the function pointer to an actual operation function */
1234 mci->edac_check = i7300_check_error;
1237 /* initialize the MC control structure 'csrows' table
1238 * with the mapping and control information */
1239 if (i7300_get_mc_regs(mci)) {
1240 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1241 " because i7300_init_csrows() returned nonzero "
1243 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1246 debugf1("MC: Enable error reporting now\n");
1247 i7300_enable_error_reporting(mci);
1251 /* add this new MC control structure to EDAC's list of MCs */
1252 if (edac_mc_add_mc(mci)) {
1253 debugf0("MC: " __FILE__
1254 ": %s(): failed edac_mc_add_mc()\n", __func__);
1255 /* FIXME: perhaps some code should go here that disables error
1256 * reporting if we just enabled it
1262 i7300_clear_error(mci);
1265 /* allocating generic PCI control info */
1266 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1269 "%s(): Unable to create PCI control\n",
1272 "%s(): PCI error report via EDAC not setup\n",
1278 /* Error exit unwinding stack */
1281 i7300_put_devices(mci);
1289 * i7300_init_one constructor for one instance of device
1295 static int __devinit i7300_init_one(struct pci_dev *pdev,
1296 const struct pci_device_id *id)
1300 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1302 /* wake up device */
1303 rc = pci_enable_device(pdev);
1307 /* now probe and enable the device */
1308 return i7300_probe1(pdev, id->driver_data);
1312 * i7300_remove_one destructor for one instance of device
1315 static void __devexit i7300_remove_one(struct pci_dev *pdev)
1317 struct mem_ctl_info *mci;
1319 debugf0(__FILE__ ": %s()\n", __func__);
1322 edac_pci_release_generic_ctl(i7300_pci);
1324 mci = edac_mc_del_mc(&pdev->dev);
1328 /* retrieve references to resources, and free those resources */
1329 i7300_put_devices(mci);
1335 * pci_device_id table for which devices we are looking for
1337 * The "E500P" device is the first device supported.
1339 static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
1340 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
1341 {0,} /* 0 terminated list. */
1344 MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
1347 * i7300_driver pci_driver structure for this module
1350 static struct pci_driver i7300_driver = {
1351 .name = "i7300_edac",
1352 .probe = i7300_init_one,
1353 .remove = __devexit_p(i7300_remove_one),
1354 .id_table = i7300_pci_tbl,
1358 * i7300_init Module entry function
1359 * Try to initialize this module for its devices
1361 static int __init i7300_init(void)
1365 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1367 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1370 pci_rc = pci_register_driver(&i7300_driver);
1372 return (pci_rc < 0) ? pci_rc : 0;
1376 * i7300_exit() Module exit function
1377 * Unregister the driver
1379 static void __exit i7300_exit(void)
1381 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1382 pci_unregister_driver(&i7300_driver);
1385 module_init(i7300_init);
1386 module_exit(i7300_exit);
1388 MODULE_LICENSE("GPL");
1389 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1390 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1391 MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1394 module_param(edac_op_state, int, 0444);
1395 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");