2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
5 * This file may be distributed under the terms of the GNU General
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
14 * Written with reference to 82443BX Host Bridge Datasheet:
15 * http://www.intel.com/design/chipsets/440/documentation.htm
16 * references to this document given in [].
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
24 #include <linux/module.h>
25 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
30 #include <linux/slab.h>
32 #include "edac_core.h"
34 #define I82443_REVISION "0.1"
36 #define EDAC_MOD_STR "i82443bxgx_edac"
38 /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
39 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
40 * rows" "The 82443BX supports multiple-bit error detection and
41 * single-bit error correction when ECC mode is enabled and
42 * single/multi-bit error detection when correction is disabled.
43 * During writes to the DRAM, the 82443BX generates ECC for the data
44 * on a QWord basis. Partial QWord writes require a read-modify-write
45 * cycle when ECC is enabled."
48 /* "Additionally, the 82443BX ensures that the data is corrected in
49 * main memory so that accumulation of errors is prevented. Another
50 * error within the same QWord would result in a double-bit error
51 * which is unrecoverable. This is known as hardware scrubbing since
52 * it requires no software intervention to correct the data in memory."
55 /* [Also see page 100 (section 4.3), "DRAM Interface"]
56 * [Also see page 112 (section 4.6.1.4), ECC]
59 #define I82443BXGX_NR_CSROWS 8
60 #define I82443BXGX_NR_CHANS 1
61 #define I82443BXGX_NR_DIMMS 4
63 /* 82443 PCI Device 0 */
64 #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
65 * config space offset */
66 #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
68 #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
70 #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
71 #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
72 #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
73 #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
74 #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
76 #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
78 /* 82443 PCI Device 0 */
79 #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
80 * config space offset, Error Address
82 #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
83 #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
84 #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
86 #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
87 * config space offset. */
88 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
89 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
91 #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
92 * config space offset. */
93 #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
94 #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
95 #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
96 #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
98 #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
99 * config space offset. */
100 #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
101 #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
102 #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
103 #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
105 #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
106 * config space offset. */
108 /* FIXME - don't poll when ECC disabled? */
110 struct i82443bxgx_edacmc_error_info {
114 static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
115 struct i82443bxgx_edacmc_error_info
118 struct pci_dev *pdev;
119 pdev = to_pci_dev(mci->dev);
120 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
121 if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
122 /* Clear error to allow next error to be reported [p.61] */
123 pci_write_bits32(pdev, I82443BXGX_EAP,
124 I82443BXGX_EAP_OFFSET_SBE,
125 I82443BXGX_EAP_OFFSET_SBE);
127 if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
128 /* Clear error to allow next error to be reported [p.61] */
129 pci_write_bits32(pdev, I82443BXGX_EAP,
130 I82443BXGX_EAP_OFFSET_MBE,
131 I82443BXGX_EAP_OFFSET_MBE);
134 static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
136 i82443bxgx_edacmc_error_info
137 *info, int handle_errors)
140 u32 eapaddr, page, pageoffset;
142 /* bits 30:12 hold the 4kb block in which the error occurred
144 eapaddr = (info->eap & 0xfffff000);
145 page = eapaddr >> PAGE_SHIFT;
146 pageoffset = eapaddr - (page << PAGE_SHIFT);
148 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
151 edac_mc_handle_ce(mci, page, pageoffset,
152 /* 440BX/GX don't make syndrome information available */
153 0, edac_mc_find_csrow_by_page(mci, page), 0, /* channel */
157 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
160 edac_mc_handle_ue(mci, page, pageoffset,
161 edac_mc_find_csrow_by_page(mci, page),
168 static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
170 struct i82443bxgx_edacmc_error_info info;
172 debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
173 i82443bxgx_edacmc_get_error_info(mci, &info);
174 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
177 static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
178 struct pci_dev *pdev,
179 enum edac_type edac_mode,
182 struct csrow_info *csrow;
185 u32 row_base, row_high_limit, row_high_limit_last;
187 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
188 row_high_limit_last = 0;
189 for (index = 0; index < mci->nr_csrows; index++) {
190 csrow = &mci->csrows[index];
191 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
192 debugf1("MC%d: " __FILE__ ": %s() Row=%d DRB = %#0x\n",
193 mci->mc_idx, __func__, index, drbar);
194 row_high_limit = ((u32) drbar << 23);
195 /* find the DRAM Chip Select Base address and mask */
196 debugf1("MC%d: " __FILE__ ": %s() Row=%d, "
197 "Boundry Address=%#0x, Last = %#0x \n",
198 mci->mc_idx, __func__, index, row_high_limit,
199 row_high_limit_last);
201 /* 440GX goes to 2GB, represented with a DRB of 0. */
202 if (row_high_limit_last && !row_high_limit)
203 row_high_limit = 1UL << 31;
205 /* This row is empty [p.49] */
206 if (row_high_limit == row_high_limit_last)
208 row_base = row_high_limit_last;
209 csrow->first_page = row_base >> PAGE_SHIFT;
210 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
211 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
212 /* EAP reports in 4kilobyte granularity [61] */
213 csrow->grain = 1 << 12;
214 csrow->mtype = mtype;
215 /* I don't think 440BX can tell you device type? FIXME? */
216 csrow->dtype = DEV_UNKNOWN;
217 /* Mode is global to all rows on 440BX */
218 csrow->edac_mode = edac_mode;
219 row_high_limit_last = row_high_limit;
223 static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
225 struct mem_ctl_info *mci;
227 u32 nbxcfg, ecc_mode;
229 enum edac_type edac_mode;
231 debugf0("MC: " __FILE__ ": %s()\n", __func__);
233 /* Something is really hosed if PCI config space reads from
234 the MC aren't working. */
235 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
238 mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS);
243 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
244 mci->dev = &pdev->dev;
245 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
246 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
247 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
248 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
249 case I82443BXGX_DRAMC_DRAM_IS_EDO:
252 case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
255 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
260 ("Unknown/reserved DRAM type value in DRAMC register!\n");
261 mtype = -MEM_UNKNOWN;
264 if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
265 mci->edac_cap = mci->edac_ctl_cap;
267 mci->edac_cap = EDAC_FLAG_NONE;
269 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
270 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
271 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
274 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
275 ? SCRUB_HW_SRC : SCRUB_NONE;
278 case I82443BXGX_NBXCFG_INTEGRITY_NONE:
279 edac_mode = EDAC_NONE;
281 case I82443BXGX_NBXCFG_INTEGRITY_EC:
284 case I82443BXGX_NBXCFG_INTEGRITY_ECC:
285 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
286 edac_mode = EDAC_SECDED;
290 ("%s(): Unknown/reserved ECC state in NBXCFG register!\n",
292 edac_mode = EDAC_UNKNOWN;
296 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
298 /* Many BIOSes don't clear error flags on boot, so do this
299 * here, or we get "phantom" errors occuring at module-load
301 pci_write_bits32(pdev, I82443BXGX_EAP,
302 (I82443BXGX_EAP_OFFSET_SBE |
303 I82443BXGX_EAP_OFFSET_MBE),
304 (I82443BXGX_EAP_OFFSET_SBE |
305 I82443BXGX_EAP_OFFSET_MBE));
307 mci->mod_name = EDAC_MOD_STR;
308 mci->mod_ver = I82443_REVISION;
309 mci->ctl_name = "I82443BXGX";
310 mci->dev_name = pci_name(pdev);
311 mci->edac_check = i82443bxgx_edacmc_check;
312 mci->ctl_page_to_phys = NULL;
314 if (edac_mc_add_mc(mci, 0)) {
315 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
319 debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
327 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
329 /* returns count (>= 0), or negative on error */
330 static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
331 const struct pci_device_id *ent)
333 debugf0("MC: " __FILE__ ": %s()\n", __func__);
335 /* don't need to call pci_device_enable() */
336 return i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
339 static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
341 struct mem_ctl_info *mci;
343 debugf0(__FILE__ ": %s()\n", __func__);
345 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
351 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
353 static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
354 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
355 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
356 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
357 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
358 {0,} /* 0 terminated list. */
361 MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
363 static struct pci_driver i82443bxgx_edacmc_driver = {
364 .name = EDAC_MOD_STR,
365 .probe = i82443bxgx_edacmc_init_one,
366 .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
367 .id_table = i82443bxgx_pci_tbl,
370 static int __init i82443bxgx_edacmc_init(void)
372 return pci_register_driver(&i82443bxgx_edacmc_driver);
375 static void __exit i82443bxgx_edacmc_exit(void)
377 pci_unregister_driver(&i82443bxgx_edacmc_driver);
380 module_init(i82443bxgx_edacmc_init);
381 module_exit(i82443bxgx_edacmc_exit);
383 MODULE_LICENSE("GPL");
384 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
385 MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");