2 * Freescale MPC85xx Memory Controller kernel module
4 * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
6 * Author: Dave Jiang <djiang@mvista.com>
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/ctype.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/edac.h>
21 #include <linux/smp.h>
22 #include <linux/gfp.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include "edac_module.h"
27 #include "edac_core.h"
28 #include "mpc85xx_edac.h"
30 static int edac_dev_idx;
32 static int edac_pci_idx;
34 static int edac_mc_idx;
36 static u32 orig_ddr_err_disable;
37 static u32 orig_ddr_err_sbe;
43 static u32 orig_pci_err_cap_dr;
44 static u32 orig_pci_err_en;
47 static u32 orig_l2_err_disable;
48 #ifdef CONFIG_FSL_SOC_BOOKE
49 static u32 orig_hid1[2];
52 /************************ MC SYSFS parts ***********************************/
54 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
56 static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
57 struct device_attribute *mattr,
60 struct mem_ctl_info *mci = to_mci(dev);
61 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
62 return sprintf(data, "0x%08x",
63 in_be32(pdata->mc_vbase +
64 MPC85XX_MC_DATA_ERR_INJECT_HI));
67 static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
68 struct device_attribute *mattr,
71 struct mem_ctl_info *mci = to_mci(dev);
72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
73 return sprintf(data, "0x%08x",
74 in_be32(pdata->mc_vbase +
75 MPC85XX_MC_DATA_ERR_INJECT_LO));
78 static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
79 struct device_attribute *mattr,
82 struct mem_ctl_info *mci = to_mci(dev);
83 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
84 return sprintf(data, "0x%08x",
85 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
88 static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
89 struct device_attribute *mattr,
90 const char *data, size_t count)
92 struct mem_ctl_info *mci = to_mci(dev);
93 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
95 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
96 simple_strtoul(data, NULL, 0));
102 static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
103 struct device_attribute *mattr,
104 const char *data, size_t count)
106 struct mem_ctl_info *mci = to_mci(dev);
107 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
108 if (isdigit(*data)) {
109 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
110 simple_strtoul(data, NULL, 0));
116 static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
117 struct device_attribute *mattr,
118 const char *data, size_t count)
120 struct mem_ctl_info *mci = to_mci(dev);
121 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
122 if (isdigit(*data)) {
123 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
124 simple_strtoul(data, NULL, 0));
130 DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
131 mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
132 DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
133 mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
134 DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
135 mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
137 static int mpc85xx_create_sysfs_attributes(struct mem_ctl_info *mci)
141 rc = device_create_file(&mci->dev, &dev_attr_inject_data_hi);
144 rc = device_create_file(&mci->dev, &dev_attr_inject_data_lo);
147 rc = device_create_file(&mci->dev, &dev_attr_inject_ctrl);
154 static void mpc85xx_remove_sysfs_attributes(struct mem_ctl_info *mci)
156 device_remove_file(&mci->dev, &dev_attr_inject_data_hi);
157 device_remove_file(&mci->dev, &dev_attr_inject_data_lo);
158 device_remove_file(&mci->dev, &dev_attr_inject_ctrl);
161 /**************************** PCI Err device ***************************/
164 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
166 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
169 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
171 /* master aborts can happen during PCI config cycles */
172 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
173 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
177 printk(KERN_ERR "PCI error(s) detected\n");
178 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
180 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
181 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
182 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
183 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
184 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
185 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
186 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
187 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
188 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
189 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
191 /* clear error bits */
192 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
194 if (err_detect & PCI_EDE_PERR_MASK)
195 edac_pci_handle_pe(pci, pci->ctl_name);
197 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
198 edac_pci_handle_npe(pci, pci->ctl_name);
201 static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
203 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
206 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
208 pr_err("PCIe error(s) detected\n");
209 pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
210 pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n",
211 in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR));
212 pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
213 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
214 pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
215 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
216 pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
217 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
218 pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
219 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
221 /* clear error bits */
222 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
225 static int mpc85xx_pcie_find_capability(struct device_node *np)
227 struct pci_controller *hose;
232 hose = pci_find_hose_for_OF_device(np);
234 return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
237 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
239 struct edac_pci_ctl_info *pci = dev_id;
240 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
243 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
249 mpc85xx_pcie_check(pci);
251 mpc85xx_pci_check(pci);
256 int mpc85xx_pci_err_probe(struct platform_device *op)
258 struct edac_pci_ctl_info *pci;
259 struct mpc85xx_pci_pdata *pdata;
263 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
266 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
270 /* make sure error reporting method is sane */
271 switch (edac_op_state) {
272 case EDAC_OPSTATE_POLL:
273 case EDAC_OPSTATE_INT:
276 edac_op_state = EDAC_OPSTATE_INT;
280 pdata = pci->pvt_info;
281 pdata->name = "mpc85xx_pci_err";
284 if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0)
285 pdata->is_pcie = true;
287 dev_set_drvdata(&op->dev, pci);
289 pci->mod_name = EDAC_MOD_STR;
290 pci->ctl_name = pdata->name;
291 pci->dev_name = dev_name(&op->dev);
293 if (edac_op_state == EDAC_OPSTATE_POLL) {
295 pci->edac_check = mpc85xx_pcie_check;
297 pci->edac_check = mpc85xx_pci_check;
300 pdata->edac_idx = edac_pci_idx++;
302 res = of_address_to_resource(op->dev.of_node, 0, &r);
304 printk(KERN_ERR "%s: Unable to get resource for "
305 "PCI err regs\n", __func__);
309 /* we only need the error registers */
312 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
314 printk(KERN_ERR "%s: Error while requesting mem region\n",
320 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
321 if (!pdata->pci_vbase) {
322 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
327 if (pdata->is_pcie) {
328 orig_pci_err_cap_dr =
329 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
330 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
332 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
333 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
335 orig_pci_err_cap_dr =
336 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
338 /* PCI master abort is expected during config cycles */
339 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
342 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
344 /* disable master abort reporting */
345 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
348 /* clear error bits */
349 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
351 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
352 edac_dbg(3, "failed edac_pci_add_device()\n");
356 if (edac_op_state == EDAC_OPSTATE_INT) {
357 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
358 res = devm_request_irq(&op->dev, pdata->irq,
361 "[EDAC] PCI err", pci);
364 "%s: Unable to request irq %d for "
365 "MPC85xx PCI err\n", __func__, pdata->irq);
366 irq_dispose_mapping(pdata->irq);
371 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
375 if (pdata->is_pcie) {
377 * Enable all PCIe error interrupt & error detect except invalid
378 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
379 * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
380 * detection enable bit. Because PCIe bus code to initialize and
381 * configure these PCIe devices on booting will use some invalid
382 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
383 * notice information. So disable this detect to fix ugly print.
385 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
386 & ~PEX_ERR_ICCAIE_EN_BIT);
387 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
388 | PEX_ERR_ICCAD_DISR_BIT);
391 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
392 edac_dbg(3, "success\n");
393 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
398 edac_pci_del_device(&op->dev);
400 edac_pci_free_ctl_info(pci);
401 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
404 EXPORT_SYMBOL(mpc85xx_pci_err_probe);
406 #endif /* CONFIG_PCI */
408 /**************************** L2 Err device ***************************/
410 /************************ L2 SYSFS parts ***********************************/
412 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
413 *edac_dev, char *data)
415 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
416 return sprintf(data, "0x%08x",
417 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
420 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
421 *edac_dev, char *data)
423 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
424 return sprintf(data, "0x%08x",
425 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
428 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
429 *edac_dev, char *data)
431 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
432 return sprintf(data, "0x%08x",
433 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
436 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
437 *edac_dev, const char *data,
440 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
441 if (isdigit(*data)) {
442 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
443 simple_strtoul(data, NULL, 0));
449 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
450 *edac_dev, const char *data,
453 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
454 if (isdigit(*data)) {
455 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
456 simple_strtoul(data, NULL, 0));
462 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
463 *edac_dev, const char *data,
466 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
467 if (isdigit(*data)) {
468 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
469 simple_strtoul(data, NULL, 0));
475 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
478 .name = "inject_data_hi",
479 .mode = (S_IRUGO | S_IWUSR)
481 .show = mpc85xx_l2_inject_data_hi_show,
482 .store = mpc85xx_l2_inject_data_hi_store},
485 .name = "inject_data_lo",
486 .mode = (S_IRUGO | S_IWUSR)
488 .show = mpc85xx_l2_inject_data_lo_show,
489 .store = mpc85xx_l2_inject_data_lo_store},
492 .name = "inject_ctrl",
493 .mode = (S_IRUGO | S_IWUSR)
495 .show = mpc85xx_l2_inject_ctrl_show,
496 .store = mpc85xx_l2_inject_ctrl_store},
500 .attr = {.name = NULL}
504 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
507 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
510 /***************************** L2 ops ***********************************/
512 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
514 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
517 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
519 if (!(err_detect & L2_EDE_MASK))
522 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
523 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
524 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
525 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
526 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
527 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
528 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
529 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
530 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
531 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
532 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
533 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
535 /* clear error detect register */
536 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
538 if (err_detect & L2_EDE_CE_MASK)
539 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
541 if (err_detect & L2_EDE_UE_MASK)
542 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
545 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
547 struct edac_device_ctl_info *edac_dev = dev_id;
548 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
551 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
553 if (!(err_detect & L2_EDE_MASK))
556 mpc85xx_l2_check(edac_dev);
561 static int mpc85xx_l2_err_probe(struct platform_device *op)
563 struct edac_device_ctl_info *edac_dev;
564 struct mpc85xx_l2_pdata *pdata;
568 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
571 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
572 "cpu", 1, "L", 1, 2, NULL, 0,
575 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
579 pdata = edac_dev->pvt_info;
580 pdata->name = "mpc85xx_l2_err";
582 edac_dev->dev = &op->dev;
583 dev_set_drvdata(edac_dev->dev, edac_dev);
584 edac_dev->ctl_name = pdata->name;
585 edac_dev->dev_name = pdata->name;
587 res = of_address_to_resource(op->dev.of_node, 0, &r);
589 printk(KERN_ERR "%s: Unable to get resource for "
590 "L2 err regs\n", __func__);
594 /* we only need the error registers */
597 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
599 printk(KERN_ERR "%s: Error while requesting mem region\n",
605 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
606 if (!pdata->l2_vbase) {
607 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
612 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
614 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
616 /* clear the err_dis */
617 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
619 edac_dev->mod_name = EDAC_MOD_STR;
621 if (edac_op_state == EDAC_OPSTATE_POLL)
622 edac_dev->edac_check = mpc85xx_l2_check;
624 mpc85xx_set_l2_sysfs_attributes(edac_dev);
626 pdata->edac_idx = edac_dev_idx++;
628 if (edac_device_add_device(edac_dev) > 0) {
629 edac_dbg(3, "failed edac_device_add_device()\n");
633 if (edac_op_state == EDAC_OPSTATE_INT) {
634 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
635 res = devm_request_irq(&op->dev, pdata->irq,
636 mpc85xx_l2_isr, IRQF_SHARED,
637 "[EDAC] L2 err", edac_dev);
640 "%s: Unable to request irq %d for "
641 "MPC85xx L2 err\n", __func__, pdata->irq);
642 irq_dispose_mapping(pdata->irq);
647 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
650 edac_dev->op_state = OP_RUNNING_INTERRUPT;
652 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
655 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
657 edac_dbg(3, "success\n");
658 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
663 edac_device_del_device(&op->dev);
665 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
666 edac_device_free_ctl_info(edac_dev);
670 static int mpc85xx_l2_err_remove(struct platform_device *op)
672 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
673 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
677 if (edac_op_state == EDAC_OPSTATE_INT) {
678 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
679 irq_dispose_mapping(pdata->irq);
682 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
683 edac_device_del_device(&op->dev);
684 edac_device_free_ctl_info(edac_dev);
688 static struct of_device_id mpc85xx_l2_err_of_match[] = {
689 /* deprecate the fsl,85.. forms in the future, 2.6.30? */
690 { .compatible = "fsl,8540-l2-cache-controller", },
691 { .compatible = "fsl,8541-l2-cache-controller", },
692 { .compatible = "fsl,8544-l2-cache-controller", },
693 { .compatible = "fsl,8548-l2-cache-controller", },
694 { .compatible = "fsl,8555-l2-cache-controller", },
695 { .compatible = "fsl,8568-l2-cache-controller", },
696 { .compatible = "fsl,mpc8536-l2-cache-controller", },
697 { .compatible = "fsl,mpc8540-l2-cache-controller", },
698 { .compatible = "fsl,mpc8541-l2-cache-controller", },
699 { .compatible = "fsl,mpc8544-l2-cache-controller", },
700 { .compatible = "fsl,mpc8548-l2-cache-controller", },
701 { .compatible = "fsl,mpc8555-l2-cache-controller", },
702 { .compatible = "fsl,mpc8560-l2-cache-controller", },
703 { .compatible = "fsl,mpc8568-l2-cache-controller", },
704 { .compatible = "fsl,mpc8569-l2-cache-controller", },
705 { .compatible = "fsl,mpc8572-l2-cache-controller", },
706 { .compatible = "fsl,p1020-l2-cache-controller", },
707 { .compatible = "fsl,p1021-l2-cache-controller", },
708 { .compatible = "fsl,p2020-l2-cache-controller", },
711 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
713 static struct platform_driver mpc85xx_l2_err_driver = {
714 .probe = mpc85xx_l2_err_probe,
715 .remove = mpc85xx_l2_err_remove,
717 .name = "mpc85xx_l2_err",
718 .of_match_table = mpc85xx_l2_err_of_match,
722 /**************************** MC Err device ***************************/
725 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
726 * MPC8572 User's Manual. Each line represents a syndrome bit column as a
727 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
728 * below correspond to Freescale's manuals.
730 static unsigned int ecc_table[16] = {
733 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
734 0x00ff00ff, 0x00fff0ff,
735 0x0f0f0f0f, 0x0f0fff00,
736 0x11113333, 0x7777000f,
737 0x22224444, 0x8888222f,
738 0x44448888, 0xffff4441,
739 0x8888ffff, 0x11118882,
740 0xffff1111, 0x22221114, /* Syndrome bit 0 */
744 * Calculate the correct ECC value for a 64-bit value specified by high:low
746 static u8 calculate_ecc(u32 high, u32 low)
755 for (i = 0; i < 8; i++) {
756 mask_high = ecc_table[i * 2];
757 mask_low = ecc_table[i * 2 + 1];
760 for (j = 0; j < 32; j++) {
761 if ((mask_high >> j) & 1)
762 bit_cnt ^= (high >> j) & 1;
763 if ((mask_low >> j) & 1)
764 bit_cnt ^= (low >> j) & 1;
774 * Create the syndrome code which is generated if the data line specified by
775 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
776 * User's Manual and 9-61 in the MPC8572 User's Manual.
778 static u8 syndrome_from_bit(unsigned int bit) {
783 * Cycle through the upper or lower 32-bit portion of each value in
784 * ecc_table depending on if 'bit' is in the upper or lower half of
787 for (i = bit < 32; i < 16; i += 2)
788 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
794 * Decode data and ecc syndrome to determine what went wrong
795 * Note: This can only decode single-bit errors
797 static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
798 int *bad_data_bit, int *bad_ecc_bit)
807 * Calculate the ECC of the captured data and XOR it with the captured
808 * ECC to find an ECC syndrome value we can search for
810 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
812 /* Check if a data line is stuck... */
813 for (i = 0; i < 64; i++) {
814 if (syndrome == syndrome_from_bit(i)) {
820 /* If data is correct, check ECC bits for errors... */
821 for (i = 0; i < 8; i++) {
822 if ((syndrome >> i) & 0x1) {
829 static void mpc85xx_mc_check(struct mem_ctl_info *mci)
831 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
832 struct csrow_info *csrow;
844 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
848 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
851 /* no more processing if not ECC bit errors */
852 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
853 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
857 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
859 /* Mask off appropriate bits of syndrome based on bus width */
860 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
861 DSC_DBW_MASK) ? 32 : 64;
867 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
868 pfn = err_addr >> PAGE_SHIFT;
870 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
871 csrow = mci->csrows[row_index];
872 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
876 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
877 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
880 * Analyze single-bit errors on 64-bit wide buses
881 * TODO: Add support for 32-bit wide buses
883 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
884 sbe_ecc_decode(cap_high, cap_low, syndrome,
885 &bad_data_bit, &bad_ecc_bit);
887 if (bad_data_bit != -1)
888 mpc85xx_mc_printk(mci, KERN_ERR,
889 "Faulty Data bit: %d\n", bad_data_bit);
890 if (bad_ecc_bit != -1)
891 mpc85xx_mc_printk(mci, KERN_ERR,
892 "Faulty ECC bit: %d\n", bad_ecc_bit);
894 mpc85xx_mc_printk(mci, KERN_ERR,
895 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
896 cap_high ^ (1 << (bad_data_bit - 32)),
897 cap_low ^ (1 << bad_data_bit),
898 syndrome ^ (1 << bad_ecc_bit));
901 mpc85xx_mc_printk(mci, KERN_ERR,
902 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
903 cap_high, cap_low, syndrome);
904 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr);
905 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
907 /* we are out of range */
908 if (row_index == mci->nr_csrows)
909 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
911 if (err_detect & DDR_EDE_SBE)
912 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
913 pfn, err_addr & ~PAGE_MASK, syndrome,
917 if (err_detect & DDR_EDE_MBE)
918 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
919 pfn, err_addr & ~PAGE_MASK, syndrome,
923 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
926 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
928 struct mem_ctl_info *mci = dev_id;
929 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
932 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
936 mpc85xx_mc_check(mci);
941 static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
943 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
944 struct csrow_info *csrow;
945 struct dimm_info *dimm;
952 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
954 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
955 if (sdram_ctl & DSC_RD_EN) {
960 case DSC_SDTYPE_DDR2:
963 case DSC_SDTYPE_DDR3:
975 case DSC_SDTYPE_DDR2:
978 case DSC_SDTYPE_DDR3:
987 for (index = 0; index < mci->nr_csrows; index++) {
991 csrow = mci->csrows[index];
992 dimm = csrow->channels[0]->dimm;
994 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
995 (index * MPC85XX_MC_CS_BNDS_OFS));
997 start = (cs_bnds & 0xffff0000) >> 16;
998 end = (cs_bnds & 0x0000ffff);
1001 continue; /* not populated */
1003 start <<= (24 - PAGE_SHIFT);
1004 end <<= (24 - PAGE_SHIFT);
1005 end |= (1 << (24 - PAGE_SHIFT)) - 1;
1007 csrow->first_page = start;
1008 csrow->last_page = end;
1010 dimm->nr_pages = end + 1 - start;
1012 dimm->mtype = mtype;
1013 dimm->dtype = DEV_UNKNOWN;
1014 if (sdram_ctl & DSC_X32_EN)
1015 dimm->dtype = DEV_X32;
1016 dimm->edac_mode = EDAC_SECDED;
1020 static int mpc85xx_mc_err_probe(struct platform_device *op)
1022 struct mem_ctl_info *mci;
1023 struct edac_mc_layer layers[2];
1024 struct mpc85xx_mc_pdata *pdata;
1029 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
1032 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1034 layers[0].is_virt_csrow = true;
1035 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1037 layers[1].is_virt_csrow = false;
1038 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
1041 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1045 pdata = mci->pvt_info;
1046 pdata->name = "mpc85xx_mc_err";
1047 pdata->irq = NO_IRQ;
1048 mci->pdev = &op->dev;
1049 pdata->edac_idx = edac_mc_idx++;
1050 dev_set_drvdata(mci->pdev, mci);
1051 mci->ctl_name = pdata->name;
1052 mci->dev_name = pdata->name;
1054 res = of_address_to_resource(op->dev.of_node, 0, &r);
1056 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
1061 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
1063 printk(KERN_ERR "%s: Error while requesting mem region\n",
1069 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
1070 if (!pdata->mc_vbase) {
1071 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1076 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1077 if (!(sdram_ctl & DSC_ECC_EN)) {
1079 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1084 edac_dbg(3, "init mci\n");
1085 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1086 MEM_FLAG_DDR | MEM_FLAG_DDR2;
1087 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1088 mci->edac_cap = EDAC_FLAG_SECDED;
1089 mci->mod_name = EDAC_MOD_STR;
1090 mci->mod_ver = MPC85XX_REVISION;
1092 if (edac_op_state == EDAC_OPSTATE_POLL)
1093 mci->edac_check = mpc85xx_mc_check;
1095 mci->ctl_page_to_phys = NULL;
1097 mci->scrub_mode = SCRUB_SW_SRC;
1099 mpc85xx_init_csrows(mci);
1101 /* store the original error disable bits */
1102 orig_ddr_err_disable =
1103 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1104 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1106 /* clear all error bits */
1107 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1109 if (edac_mc_add_mc(mci)) {
1110 edac_dbg(3, "failed edac_mc_add_mc()\n");
1114 if (mpc85xx_create_sysfs_attributes(mci)) {
1115 edac_mc_del_mc(mci->pdev);
1116 edac_dbg(3, "failed edac_mc_add_mc()\n");
1120 if (edac_op_state == EDAC_OPSTATE_INT) {
1121 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1122 DDR_EIE_MBEE | DDR_EIE_SBEE);
1124 /* store the original error management threshold */
1125 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1126 MPC85XX_MC_ERR_SBE) & 0xff0000;
1128 /* set threshold to 1 error per interrupt */
1129 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1131 /* register interrupts */
1132 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1133 res = devm_request_irq(&op->dev, pdata->irq,
1136 "[EDAC] MC err", mci);
1138 printk(KERN_ERR "%s: Unable to request irq %d for "
1139 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1140 irq_dispose_mapping(pdata->irq);
1145 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1149 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1150 edac_dbg(3, "success\n");
1151 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1156 edac_mc_del_mc(&op->dev);
1158 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1163 static int mpc85xx_mc_err_remove(struct platform_device *op)
1165 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1166 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1170 if (edac_op_state == EDAC_OPSTATE_INT) {
1171 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1172 irq_dispose_mapping(pdata->irq);
1175 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1176 orig_ddr_err_disable);
1177 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1179 mpc85xx_remove_sysfs_attributes(mci);
1180 edac_mc_del_mc(&op->dev);
1185 static struct of_device_id mpc85xx_mc_err_of_match[] = {
1186 /* deprecate the fsl,85.. forms in the future, 2.6.30? */
1187 { .compatible = "fsl,8540-memory-controller", },
1188 { .compatible = "fsl,8541-memory-controller", },
1189 { .compatible = "fsl,8544-memory-controller", },
1190 { .compatible = "fsl,8548-memory-controller", },
1191 { .compatible = "fsl,8555-memory-controller", },
1192 { .compatible = "fsl,8568-memory-controller", },
1193 { .compatible = "fsl,mpc8536-memory-controller", },
1194 { .compatible = "fsl,mpc8540-memory-controller", },
1195 { .compatible = "fsl,mpc8541-memory-controller", },
1196 { .compatible = "fsl,mpc8544-memory-controller", },
1197 { .compatible = "fsl,mpc8548-memory-controller", },
1198 { .compatible = "fsl,mpc8555-memory-controller", },
1199 { .compatible = "fsl,mpc8560-memory-controller", },
1200 { .compatible = "fsl,mpc8568-memory-controller", },
1201 { .compatible = "fsl,mpc8569-memory-controller", },
1202 { .compatible = "fsl,mpc8572-memory-controller", },
1203 { .compatible = "fsl,mpc8349-memory-controller", },
1204 { .compatible = "fsl,p1020-memory-controller", },
1205 { .compatible = "fsl,p1021-memory-controller", },
1206 { .compatible = "fsl,p2020-memory-controller", },
1207 { .compatible = "fsl,qoriq-memory-controller", },
1210 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
1212 static struct platform_driver mpc85xx_mc_err_driver = {
1213 .probe = mpc85xx_mc_err_probe,
1214 .remove = mpc85xx_mc_err_remove,
1216 .name = "mpc85xx_mc_err",
1217 .of_match_table = mpc85xx_mc_err_of_match,
1221 #ifdef CONFIG_FSL_SOC_BOOKE
1222 static void __init mpc85xx_mc_clear_rfxe(void *data)
1224 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1225 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
1229 static int __init mpc85xx_mc_init(void)
1234 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1235 "(C) 2006 Montavista Software\n");
1237 /* make sure error reporting method is sane */
1238 switch (edac_op_state) {
1239 case EDAC_OPSTATE_POLL:
1240 case EDAC_OPSTATE_INT:
1243 edac_op_state = EDAC_OPSTATE_INT;
1247 res = platform_driver_register(&mpc85xx_mc_err_driver);
1249 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1251 res = platform_driver_register(&mpc85xx_l2_err_driver);
1253 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1255 #ifdef CONFIG_FSL_SOC_BOOKE
1256 pvr = mfspr(SPRN_PVR);
1258 if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
1259 (PVR_VER(pvr) == PVR_VER_E500V2)) {
1261 * need to clear HID1[RFXE] to disable machine check int
1262 * so we can catch it
1264 if (edac_op_state == EDAC_OPSTATE_INT)
1265 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
1272 module_init(mpc85xx_mc_init);
1274 #ifdef CONFIG_FSL_SOC_BOOKE
1275 static void __exit mpc85xx_mc_restore_hid1(void *data)
1277 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1281 static void __exit mpc85xx_mc_exit(void)
1283 #ifdef CONFIG_FSL_SOC_BOOKE
1284 u32 pvr = mfspr(SPRN_PVR);
1286 if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
1287 (PVR_VER(pvr) == PVR_VER_E500V2)) {
1288 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1291 platform_driver_unregister(&mpc85xx_l2_err_driver);
1292 platform_driver_unregister(&mpc85xx_mc_err_driver);
1295 module_exit(mpc85xx_mc_exit);
1297 MODULE_LICENSE("GPL");
1298 MODULE_AUTHOR("Montavista Software, Inc.");
1299 module_param(edac_op_state, int, 0444);
1300 MODULE_PARM_DESC(edac_op_state,
1301 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");