2 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of the
12 #include <linux/edac.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/of_platform.h>
20 #include <linux/types.h>
24 #include "edac_core.h"
25 #include "ppc4xx_edac.h"
28 * This file implements a driver for monitoring and handling events
29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
30 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
32 * As realized in the 405EX[r], this controller features:
34 * - Support for registered- and non-registered DDR1 and DDR2 memory.
35 * - 32-bit or 16-bit memory interface with optional ECC.
37 * o ECC support includes:
40 * - Aligned-nibble error detect
43 * - Two (2) memory banks/ranks.
44 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
45 * bank/rank in 16-bit mode.
47 * As realized in the 440SP and 440SPe, this controller changes/adds:
49 * - 64-bit or 32-bit memory interface with optional ECC.
51 * o ECC support includes:
54 * - Aligned-nibble error detect
57 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
58 * per bank/rank in 32-bit mode.
60 * As realized in the 460EX and 460GT, this controller changes/adds:
62 * - 64-bit or 32-bit memory interface with optional ECC.
64 * o ECC support includes:
67 * - Aligned-nibble error detect
70 * - Four (4) memory banks/ranks.
71 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
72 * per bank/rank in 32-bit mode.
74 * At present, this driver has ONLY been tested against the controller
75 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
76 * boards (256 MiB w/o ECC memory soldered onto the board) and a
77 * proprietary board based on those designs (128 MiB ECC memory, also
78 * soldered onto the board).
80 * Dynamic feature detection and handling needs to be added for the
81 * other realizations of this controller listed above.
83 * Eventually, this driver will likely be adapted to the above variant
84 * realizations of this controller as well as broken apart to handle
85 * the other known ECC-capable controllers prevalent in other 4xx
88 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
89 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
90 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
92 * For this controller, unfortunately, correctable errors report
93 * nothing more than the beat/cycle and byte/lane the correction
94 * occurred on and the check bit group that covered the error.
96 * In contrast, uncorrectable errors also report the failing address,
97 * the bus master and the transaction direction (i.e. read or write)
99 * Regardless of whether the error is a CE or a UE, we report the
100 * following pieces of information in the driver-unique message to the
105 * - Check bit error group
109 /* Preprocessor Definitions */
111 #define EDAC_OPSTATE_INT_STR "interrupt"
112 #define EDAC_OPSTATE_POLL_STR "polled"
113 #define EDAC_OPSTATE_UNKNOWN_STR "unknown"
115 #define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
116 #define PPC4XX_EDAC_MODULE_REVISION "v1.0.0"
118 #define PPC4XX_EDAC_MESSAGE_SIZE 256
121 * Kernel logging without an EDAC instance
123 #define ppc4xx_edac_printk(level, fmt, arg...) \
124 edac_printk(level, "PPC4xx MC", fmt, ##arg)
127 * Kernel logging with an EDAC instance
129 #define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
130 edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
133 * Macros to convert bank configuration size enumerations into MiB and
136 #define SDRAM_MBCF_SZ_MiB_MIN 4
137 #define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
138 << (SDRAM_MBCF_SZ_DECODE(n)))
139 #define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
140 << (20 - PAGE_SHIFT + \
141 SDRAM_MBCF_SZ_DECODE(n)))
144 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
145 * indirectly accessed and have a base and length defined by the
146 * device tree. The base can be anything; however, we expect the
147 * length to be precisely two registers, the first for the address
148 * window and the second for the data window.
150 #define SDRAM_DCR_RESOURCE_LEN 2
151 #define SDRAM_DCR_ADDR_OFFSET 0
152 #define SDRAM_DCR_DATA_OFFSET 1
155 * Device tree interrupt indices
157 #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
158 #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
160 /* Type Definitions */
163 * PPC4xx SDRAM memory controller private instance data
165 struct ppc4xx_edac_pdata {
166 dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */
168 int sec; /* Single-bit correctable error IRQ assigned */
169 int ded; /* Double-bit detectable error IRQ assigned */
174 * Various status data gathered and manipulated when checking and
175 * reporting ECC status.
177 struct ppc4xx_ecc_status {
185 /* Function Prototypes */
187 static int ppc4xx_edac_probe(struct platform_device *device);
188 static int ppc4xx_edac_remove(struct platform_device *device);
190 /* Global Variables */
193 * Device tree node type and compatible tuples this driver can match
196 static struct of_device_id ppc4xx_edac_match[] = {
198 .compatible = "ibm,sdram-4xx-ddr2"
203 static struct platform_driver ppc4xx_edac_driver = {
204 .probe = ppc4xx_edac_probe,
205 .remove = ppc4xx_edac_remove,
207 .name = PPC4XX_EDAC_MODULE_NAME,
208 .of_match_table = ppc4xx_edac_match,
213 * TODO: The row and channel parameters likely need to be dynamically
214 * set based on the aforementioned variant controller realizations.
216 static const unsigned ppc4xx_edac_nr_csrows = 2;
217 static const unsigned ppc4xx_edac_nr_chans = 1;
220 * Strings associated with PLB master IDs capable of being posted in
221 * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
223 static const char * const ppc4xx_plb_masters[9] = {
224 [SDRAM_PLB_M0ID_ICU] = "ICU",
225 [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
226 [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
227 [SDRAM_PLB_M0ID_DMA] = "DMA",
228 [SDRAM_PLB_M0ID_DCU] = "DCU",
229 [SDRAM_PLB_M0ID_OPB] = "OPB",
230 [SDRAM_PLB_M0ID_MAL] = "MAL",
231 [SDRAM_PLB_M0ID_SEC] = "SEC",
232 [SDRAM_PLB_M0ID_AHB] = "AHB"
236 * mfsdram - read and return controller register data
237 * @dcr_host: A pointer to the DCR mapping.
238 * @idcr_n: The indirect DCR register to read.
240 * This routine reads and returns the data associated with the
241 * controller's specified indirect DCR register.
243 * Returns the read data.
246 mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
248 return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
249 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
254 * mtsdram - write controller register data
255 * @dcr_host: A pointer to the DCR mapping.
256 * @idcr_n: The indirect DCR register to write.
257 * @value: The data to write.
259 * This routine writes the provided data to the controller's specified
260 * indirect DCR register.
263 mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
265 return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
266 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
272 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
273 * @status: A pointer to the ECC status structure to check for an
275 * @bank: The bank to check for an ECC error.
277 * This routine determines whether the specified bank has an ECC
280 * Returns true if the specified bank has an ECC error; otherwise,
284 ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
289 return status->ecces & SDRAM_ECCES_BK0ER;
291 return status->ecces & SDRAM_ECCES_BK1ER;
298 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
299 * @mci: A pointer to the EDAC memory controller instance associated
300 * with the bank message being generated.
301 * @status: A pointer to the ECC status structure to generate the
303 * @buffer: A pointer to the buffer in which to generate the
305 * @size: The size, in bytes, of space available in buffer.
307 * This routine generates to the provided buffer the portion of the
308 * driver-unique report message associated with the ECCESS[BKNER]
309 * field of the specified ECC status.
311 * Returns the number of characters generated on success; otherwise, <
315 ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
316 const struct ppc4xx_ecc_status *status,
321 unsigned int row, rows;
323 n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
325 if (n < 0 || n >= size)
332 for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
333 if (ppc4xx_edac_check_bank_error(status, row)) {
334 n = snprintf(buffer, size, "%s%u",
335 (rows++ ? ", " : ""), row);
337 if (n < 0 || n >= size)
346 n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
348 if (n < 0 || n >= size)
360 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
361 * @mci: A pointer to the EDAC memory controller instance associated
362 * with the checkbit message being generated.
363 * @status: A pointer to the ECC status structure to generate the
365 * @buffer: A pointer to the buffer in which to generate the
367 * @size: The size, in bytes, of space available in buffer.
369 * This routine generates to the provided buffer the portion of the
370 * driver-unique report message associated with the ECCESS[CKBER]
371 * field of the specified ECC status.
373 * Returns the number of characters generated on success; otherwise, <
377 ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
378 const struct ppc4xx_ecc_status *status,
382 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
383 const char *ckber = NULL;
385 switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
386 case SDRAM_ECCES_CKBER_NONE:
389 case SDRAM_ECCES_CKBER_32_ECC_0_3:
392 case SDRAM_ECCES_CKBER_32_ECC_4_8:
393 switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
394 SDRAM_MCOPT1_WDTH_MASK) {
395 case SDRAM_MCOPT1_WDTH_16:
398 case SDRAM_MCOPT1_WDTH_32:
406 case SDRAM_ECCES_CKBER_32_ECC_0_8:
414 return snprintf(buffer, size, "Checkbit Error: %s", ckber);
418 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
419 * @mci: A pointer to the EDAC memory controller instance associated
420 * with the byte lane message being generated.
421 * @status: A pointer to the ECC status structure to generate the
423 * @buffer: A pointer to the buffer in which to generate the
425 * @size: The size, in bytes, of space available in buffer.
427 * This routine generates to the provided buffer the portion of the
428 * driver-unique report message associated with the ECCESS[BNCE]
429 * field of the specified ECC status.
431 * Returns the number of characters generated on success; otherwise, <
435 ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
436 const struct ppc4xx_ecc_status *status,
441 unsigned int lane, lanes;
442 const unsigned int first_lane = 0;
443 const unsigned int lane_count = 16;
445 n = snprintf(buffer, size, "; Byte Lane Errors: ");
447 if (n < 0 || n >= size)
454 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
455 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
456 n = snprintf(buffer, size,
458 (lanes++ ? ", " : ""), lane);
460 if (n < 0 || n >= size)
469 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
471 if (n < 0 || n >= size)
483 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
484 * @mci: A pointer to the EDAC memory controller instance associated
485 * with the ECCES message being generated.
486 * @status: A pointer to the ECC status structure to generate the
488 * @buffer: A pointer to the buffer in which to generate the
490 * @size: The size, in bytes, of space available in buffer.
492 * This routine generates to the provided buffer the portion of the
493 * driver-unique report message associated with the ECCESS register of
494 * the specified ECC status.
496 * Returns the number of characters generated on success; otherwise, <
500 ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
501 const struct ppc4xx_ecc_status *status,
507 n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
509 if (n < 0 || n >= size)
516 n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
518 if (n < 0 || n >= size)
525 n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
527 if (n < 0 || n >= size)
539 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
540 * @mci: A pointer to the EDAC memory controller instance associated
541 * with the PLB message being generated.
542 * @status: A pointer to the ECC status structure to generate the
544 * @buffer: A pointer to the buffer in which to generate the
546 * @size: The size, in bytes, of space available in buffer.
548 * This routine generates to the provided buffer the portion of the
549 * driver-unique report message associated with the PLB-related BESR
550 * and/or WMIRQ registers of the specified ECC status.
552 * Returns the number of characters generated on success; otherwise, <
556 ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
557 const struct ppc4xx_ecc_status *status,
564 if ((status->besr & SDRAM_BESR_MASK) == 0)
567 if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
570 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
572 master = SDRAM_BESR_M0ID_DECODE(status->besr);
574 return snprintf(buffer, size,
575 "%s error w/ PLB master %u \"%s\"; ",
576 (read ? "Read" : "Write"),
578 (((master >= SDRAM_PLB_M0ID_FIRST) &&
579 (master <= SDRAM_PLB_M0ID_LAST)) ?
580 ppc4xx_plb_masters[master] : "UNKNOWN"));
584 * ppc4xx_edac_generate_message - generate interpretted status message
585 * @mci: A pointer to the EDAC memory controller instance associated
586 * with the driver-unique message being generated.
587 * @status: A pointer to the ECC status structure to generate the
589 * @buffer: A pointer to the buffer in which to generate the
591 * @size: The size, in bytes, of space available in buffer.
593 * This routine generates to the provided buffer the driver-unique
594 * EDAC report message from the specified ECC status.
597 ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
598 const struct ppc4xx_ecc_status *status,
604 if (buffer == NULL || size == 0)
607 n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
609 if (n < 0 || n >= size)
615 ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
620 * ppc4xx_ecc_dump_status - dump controller ECC status registers
621 * @mci: A pointer to the EDAC memory controller instance
622 * associated with the status being dumped.
623 * @status: A pointer to the ECC status structure to generate the
626 * This routine dumps to the kernel log buffer the raw and
627 * interpretted specified ECC status.
630 ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
631 const struct ppc4xx_ecc_status *status)
633 char message[PPC4XX_EDAC_MESSAGE_SIZE];
635 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
637 ppc4xx_edac_mc_printk(KERN_INFO, mci,
642 "\tBEAR: 0x%08x%08x\n"
654 * ppc4xx_ecc_get_status - get controller ECC status
655 * @mci: A pointer to the EDAC memory controller instance
656 * associated with the status being retrieved.
657 * @status: A pointer to the ECC status structure to populate the
660 * This routine reads and masks, as appropriate, all the relevant
661 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
662 * While we read all of them, for correctable errors, we only expect
663 * to deal with ECCES. For uncorrectable errors, we expect to deal
667 ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
668 struct ppc4xx_ecc_status *status)
670 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
671 const dcr_host_t *dcr_host = &pdata->dcr_host;
673 status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
674 status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
675 status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
676 status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
677 status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
681 * ppc4xx_ecc_clear_status - clear controller ECC status
682 * @mci: A pointer to the EDAC memory controller instance
683 * associated with the status being cleared.
684 * @status: A pointer to the ECC status structure containing the
685 * values to write to clear the ECC status.
687 * This routine clears--by writing the masked (as appropriate) status
688 * values back to--the status registers that deal with
689 * ibm,sdram-4xx-ddr2 ECC errors.
692 ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
693 const struct ppc4xx_ecc_status *status)
695 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
696 const dcr_host_t *dcr_host = &pdata->dcr_host;
698 mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
699 mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
700 mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
701 mtsdram(dcr_host, SDRAM_BEARL, 0);
702 mtsdram(dcr_host, SDRAM_BEARH, 0);
706 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
707 * @mci: A pointer to the EDAC memory controller instance
708 * associated with the correctable error being handled and reported.
709 * @status: A pointer to the ECC status structure associated with
710 * the correctable error being handled and reported.
712 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
713 * correctable error. Per the aforementioned discussion, there's not
714 * enough status available to use the full EDAC correctable error
715 * interface, so we just pass driver-unique message to the "no info"
719 ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
720 const struct ppc4xx_ecc_status *status)
723 char message[PPC4XX_EDAC_MESSAGE_SIZE];
725 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
727 for (row = 0; row < mci->nr_csrows; row++)
728 if (ppc4xx_edac_check_bank_error(status, row))
729 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
736 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
737 * @mci: A pointer to the EDAC memory controller instance
738 * associated with the uncorrectable error being handled and
740 * @status: A pointer to the ECC status structure associated with
741 * the uncorrectable error being handled and reported.
743 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
744 * uncorrectable error.
747 ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
748 const struct ppc4xx_ecc_status *status)
750 const u64 bear = ((u64)status->bearh << 32 | status->bearl);
751 const unsigned long page = bear >> PAGE_SHIFT;
752 const unsigned long offset = bear & ~PAGE_MASK;
754 char message[PPC4XX_EDAC_MESSAGE_SIZE];
756 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
758 for (row = 0; row < mci->nr_csrows; row++)
759 if (ppc4xx_edac_check_bank_error(status, row))
760 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
767 * ppc4xx_edac_check - check controller for ECC errors
768 * @mci: A pointer to the EDAC memory controller instance
769 * associated with the ibm,sdram-4xx-ddr2 controller being
772 * This routine is used to check and post ECC errors and is called by
773 * both the EDAC polling thread and this driver's CE and UE interrupt
777 ppc4xx_edac_check(struct mem_ctl_info *mci)
780 static unsigned int count;
782 struct ppc4xx_ecc_status status;
784 ppc4xx_ecc_get_status(mci, &status);
787 if (count++ % 30 == 0)
788 ppc4xx_ecc_dump_status(mci, &status);
791 if (status.ecces & SDRAM_ECCES_UE)
792 ppc4xx_edac_handle_ue(mci, &status);
794 if (status.ecces & SDRAM_ECCES_CE)
795 ppc4xx_edac_handle_ce(mci, &status);
797 ppc4xx_ecc_clear_status(mci, &status);
801 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
802 * @irq: The virtual interrupt number being serviced.
803 * @dev_id: A pointer to the EDAC memory controller instance
804 * associated with the interrupt being handled.
806 * This routine implements the interrupt handler for both correctable
807 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
808 * controller. It simply calls through to the same routine used during
809 * polling to check, report and clear the ECC status.
811 * Unconditionally returns IRQ_HANDLED.
814 ppc4xx_edac_isr(int irq, void *dev_id)
816 struct mem_ctl_info *mci = dev_id;
818 ppc4xx_edac_check(mci);
824 * ppc4xx_edac_get_dtype - return the controller memory width
825 * @mcopt1: The 32-bit Memory Controller Option 1 register value
826 * currently set for the controller, from which the width
829 * This routine returns the EDAC device type width appropriate for the
830 * current controller configuration.
832 * TODO: This needs to be conditioned dynamically through feature
833 * flags or some such when other controller variants are supported as
834 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
835 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
838 * Returns a device type width enumeration.
840 static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1)
842 switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
843 case SDRAM_MCOPT1_WDTH_16:
845 case SDRAM_MCOPT1_WDTH_32:
853 * ppc4xx_edac_get_mtype - return controller memory type
854 * @mcopt1: The 32-bit Memory Controller Option 1 register value
855 * currently set for the controller, from which the memory type
858 * This routine returns the EDAC memory type appropriate for the
859 * current controller configuration.
861 * Returns a memory type enumeration.
863 static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1)
865 bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
867 switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
868 case SDRAM_MCOPT1_DDR2_TYPE:
869 return rden ? MEM_RDDR2 : MEM_DDR2;
870 case SDRAM_MCOPT1_DDR1_TYPE:
871 return rden ? MEM_RDDR : MEM_DDR;
878 * ppc4xx_edac_init_csrows - initialize driver instance rows
879 * @mci: A pointer to the EDAC memory controller instance
880 * associated with the ibm,sdram-4xx-ddr2 controller for which
881 * the csrows (i.e. banks/ranks) are being initialized.
882 * @mcopt1: The 32-bit Memory Controller Option 1 register value
883 * currently set for the controller, from which bank width
884 * and memory typ information is derived.
886 * This routine initializes the virtual "chip select rows" associated
887 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
888 * controller bank/rank is mapped to a row.
890 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
891 * configuration cannot be determined.
893 static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
895 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
899 enum edac_type edac_mode;
901 u32 mbxcf, size, nr_pages;
903 /* Establish the memory type and width */
905 mtype = ppc4xx_edac_get_mtype(mcopt1);
906 dtype = ppc4xx_edac_get_dtype(mcopt1);
908 /* Establish EDAC mode */
910 if (mci->edac_cap & EDAC_FLAG_SECDED)
911 edac_mode = EDAC_SECDED;
912 else if (mci->edac_cap & EDAC_FLAG_EC)
915 edac_mode = EDAC_NONE;
918 * Initialize each chip select row structure which correspond
919 * 1:1 with a controller bank/rank.
922 for (row = 0; row < mci->nr_csrows; row++) {
923 struct csrow_info *csi = &mci->csrows[row];
926 * Get the configuration settings for this
927 * row/bank/rank and skip disabled banks.
930 mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
932 if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
935 /* Map the bank configuration size setting to pages. */
937 size = mbxcf & SDRAM_MBCF_SZ_MASK;
940 case SDRAM_MBCF_SZ_4MB:
941 case SDRAM_MBCF_SZ_8MB:
942 case SDRAM_MBCF_SZ_16MB:
943 case SDRAM_MBCF_SZ_32MB:
944 case SDRAM_MBCF_SZ_64MB:
945 case SDRAM_MBCF_SZ_128MB:
946 case SDRAM_MBCF_SZ_256MB:
947 case SDRAM_MBCF_SZ_512MB:
948 case SDRAM_MBCF_SZ_1GB:
949 case SDRAM_MBCF_SZ_2GB:
950 case SDRAM_MBCF_SZ_4GB:
951 case SDRAM_MBCF_SZ_8GB:
952 nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
955 ppc4xx_edac_mc_printk(KERN_ERR, mci,
956 "Unrecognized memory bank %d "
958 row, SDRAM_MBCF_SZ_DECODE(size));
964 * It's unclear exactly what grain should be set to
965 * here. The SDRAM_ECCES register allows resolution of
966 * an error down to a nibble which would potentially
967 * argue for a grain of '1' byte, even though we only
968 * know the associated address for uncorrectable
969 * errors. This value is not used at present for
970 * anything other than error reporting so getting it
971 * wrong should be of little consequence. Other
972 * possible values would be the PLB width (16), the
973 * page size (PAGE_SIZE) or the memory width (2 or 4).
975 for (j = 0; j < csi->nr_channels; j++) {
976 struct dimm_info *dimm = csi->channels[j]->dimm;
978 dimm->nr_pages = nr_pages / csi->nr_channels;
984 dimm->edac_mode = edac_mode;
993 * ppc4xx_edac_mc_init - initialize driver instance
994 * @mci: A pointer to the EDAC memory controller instance being
996 * @op: A pointer to the OpenFirmware device tree node associated
997 * with the controller this EDAC instance is bound to.
998 * @dcr_host: A pointer to the DCR data containing the DCR mapping
999 * for this controller instance.
1000 * @mcopt1: The 32-bit Memory Controller Option 1 register value
1001 * currently set for the controller, from which ECC capabilities
1002 * and scrub mode are derived.
1004 * This routine performs initialization of the EDAC memory controller
1005 * instance and related driver-private data associated with the
1006 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1008 * Returns 0 if OK; otherwise, < 0 on error.
1010 static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
1011 struct platform_device *op,
1012 const dcr_host_t *dcr_host, u32 mcopt1)
1015 const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1016 struct ppc4xx_edac_pdata *pdata = NULL;
1017 const struct device_node *np = op->dev.of_node;
1019 if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
1022 /* Initial driver pointers and private data */
1024 mci->pdev = &op->dev;
1026 dev_set_drvdata(mci->pdev, mci);
1028 pdata = mci->pvt_info;
1030 pdata->dcr_host = *dcr_host;
1031 pdata->irqs.sec = NO_IRQ;
1032 pdata->irqs.ded = NO_IRQ;
1034 /* Initialize controller capabilities and configuration */
1036 mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1037 MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1039 mci->edac_ctl_cap = (EDAC_FLAG_NONE |
1043 mci->scrub_cap = SCRUB_NONE;
1044 mci->scrub_mode = SCRUB_NONE;
1047 * Update the actual capabilites based on the MCOPT1[MCHK]
1048 * settings. Scrubbing is only useful if reporting is enabled.
1052 case SDRAM_MCOPT1_MCHK_CHK:
1053 mci->edac_cap = EDAC_FLAG_EC;
1055 case SDRAM_MCOPT1_MCHK_CHK_REP:
1056 mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1057 mci->scrub_mode = SCRUB_SW_SRC;
1060 mci->edac_cap = EDAC_FLAG_NONE;
1064 /* Initialize strings */
1066 mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
1067 mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION;
1068 mci->ctl_name = ppc4xx_edac_match->compatible,
1069 mci->dev_name = np->full_name;
1071 /* Initialize callbacks */
1073 mci->edac_check = ppc4xx_edac_check;
1074 mci->ctl_page_to_phys = NULL;
1076 /* Initialize chip select rows */
1078 status = ppc4xx_edac_init_csrows(mci, mcopt1);
1081 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1082 "Failed to initialize rows!\n");
1088 * ppc4xx_edac_register_irq - setup and register controller interrupts
1089 * @op: A pointer to the OpenFirmware device tree node associated
1090 * with the controller this EDAC instance is bound to.
1091 * @mci: A pointer to the EDAC memory controller instance
1092 * associated with the ibm,sdram-4xx-ddr2 controller for which
1093 * interrupts are being registered.
1095 * This routine parses the correctable (CE) and uncorrectable error (UE)
1096 * interrupts from the device tree node and maps and assigns them to
1097 * the associated EDAC memory controller instance.
1099 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1100 * mapped and assigned.
1102 static int ppc4xx_edac_register_irq(struct platform_device *op,
1103 struct mem_ctl_info *mci)
1106 int ded_irq, sec_irq;
1107 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1108 struct device_node *np = op->dev.of_node;
1110 ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
1111 sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
1113 if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) {
1114 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1115 "Unable to map interrupts.\n");
1120 status = request_irq(ded_irq,
1127 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1128 "Unable to request irq %d for ECC DED",
1134 status = request_irq(sec_irq,
1141 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1142 "Unable to request irq %d for ECC SEC",
1148 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1149 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1151 pdata->irqs.ded = ded_irq;
1152 pdata->irqs.sec = sec_irq;
1157 free_irq(sec_irq, mci);
1160 free_irq(ded_irq, mci);
1167 * ppc4xx_edac_map_dcrs - locate and map controller registers
1168 * @np: A pointer to the device tree node containing the DCR
1170 * @dcr_host: A pointer to the DCR data to populate with the
1173 * This routine attempts to locate in the device tree and map the DCR
1174 * register resources associated with the controller's indirect DCR
1175 * address and data windows.
1177 * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1180 static int ppc4xx_edac_map_dcrs(const struct device_node *np,
1181 dcr_host_t *dcr_host)
1183 unsigned int dcr_base, dcr_len;
1185 if (np == NULL || dcr_host == NULL)
1188 /* Get the DCR resource extent and sanity check the values. */
1190 dcr_base = dcr_resource_start(np, 0);
1191 dcr_len = dcr_resource_len(np, 0);
1193 if (dcr_base == 0 || dcr_len == 0) {
1194 ppc4xx_edac_printk(KERN_ERR,
1195 "Failed to obtain DCR property.\n");
1199 if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1200 ppc4xx_edac_printk(KERN_ERR,
1201 "Unexpected DCR length %d, expected %d.\n",
1202 dcr_len, SDRAM_DCR_RESOURCE_LEN);
1206 /* Attempt to map the DCR extent. */
1208 *dcr_host = dcr_map(np, dcr_base, dcr_len);
1210 if (!DCR_MAP_OK(*dcr_host)) {
1211 ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1219 * ppc4xx_edac_probe - check controller and bind driver
1220 * @op: A pointer to the OpenFirmware device tree node associated
1221 * with the controller being probed for driver binding.
1223 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1224 * instance for binding with the driver.
1226 * Returns 0 if the controller instance was successfully bound to the
1227 * driver; otherwise, < 0 on error.
1229 static int ppc4xx_edac_probe(struct platform_device *op)
1232 u32 mcopt1, memcheck;
1233 dcr_host_t dcr_host;
1234 const struct device_node *np = op->dev.of_node;
1235 struct mem_ctl_info *mci = NULL;
1236 struct edac_mc_layer layers[2];
1237 static int ppc4xx_edac_instance;
1240 * At this point, we only support the controller realized on
1241 * the AMCC PPC 405EX[r]. Reject anything else.
1244 if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
1245 !of_device_is_compatible(np, "ibm,sdram-405exr")) {
1246 ppc4xx_edac_printk(KERN_NOTICE,
1247 "Only the PPC405EX[r] is supported.\n");
1252 * Next, get the DCR property and attempt to map it so that we
1253 * can probe the controller.
1256 status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1262 * First determine whether ECC is enabled at all. If not,
1263 * there is no useful checking or monitoring that can be done
1264 * for this controller.
1267 mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1268 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1270 if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
1271 ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or "
1272 "ECC is disabled.\n", np->full_name);
1278 * At this point, we know ECC is enabled, allocate an EDAC
1279 * controller instance and perform the appropriate
1282 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1283 layers[0].size = ppc4xx_edac_nr_csrows;
1284 layers[0].is_virt_csrow = true;
1285 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1286 layers[1].size = ppc4xx_edac_nr_chans;
1287 layers[1].is_virt_csrow = false;
1288 mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
1289 sizeof(struct ppc4xx_edac_pdata));
1291 ppc4xx_edac_printk(KERN_ERR, "%s: "
1292 "Failed to allocate EDAC MC instance!\n",
1298 status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
1301 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1302 "Failed to initialize instance!\n");
1307 * We have a valid, initialized EDAC instance bound to the
1308 * controller. Attempt to register it with the EDAC subsystem
1309 * and, if necessary, register interrupts.
1312 if (edac_mc_add_mc(mci)) {
1313 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1314 "Failed to add instance!\n");
1319 if (edac_op_state == EDAC_OPSTATE_INT) {
1320 status = ppc4xx_edac_register_irq(op, mci);
1326 ppc4xx_edac_instance++;
1331 edac_mc_del_mc(mci->pdev);
1341 * ppc4xx_edac_remove - unbind driver from controller
1342 * @op: A pointer to the OpenFirmware device tree node associated
1343 * with the controller this EDAC instance is to be unbound/removed
1346 * This routine unbinds the EDAC memory controller instance associated
1347 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1348 * OpenFirmware device tree node passed as a parameter.
1350 * Unconditionally returns 0.
1353 ppc4xx_edac_remove(struct platform_device *op)
1355 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1356 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1358 if (edac_op_state == EDAC_OPSTATE_INT) {
1359 free_irq(pdata->irqs.sec, mci);
1360 free_irq(pdata->irqs.ded, mci);
1363 dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1365 edac_mc_del_mc(mci->pdev);
1372 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1374 * This routine ensures that the EDAC memory controller reporting
1375 * method is mapped to a sane value as the EDAC core defines the value
1376 * to EDAC_OPSTATE_INVAL by default. We don't call the global
1377 * opstate_init as that defaults to polling and we want interrupt as
1380 static inline void __init
1381 ppc4xx_edac_opstate_init(void)
1383 switch (edac_op_state) {
1384 case EDAC_OPSTATE_POLL:
1385 case EDAC_OPSTATE_INT:
1388 edac_op_state = EDAC_OPSTATE_INT;
1392 ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1393 ((edac_op_state == EDAC_OPSTATE_POLL) ?
1394 EDAC_OPSTATE_POLL_STR :
1395 ((edac_op_state == EDAC_OPSTATE_INT) ?
1396 EDAC_OPSTATE_INT_STR :
1397 EDAC_OPSTATE_UNKNOWN_STR)));
1401 * ppc4xx_edac_init - driver/module insertion entry point
1403 * This routine is the driver/module insertion entry point. It
1404 * initializes the EDAC memory controller reporting state and
1405 * registers the driver as an OpenFirmware device tree platform
1409 ppc4xx_edac_init(void)
1411 ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1413 ppc4xx_edac_opstate_init();
1415 return platform_driver_register(&ppc4xx_edac_driver);
1419 * ppc4xx_edac_exit - driver/module removal entry point
1421 * This routine is the driver/module removal entry point. It
1422 * unregisters the driver as an OpenFirmware device tree platform
1426 ppc4xx_edac_exit(void)
1428 platform_driver_unregister(&ppc4xx_edac_driver);
1431 module_init(ppc4xx_edac_init);
1432 module_exit(ppc4xx_edac_exit);
1434 MODULE_LICENSE("GPL v2");
1435 MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1436 MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1437 module_param(edac_op_state, int, 0444);
1438 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1439 "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);