1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
27 #include "edac_core.h"
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
35 * Alter this version for the module when modifications are made
37 #define SBRIDGE_REVISION " Ver: 1.1.0 "
38 #define EDAC_MOD_STR "sbridge_edac"
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
56 * sbridge Memory Controller Registers
60 * FIXME: For now, let's order by device function, as it makes
61 * easier for driver's development process. This table should be
62 * moved to pci_id.h when submitted upstream
64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
85 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86 static const u32 sbridge_dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
91 static const u32 ibridge_dram_rule[] = {
92 0x60, 0x68, 0x70, 0x78, 0x80,
93 0x88, 0x90, 0x98, 0xa0, 0xa8,
94 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
95 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
98 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
99 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
100 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
101 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
103 static char *get_dram_attr(u32 reg)
105 switch(DRAM_ATTR(reg)) {
117 static const u32 sbridge_interleave_list[] = {
118 0x84, 0x8c, 0x94, 0x9c, 0xa4,
119 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
122 static const u32 ibridge_interleave_list[] = {
123 0x64, 0x6c, 0x74, 0x7c, 0x84,
124 0x8c, 0x94, 0x9c, 0xa4, 0xac,
125 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
126 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
129 struct interleave_pkg {
134 static const struct interleave_pkg sbridge_interleave_pkg[] = {
145 static const struct interleave_pkg ibridge_interleave_pkg[] = {
156 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
159 return GET_BITFIELD(reg, table[interleave].start,
160 table[interleave].end);
163 /* Devices 12 Function 7 */
168 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
169 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
171 /* Device 13 Function 6 */
173 #define SAD_TARGET 0xf0
175 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
177 #define SAD_CONTROL 0xf4
179 /* Device 14 function 0 */
181 static const u32 tad_dram_rule[] = {
182 0x40, 0x44, 0x48, 0x4c,
183 0x50, 0x54, 0x58, 0x5c,
184 0x60, 0x64, 0x68, 0x6c,
186 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
188 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
189 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
190 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
191 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
192 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
193 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
194 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
196 /* Device 15, function 0 */
200 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
201 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
202 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
204 /* Device 15, function 1 */
206 #define RASENABLES 0xac
207 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
209 /* Device 15, functions 2-5 */
211 static const int mtr_regs[] = {
215 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
216 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
217 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
218 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
219 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
221 static const u32 tad_ch_nilv_offset[] = {
222 0x90, 0x94, 0x98, 0x9c,
223 0xa0, 0xa4, 0xa8, 0xac,
224 0xb0, 0xb4, 0xb8, 0xbc,
226 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
227 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
229 static const u32 rir_way_limit[] = {
230 0x108, 0x10c, 0x110, 0x114, 0x118,
232 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
234 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
235 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
237 #define MAX_RIR_WAY 8
239 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
240 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
241 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
242 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
243 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
244 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
247 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
248 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
250 /* Device 16, functions 2-7 */
253 * FIXME: Implement the error count reads directly
256 static const u32 correrrcnt[] = {
257 0x104, 0x108, 0x10c, 0x110,
260 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
261 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
262 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
263 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
265 static const u32 correrrthrsld[] = {
266 0x11c, 0x120, 0x124, 0x128,
269 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
270 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
273 /* Device 17, function 0 */
275 #define SB_RANK_CFG_A 0x0328
277 #define IB_RANK_CFG_A 0x0320
283 #define NUM_CHANNELS 4
284 #define MAX_DIMMS 3 /* Max DIMMS per channel */
292 struct sbridge_info {
296 u64 (*get_tolm)(struct sbridge_pvt *pvt);
297 u64 (*get_tohm)(struct sbridge_pvt *pvt);
298 u64 (*rir_limit)(u32 reg);
299 const u32 *dram_rule;
300 const u32 *interleave_list;
301 const struct interleave_pkg *interleave_pkg;
304 u8 (*get_node_id)(struct sbridge_pvt *pvt);
305 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
308 struct sbridge_channel {
313 struct pci_id_descr {
318 struct pci_id_table {
319 const struct pci_id_descr *descr;
324 struct list_head list;
326 u8 node_id, source_id;
327 struct pci_dev **pdev;
329 struct mem_ctl_info *mci;
333 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
334 struct pci_dev *pci_sad0, *pci_sad1;
335 struct pci_dev *pci_ha0, *pci_ha1;
336 struct pci_dev *pci_br0, *pci_br1;
337 struct pci_dev *pci_tad[NUM_CHANNELS];
339 struct sbridge_dev *sbridge_dev;
341 struct sbridge_info info;
342 struct sbridge_channel channel[NUM_CHANNELS];
344 /* Memory type detection */
345 bool is_mirrored, is_lockstep, is_close_pg;
347 /* Fifo double buffers */
348 struct mce mce_entry[MCE_LOG_LEN];
349 struct mce mce_outentry[MCE_LOG_LEN];
351 /* Fifo in/out counters */
352 unsigned mce_in, mce_out;
354 /* Count indicator to show errors not got */
355 unsigned mce_overrun;
357 /* Memory description */
361 #define PCI_DESCR(device_id, opt) \
362 .dev_id = (device_id), \
365 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
366 /* Processor Home Agent */
367 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
369 /* Memory controller */
370 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
371 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
372 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
373 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
374 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
375 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
376 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
378 /* System Address Decoder */
379 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
380 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
382 /* Broadcast Registers */
383 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
386 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
387 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
388 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
389 {0,} /* 0 terminated list. */
392 /* This changes depending if 1HA or 2HA:
394 * 0x0eb8 (17.0) is DDRIO0
396 * 0x0ebc (17.4) is DDRIO0
398 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
399 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
402 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
403 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
404 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
405 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
406 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
407 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
408 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
409 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
410 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
411 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
412 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
413 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
414 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
415 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
416 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
418 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
419 /* Processor Home Agent */
420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
422 /* Memory controller */
423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
424 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
425 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
426 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
427 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
428 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
430 /* System Address Decoder */
431 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
433 /* Broadcast Registers */
434 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
435 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
437 /* Optional, mode 2HA */
438 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
440 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
441 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
443 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
444 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
446 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
447 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
450 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
451 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
452 {0,} /* 0 terminated list. */
456 * pci_device_id table for which devices we are looking for
458 static const struct pci_device_id sbridge_pci_tbl[] = {
459 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
460 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
461 {0,} /* 0 terminated list. */
465 /****************************************************************************
466 Ancillary status routines
467 ****************************************************************************/
469 static inline int numrank(u32 mtr)
471 int ranks = (1 << RANK_CNT_BITS(mtr));
474 edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",
475 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
482 static inline int numrow(u32 mtr)
484 int rows = (RANK_WIDTH_BITS(mtr) + 12);
486 if (rows < 13 || rows > 18) {
487 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
488 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
495 static inline int numcol(u32 mtr)
497 int cols = (COL_WIDTH_BITS(mtr) + 10);
500 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
501 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
508 static struct sbridge_dev *get_sbridge_dev(u8 bus)
510 struct sbridge_dev *sbridge_dev;
512 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
513 if (sbridge_dev->bus == bus)
520 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
521 const struct pci_id_table *table)
523 struct sbridge_dev *sbridge_dev;
525 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
529 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
531 if (!sbridge_dev->pdev) {
536 sbridge_dev->bus = bus;
537 sbridge_dev->n_devs = table->n_devs;
538 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
543 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
545 list_del(&sbridge_dev->list);
546 kfree(sbridge_dev->pdev);
550 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
554 /* Address range is 32:28 */
555 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
556 return GET_TOLM(reg);
559 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
563 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
564 return GET_TOHM(reg);
567 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
571 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
573 return GET_TOLM(reg);
576 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
580 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
582 return GET_TOHM(reg);
585 static u64 rir_limit(u32 reg)
587 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
590 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
595 if (pvt->pci_ddrio) {
596 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
598 if (GET_BITFIELD(reg, 11, 11))
599 /* FIXME: Can also be LRDIMM */
609 static u8 get_node_id(struct sbridge_pvt *pvt)
612 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
613 return GET_BITFIELD(reg, 0, 2);
616 static inline u8 sad_pkg_socket(u8 pkg)
618 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
619 return ((pkg >> 3) << 2) | (pkg & 0x3);
622 static inline u8 sad_pkg_ha(u8 pkg)
624 return (pkg >> 2) & 0x1;
627 /****************************************************************************
628 Memory check routines
629 ****************************************************************************/
630 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
632 struct pci_dev *pdev = NULL;
635 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
636 if (pdev && pdev->bus->number == bus)
644 * check_if_ecc_is_active() - Checks if ECC is active
647 static int check_if_ecc_is_active(const u8 bus, enum type type)
649 struct pci_dev *pdev = NULL;
652 if (type == IVY_BRIDGE)
653 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
655 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
657 pdev = get_pdev_same_bus(bus, id);
659 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
660 "%04x:%04x! on bus %02d\n",
661 PCI_VENDOR_ID_INTEL, id, bus);
665 pci_read_config_dword(pdev, MCMTR, &mcmtr);
666 if (!IS_ECC_ENABLED(mcmtr)) {
667 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
673 static int get_dimm_config(struct mem_ctl_info *mci)
675 struct sbridge_pvt *pvt = mci->pvt_info;
676 struct dimm_info *dimm;
677 unsigned i, j, banks, ranks, rows, cols, npages;
683 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
684 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
686 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
687 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
688 pvt->sbridge_dev->mc,
689 pvt->sbridge_dev->node_id,
690 pvt->sbridge_dev->source_id);
692 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
693 if (IS_MIRROR_ENABLED(reg)) {
694 edac_dbg(0, "Memory mirror is enabled\n");
695 pvt->is_mirrored = true;
697 edac_dbg(0, "Memory mirror is disabled\n");
698 pvt->is_mirrored = false;
701 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
702 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
703 edac_dbg(0, "Lockstep is enabled\n");
704 mode = EDAC_S8ECD8ED;
705 pvt->is_lockstep = true;
707 edac_dbg(0, "Lockstep is disabled\n");
708 mode = EDAC_S4ECD4ED;
709 pvt->is_lockstep = false;
711 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
712 edac_dbg(0, "address map is on closed page mode\n");
713 pvt->is_close_pg = true;
715 edac_dbg(0, "address map is on open page mode\n");
716 pvt->is_close_pg = false;
719 mtype = pvt->info.get_memory_type(pvt);
720 if (mtype == MEM_RDDR3)
721 edac_dbg(0, "Memory is registered\n");
722 else if (mtype == MEM_UNKNOWN)
723 edac_dbg(0, "Cannot determine memory type\n");
725 edac_dbg(0, "Memory is unregistered\n");
727 /* On all supported DDR3 DIMM types, there are 8 banks available */
730 for (i = 0; i < NUM_CHANNELS; i++) {
733 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
734 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
736 pci_read_config_dword(pvt->pci_tad[i],
738 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
739 if (IS_DIMM_PRESENT(mtr)) {
740 pvt->channel[i].dimms++;
742 ranks = numrank(mtr);
746 /* DDR3 has 8 I/O banks */
747 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
748 npages = MiB_TO_PAGES(size);
750 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
751 pvt->sbridge_dev->mc, i, j,
753 banks, ranks, rows, cols);
755 dimm->nr_pages = npages;
757 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
759 dimm->edac_mode = mode;
760 snprintf(dimm->label, sizeof(dimm->label),
761 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
762 pvt->sbridge_dev->source_id, i, j);
770 static void get_memory_layout(const struct mem_ctl_info *mci)
772 struct sbridge_pvt *pvt = mci->pvt_info;
773 int i, j, k, n_sads, n_tads, sad_interl;
781 * Step 1) Get TOLM/TOHM ranges
784 pvt->tolm = pvt->info.get_tolm(pvt);
785 tmp_mb = (1 + pvt->tolm) >> 20;
787 mb = div_u64_rem(tmp_mb, 1000, &kb);
788 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);
790 /* Address range is already 45:25 */
791 pvt->tohm = pvt->info.get_tohm(pvt);
792 tmp_mb = (1 + pvt->tohm) >> 20;
794 mb = div_u64_rem(tmp_mb, 1000, &kb);
795 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm);
798 * Step 2) Get SAD range and SAD Interleave list
799 * TAD registers contain the interleave wayness. However, it
800 * seems simpler to just discover it indirectly, with the
804 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
805 /* SAD_LIMIT Address range is 45:26 */
806 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
808 limit = SAD_LIMIT(reg);
810 if (!DRAM_RULE_ENABLE(reg))
816 tmp_mb = (limit + 1) >> 20;
817 mb = div_u64_rem(tmp_mb, 1000, &kb);
818 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
822 ((u64)tmp_mb) << 20L,
823 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
827 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
829 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
830 for (j = 0; j < 8; j++) {
831 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
832 if (j > 0 && sad_interl == pkg)
835 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
841 * Step 3) Get TAD range
844 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
845 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
847 limit = TAD_LIMIT(reg);
850 tmp_mb = (limit + 1) >> 20;
852 mb = div_u64_rem(tmp_mb, 1000, &kb);
853 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
855 ((u64)tmp_mb) << 20L,
867 * Step 4) Get TAD offsets, per each channel
869 for (i = 0; i < NUM_CHANNELS; i++) {
870 if (!pvt->channel[i].dimms)
872 for (j = 0; j < n_tads; j++) {
873 pci_read_config_dword(pvt->pci_tad[i],
874 tad_ch_nilv_offset[j],
876 tmp_mb = TAD_OFFSET(reg) >> 20;
877 mb = div_u64_rem(tmp_mb, 1000, &kb);
878 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
881 ((u64)tmp_mb) << 20L,
887 * Step 6) Get RIR Wayness/Limit, per each channel
889 for (i = 0; i < NUM_CHANNELS; i++) {
890 if (!pvt->channel[i].dimms)
892 for (j = 0; j < MAX_RIR_RANGES; j++) {
893 pci_read_config_dword(pvt->pci_tad[i],
897 if (!IS_RIR_VALID(reg))
900 tmp_mb = pvt->info.rir_limit(reg) >> 20;
901 rir_way = 1 << RIR_WAY(reg);
902 mb = div_u64_rem(tmp_mb, 1000, &kb);
903 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
906 ((u64)tmp_mb) << 20L,
910 for (k = 0; k < rir_way; k++) {
911 pci_read_config_dword(pvt->pci_tad[i],
914 tmp_mb = RIR_OFFSET(reg) << 6;
916 mb = div_u64_rem(tmp_mb, 1000, &kb);
917 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
920 ((u64)tmp_mb) << 20L,
921 (u32)RIR_RNK_TGT(reg),
928 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
930 struct sbridge_dev *sbridge_dev;
932 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
933 if (sbridge_dev->node_id == node_id)
934 return sbridge_dev->mci;
939 static int get_memory_error_data(struct mem_ctl_info *mci,
944 char **area_type, char *msg)
946 struct mem_ctl_info *new_mci;
947 struct sbridge_pvt *pvt = mci->pvt_info;
948 struct pci_dev *pci_ha;
949 int n_rir, n_sads, n_tads, sad_way, sck_xch;
950 int sad_interl, idx, base_ch;
952 unsigned sad_interleave[pvt->info.max_interleave];
954 u8 ch_way, sck_way, pkg, sad_ha = 0;
958 u64 ch_addr, offset, limit = 0, prv = 0;
962 * Step 0) Check if the address is at special memory ranges
963 * The check bellow is probably enough to fill all cases where
964 * the error is not inside a memory, except for the legacy
965 * range (e. g. VGA addresses). It is unlikely, however, that the
966 * memory controller would generate an error on that range.
968 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
969 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
972 if (addr >= (u64)pvt->tohm) {
973 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
980 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
981 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
984 if (!DRAM_RULE_ENABLE(reg))
987 limit = SAD_LIMIT(reg);
989 sprintf(msg, "Can't discover the memory socket");
996 if (n_sads == pvt->info.max_sad) {
997 sprintf(msg, "Can't discover the memory socket");
1000 *area_type = get_dram_attr(reg);
1001 interleave_mode = INTERLEAVE_MODE(reg);
1003 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1006 if (pvt->info.type == SANDY_BRIDGE) {
1007 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1008 for (sad_way = 0; sad_way < 8; sad_way++) {
1009 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1010 if (sad_way > 0 && sad_interl == pkg)
1012 sad_interleave[sad_way] = pkg;
1013 edac_dbg(0, "SAD interleave #%d: %d\n",
1014 sad_way, sad_interleave[sad_way]);
1016 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1017 pvt->sbridge_dev->mc,
1022 !interleave_mode ? "" : "XOR[18:16]");
1023 if (interleave_mode)
1024 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1026 idx = (addr >> 6) & 7;
1040 sprintf(msg, "Can't discover socket interleave");
1043 *socket = sad_interleave[idx];
1044 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1045 idx, sad_way, *socket);
1047 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1048 idx = (addr >> 6) & 7;
1049 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1050 *socket = sad_pkg_socket(pkg);
1051 sad_ha = sad_pkg_ha(pkg);
1052 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1053 idx, *socket, sad_ha);
1057 * Move to the proper node structure, in order to access the
1058 * right PCI registers
1060 new_mci = get_mci_for_node_id(*socket);
1062 sprintf(msg, "Struct for socket #%u wasn't initialized",
1067 pvt = mci->pvt_info;
1070 * Step 2) Get memory channel
1073 if (pvt->info.type == SANDY_BRIDGE)
1074 pci_ha = pvt->pci_ha0;
1077 pci_ha = pvt->pci_ha1;
1079 pci_ha = pvt->pci_ha0;
1081 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1082 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
1083 limit = TAD_LIMIT(reg);
1085 sprintf(msg, "Can't discover the memory channel");
1092 if (n_tads == MAX_TAD) {
1093 sprintf(msg, "Can't discover the memory channel");
1097 ch_way = TAD_CH(reg) + 1;
1098 sck_way = TAD_SOCK(reg) + 1;
1103 idx = addr >> (6 + sck_way);
1107 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1111 base_ch = TAD_TGT0(reg);
1114 base_ch = TAD_TGT1(reg);
1117 base_ch = TAD_TGT2(reg);
1120 base_ch = TAD_TGT3(reg);
1123 sprintf(msg, "Can't discover the TAD target");
1126 *channel_mask = 1 << base_ch;
1128 pci_read_config_dword(pvt->pci_tad[base_ch],
1129 tad_ch_nilv_offset[n_tads],
1132 if (pvt->is_mirrored) {
1133 *channel_mask |= 1 << ((base_ch + 2) % 4);
1137 sck_xch = 1 << sck_way * (ch_way >> 1);
1140 sprintf(msg, "Invalid mirror set. Can't decode addr");
1144 sck_xch = (1 << sck_way) * ch_way;
1146 if (pvt->is_lockstep)
1147 *channel_mask |= 1 << ((base_ch + 1) % 4);
1149 offset = TAD_OFFSET(tad_offset);
1151 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1162 /* Calculate channel address */
1163 /* Remove the TAD offset */
1165 if (offset > addr) {
1166 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1171 /* Store the low bits [0:6] of the addr */
1172 ch_addr = addr & 0x7f;
1173 /* Remove socket wayness and remove 6 bits */
1175 addr = div_u64(addr, sck_xch);
1177 /* Divide by channel way */
1178 addr = addr / ch_way;
1180 /* Recover the last 6 bits */
1181 ch_addr |= addr << 6;
1184 * Step 3) Decode rank
1186 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1187 pci_read_config_dword(pvt->pci_tad[base_ch],
1188 rir_way_limit[n_rir],
1191 if (!IS_RIR_VALID(reg))
1194 limit = pvt->info.rir_limit(reg);
1195 mb = div_u64_rem(limit >> 20, 1000, &kb);
1196 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1201 if (ch_addr <= limit)
1204 if (n_rir == MAX_RIR_RANGES) {
1205 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1209 rir_way = RIR_WAY(reg);
1210 if (pvt->is_close_pg)
1211 idx = (ch_addr >> 6);
1213 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1214 idx %= 1 << rir_way;
1216 pci_read_config_dword(pvt->pci_tad[base_ch],
1217 rir_offset[n_rir][idx],
1219 *rank = RIR_RNK_TGT(reg);
1221 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1231 /****************************************************************************
1232 Device initialization routines: put/get, init/exit
1233 ****************************************************************************/
1236 * sbridge_put_all_devices 'put' all the devices that we have
1237 * reserved via 'get'
1239 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1244 for (i = 0; i < sbridge_dev->n_devs; i++) {
1245 struct pci_dev *pdev = sbridge_dev->pdev[i];
1248 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1250 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1255 static void sbridge_put_all_devices(void)
1257 struct sbridge_dev *sbridge_dev, *tmp;
1259 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1260 sbridge_put_devices(sbridge_dev);
1261 free_sbridge_dev(sbridge_dev);
1265 static int sbridge_get_onedevice(struct pci_dev **prev,
1267 const struct pci_id_table *table,
1268 const unsigned devno)
1270 struct sbridge_dev *sbridge_dev;
1271 const struct pci_id_descr *dev_descr = &table->descr[devno];
1272 struct pci_dev *pdev = NULL;
1275 sbridge_printk(KERN_DEBUG,
1276 "Seeking for: PCI ID %04x:%04x\n",
1277 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1279 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1280 dev_descr->dev_id, *prev);
1288 if (dev_descr->optional)
1291 /* if the HA wasn't found */
1295 sbridge_printk(KERN_INFO,
1296 "Device not found: %04x:%04x\n",
1297 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1299 /* End of list, leave */
1302 bus = pdev->bus->number;
1304 sbridge_dev = get_sbridge_dev(bus);
1306 sbridge_dev = alloc_sbridge_dev(bus, table);
1314 if (sbridge_dev->pdev[devno]) {
1315 sbridge_printk(KERN_ERR,
1316 "Duplicated device for %04x:%04x\n",
1317 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1322 sbridge_dev->pdev[devno] = pdev;
1324 /* Be sure that the device is enabled */
1325 if (unlikely(pci_enable_device(pdev) < 0)) {
1326 sbridge_printk(KERN_ERR,
1327 "Couldn't enable %04x:%04x\n",
1328 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1332 edac_dbg(0, "Detected %04x:%04x\n",
1333 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1336 * As stated on drivers/pci/search.c, the reference count for
1337 * @from is always decremented if it is not %NULL. So, as we need
1338 * to get all devices up to null, we need to do a get for the device
1348 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1349 * devices we want to reference for this driver.
1350 * @num_mc: pointer to the memory controllers count, to be incremented in case
1352 * @table: model specific table
1354 * returns 0 in case of success or error code
1356 static int sbridge_get_all_devices(u8 *num_mc,
1357 const struct pci_id_table *table)
1360 struct pci_dev *pdev = NULL;
1362 while (table && table->descr) {
1363 for (i = 0; i < table->n_devs; i++) {
1366 rc = sbridge_get_onedevice(&pdev, num_mc,
1373 sbridge_put_all_devices();
1384 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1385 struct sbridge_dev *sbridge_dev)
1387 struct sbridge_pvt *pvt = mci->pvt_info;
1388 struct pci_dev *pdev;
1391 for (i = 0; i < sbridge_dev->n_devs; i++) {
1392 pdev = sbridge_dev->pdev[i];
1396 switch (pdev->device) {
1397 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1398 pvt->pci_sad0 = pdev;
1400 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1401 pvt->pci_sad1 = pdev;
1403 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1404 pvt->pci_br0 = pdev;
1406 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1407 pvt->pci_ha0 = pdev;
1409 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1412 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1413 pvt->pci_ras = pdev;
1415 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1416 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1417 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1418 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1420 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1421 pvt->pci_tad[id] = pdev;
1424 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1425 pvt->pci_ddrio = pdev;
1431 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1432 pdev->vendor, pdev->device,
1437 /* Check if everything were registered */
1438 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1439 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
1442 for (i = 0; i < NUM_CHANNELS; i++) {
1443 if (!pvt->pci_tad[i])
1449 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1453 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1454 PCI_VENDOR_ID_INTEL, pdev->device);
1458 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1459 struct sbridge_dev *sbridge_dev)
1461 struct sbridge_pvt *pvt = mci->pvt_info;
1462 struct pci_dev *pdev, *tmp;
1464 bool mode_2ha = false;
1466 tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1467 PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL);
1473 for (i = 0; i < sbridge_dev->n_devs; i++) {
1474 pdev = sbridge_dev->pdev[i];
1478 switch (pdev->device) {
1479 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1480 pvt->pci_ha0 = pdev;
1482 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1484 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1485 pvt->pci_ras = pdev;
1487 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1488 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1489 /* if we have 2 HAs active, channels 2 and 3
1490 * are in other device */
1494 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1495 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1497 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1498 pvt->pci_tad[id] = pdev;
1501 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1502 pvt->pci_ddrio = pdev;
1504 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1506 pvt->pci_ddrio = pdev;
1508 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1509 pvt->pci_sad0 = pdev;
1511 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1512 pvt->pci_br0 = pdev;
1514 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1515 pvt->pci_br1 = pdev;
1517 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1518 pvt->pci_ha1 = pdev;
1520 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1521 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1523 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2;
1525 /* we shouldn't have this device if we have just one
1528 pvt->pci_tad[id] = pdev;
1535 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1537 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1541 /* Check if everything were registered */
1542 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1543 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
1547 for (i = 0; i < NUM_CHANNELS; i++) {
1548 if (!pvt->pci_tad[i])
1554 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1558 sbridge_printk(KERN_ERR,
1559 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1564 /****************************************************************************
1565 Error check routines
1566 ****************************************************************************/
1569 * While Sandy Bridge has error count registers, SMI BIOS read values from
1570 * and resets the counters. So, they are not reliable for the OS to read
1571 * from them. So, we have no option but to just trust on whatever MCE is
1572 * telling us about the errors.
1574 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1575 const struct mce *m)
1577 struct mem_ctl_info *new_mci;
1578 struct sbridge_pvt *pvt = mci->pvt_info;
1579 enum hw_event_mc_err_type tp_event;
1580 char *type, *optype, msg[256];
1581 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1582 bool overflow = GET_BITFIELD(m->status, 62, 62);
1583 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1585 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1586 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1587 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1588 u32 channel = GET_BITFIELD(m->status, 0, 3);
1589 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1590 long channel_mask, first_channel;
1593 char *area_type = NULL;
1595 if (pvt->info.type == IVY_BRIDGE)
1598 recoverable = GET_BITFIELD(m->status, 56, 56);
1600 if (uncorrected_error) {
1603 tp_event = HW_EVENT_ERR_FATAL;
1606 tp_event = HW_EVENT_ERR_UNCORRECTED;
1610 tp_event = HW_EVENT_ERR_CORRECTED;
1614 * According with Table 15-9 of the Intel Architecture spec vol 3A,
1615 * memory errors should fit in this mask:
1616 * 000f 0000 1mmm cccc (binary)
1618 * f = Correction Report Filtering Bit. If 1, subsequent errors
1622 * If the mask doesn't match, report an error to the parsing logic
1624 if (! ((errcode & 0xef80) == 0x80)) {
1625 optype = "Can't parse: it is not a mem";
1627 switch (optypenum) {
1629 optype = "generic undef request error";
1632 optype = "memory read error";
1635 optype = "memory write error";
1638 optype = "addr/cmd error";
1641 optype = "memory scrubbing error";
1644 optype = "reserved";
1649 /* Only decode errors with an valid address (ADDRV) */
1650 if (!GET_BITFIELD(m->status, 58, 58))
1653 rc = get_memory_error_data(mci, m->addr, &socket,
1654 &channel_mask, &rank, &area_type, msg);
1657 new_mci = get_mci_for_node_id(socket);
1659 strcpy(msg, "Error: socket got corrupted!");
1663 pvt = mci->pvt_info;
1665 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1676 * FIXME: On some memory configurations (mirror, lockstep), the
1677 * Memory Controller can't point the error to a single DIMM. The
1678 * EDAC core should be handling the channel mask, in order to point
1679 * to the group of dimm's where the error may be happening.
1681 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
1682 channel = first_channel;
1684 snprintf(msg, sizeof(msg),
1685 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
1686 overflow ? " OVERFLOW" : "",
1687 (uncorrected_error && recoverable) ? " recoverable" : "",
1694 edac_dbg(0, "%s\n", msg);
1696 /* FIXME: need support for channel mask */
1698 /* Call the helper to output message */
1699 edac_mc_handle_error(tp_event, mci, core_err_cnt,
1700 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
1705 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
1712 * sbridge_check_error Retrieve and process errors reported by the
1713 * hardware. Called by the Core module.
1715 static void sbridge_check_error(struct mem_ctl_info *mci)
1717 struct sbridge_pvt *pvt = mci->pvt_info;
1723 * MCE first step: Copy all mce errors into a temporary buffer
1724 * We use a double buffering here, to reduce the risk of
1728 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1733 m = pvt->mce_outentry;
1734 if (pvt->mce_in + count > MCE_LOG_LEN) {
1735 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1737 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1743 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1745 pvt->mce_in += count;
1748 if (pvt->mce_overrun) {
1749 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1752 pvt->mce_overrun = 0;
1756 * MCE second step: parse errors and display
1758 for (i = 0; i < count; i++)
1759 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1763 * sbridge_mce_check_error Replicates mcelog routine to get errors
1764 * This routine simply queues mcelog errors, and
1765 * return. The error itself should be handled later
1766 * by sbridge_check_error.
1767 * WARNING: As this routine should be called at NMI time, extra care should
1768 * be taken to avoid deadlocks, and to be as fast as possible.
1770 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1773 struct mce *mce = (struct mce *)data;
1774 struct mem_ctl_info *mci;
1775 struct sbridge_pvt *pvt;
1778 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
1781 mci = get_mci_for_node_id(mce->socketid);
1784 pvt = mci->pvt_info;
1787 * Just let mcelog handle it if the error is
1788 * outside the memory controller. A memory error
1789 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1790 * bit 12 has an special meaning.
1792 if ((mce->status & 0xefff) >> 7 != 1)
1795 if (mce->mcgstatus & MCG_STATUS_MCIP)
1800 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
1802 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
1803 "Bank %d: %016Lx\n", mce->extcpu, type,
1804 mce->mcgstatus, mce->bank, mce->status);
1805 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
1806 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
1807 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
1809 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
1810 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
1811 mce->time, mce->socketid, mce->apicid);
1813 /* Only handle if it is the right mc controller */
1814 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
1818 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1824 /* Copy memory error at the ringbuffer */
1825 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1827 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1829 /* Handle fatal errors immediately */
1830 if (mce->mcgstatus & 1)
1831 sbridge_check_error(mci);
1833 /* Advice mcelog that the error were handled */
1837 static struct notifier_block sbridge_mce_dec = {
1838 .notifier_call = sbridge_mce_check_error,
1841 /****************************************************************************
1842 EDAC register/unregister logic
1843 ****************************************************************************/
1845 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1847 struct mem_ctl_info *mci = sbridge_dev->mci;
1848 struct sbridge_pvt *pvt;
1850 if (unlikely(!mci || !mci->pvt_info)) {
1851 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
1853 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1857 pvt = mci->pvt_info;
1859 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1860 mci, &sbridge_dev->pdev[0]->dev);
1862 /* Remove MC sysfs nodes */
1863 edac_mc_del_mc(mci->pdev);
1865 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
1866 kfree(mci->ctl_name);
1868 sbridge_dev->mci = NULL;
1871 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
1873 struct mem_ctl_info *mci;
1874 struct edac_mc_layer layers[2];
1875 struct sbridge_pvt *pvt;
1876 struct pci_dev *pdev = sbridge_dev->pdev[0];
1879 /* Check the number of active and not disabled channels */
1880 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
1881 if (unlikely(rc < 0))
1884 /* allocate a new MC control structure */
1885 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1886 layers[0].size = NUM_CHANNELS;
1887 layers[0].is_virt_csrow = false;
1888 layers[1].type = EDAC_MC_LAYER_SLOT;
1889 layers[1].size = MAX_DIMMS;
1890 layers[1].is_virt_csrow = true;
1891 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
1897 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1900 pvt = mci->pvt_info;
1901 memset(pvt, 0, sizeof(*pvt));
1903 /* Associate sbridge_dev and mci for future usage */
1904 pvt->sbridge_dev = sbridge_dev;
1905 sbridge_dev->mci = mci;
1907 mci->mtype_cap = MEM_FLAG_DDR3;
1908 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1909 mci->edac_cap = EDAC_FLAG_NONE;
1910 mci->mod_name = "sbridge_edac.c";
1911 mci->mod_ver = SBRIDGE_REVISION;
1912 mci->dev_name = pci_name(pdev);
1913 mci->ctl_page_to_phys = NULL;
1915 /* Set the function pointer to an actual operation function */
1916 mci->edac_check = sbridge_check_error;
1918 pvt->info.type = type;
1919 if (type == IVY_BRIDGE) {
1920 pvt->info.rankcfgr = IB_RANK_CFG_A;
1921 pvt->info.get_tolm = ibridge_get_tolm;
1922 pvt->info.get_tohm = ibridge_get_tohm;
1923 pvt->info.dram_rule = ibridge_dram_rule;
1924 pvt->info.get_memory_type = get_memory_type;
1925 pvt->info.get_node_id = get_node_id;
1926 pvt->info.rir_limit = rir_limit;
1927 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
1928 pvt->info.interleave_list = ibridge_interleave_list;
1929 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
1930 pvt->info.interleave_pkg = ibridge_interleave_pkg;
1931 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
1933 /* Store pci devices at mci for faster access */
1934 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
1935 if (unlikely(rc < 0))
1938 pvt->info.rankcfgr = SB_RANK_CFG_A;
1939 pvt->info.get_tolm = sbridge_get_tolm;
1940 pvt->info.get_tohm = sbridge_get_tohm;
1941 pvt->info.dram_rule = sbridge_dram_rule;
1942 pvt->info.get_memory_type = get_memory_type;
1943 pvt->info.get_node_id = get_node_id;
1944 pvt->info.rir_limit = rir_limit;
1945 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
1946 pvt->info.interleave_list = sbridge_interleave_list;
1947 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
1948 pvt->info.interleave_pkg = sbridge_interleave_pkg;
1949 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1951 /* Store pci devices at mci for faster access */
1952 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
1953 if (unlikely(rc < 0))
1958 /* Get dimm basic config and the memory layout */
1959 get_dimm_config(mci);
1960 get_memory_layout(mci);
1962 /* record ptr to the generic device */
1963 mci->pdev = &pdev->dev;
1965 /* add this new MC control structure to EDAC's list of MCs */
1966 if (unlikely(edac_mc_add_mc(mci))) {
1967 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1975 kfree(mci->ctl_name);
1977 sbridge_dev->mci = NULL;
1982 * sbridge_probe Probe for ONE instance of device to see if it is
1985 * 0 for FOUND a device
1986 * < 0 for error code
1989 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1993 struct sbridge_dev *sbridge_dev;
1996 /* get the pci devices we want to reserve for our use */
1997 mutex_lock(&sbridge_edac_lock);
2000 * All memory controllers are allocated at the first pass.
2002 if (unlikely(probed >= 1)) {
2003 mutex_unlock(&sbridge_edac_lock);
2008 if (pdev->device == PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA) {
2009 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2012 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2013 type = SANDY_BRIDGE;
2015 if (unlikely(rc < 0))
2019 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2020 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2021 mc, mc + 1, num_mc);
2022 sbridge_dev->mc = mc++;
2023 rc = sbridge_register_mci(sbridge_dev, type);
2024 if (unlikely(rc < 0))
2028 sbridge_printk(KERN_INFO, "Driver loaded.\n");
2030 mutex_unlock(&sbridge_edac_lock);
2034 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2035 sbridge_unregister_mci(sbridge_dev);
2037 sbridge_put_all_devices();
2039 mutex_unlock(&sbridge_edac_lock);
2044 * sbridge_remove destructor for one instance of device
2047 static void sbridge_remove(struct pci_dev *pdev)
2049 struct sbridge_dev *sbridge_dev;
2054 * we have a trouble here: pdev value for removal will be wrong, since
2055 * it will point to the X58 register used to detect that the machine
2056 * is a Nehalem or upper design. However, due to the way several PCI
2057 * devices are grouped together to provide MC functionality, we need
2058 * to use a different method for releasing the devices
2061 mutex_lock(&sbridge_edac_lock);
2063 if (unlikely(!probed)) {
2064 mutex_unlock(&sbridge_edac_lock);
2068 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2069 sbridge_unregister_mci(sbridge_dev);
2071 /* Release PCI resources */
2072 sbridge_put_all_devices();
2076 mutex_unlock(&sbridge_edac_lock);
2079 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2082 * sbridge_driver pci_driver structure for this module
2085 static struct pci_driver sbridge_driver = {
2086 .name = "sbridge_edac",
2087 .probe = sbridge_probe,
2088 .remove = sbridge_remove,
2089 .id_table = sbridge_pci_tbl,
2093 * sbridge_init Module entry function
2094 * Try to initialize this module for its devices
2096 static int __init sbridge_init(void)
2102 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2105 pci_rc = pci_register_driver(&sbridge_driver);
2107 mce_register_decode_chain(&sbridge_mce_dec);
2108 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2109 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2113 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2120 * sbridge_exit() Module exit function
2121 * Unregister the driver
2123 static void __exit sbridge_exit(void)
2126 pci_unregister_driver(&sbridge_driver);
2127 mce_unregister_decode_chain(&sbridge_mce_dec);
2130 module_init(sbridge_init);
2131 module_exit(sbridge_exit);
2133 module_param(edac_op_state, int, 0444);
2134 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2136 MODULE_LICENSE("GPL");
2137 MODULE_AUTHOR("Mauro Carvalho Chehab");
2138 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2139 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "