drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <asm/processor.h>
  25 #include <asm/mce.h>
  26
  27 #include "edac_core.h"
  28
  29 /* Static vars */
  30 static LIST_HEAD(sbridge_edac_list);
  31 static DEFINE_MUTEX(sbridge_edac_lock);
  32 static int probed;
  33
  34 /*
  35  * Alter this version for the module when modifications are made
  36  */
  37 #define SBRIDGE_REVISION    " Ver: 1.1.0 "
  38 #define EDAC_MOD_STR      "sbridge_edac"
  39
  40 /*
  41  * Debug macros
  42  */
  43 #define sbridge_printk(level, fmt, arg...)                      \
  44         edac_printk(level, "sbridge", fmt, ##arg)
  45
  46 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  47         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  48
  49 /*
  50  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  51  */
  52 #define GET_BITFIELD(v, lo, hi) \
  53         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  54
  55 /*
  56  * sbridge Memory Controller Registers
  57  */
  58
  59 /*
  60  * FIXME: For now, let's order by device function, as it makes
  61  * easier for driver's development process. This table should be
  62  * moved to pci_id.h when submitted upstream
  63  */
  64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0        0x3cf4  /* 12.6 */
  65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1        0x3cf6  /* 12.7 */
  66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR          0x3cf5  /* 13.6 */
  67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0     0x3ca0  /* 14.0 */
  68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA      0x3ca8  /* 15.0 */
  69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS     0x3c71  /* 15.1 */
  70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0    0x3caa  /* 15.2 */
  71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1    0x3cab  /* 15.3 */
  72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2    0x3cac  /* 15.4 */
  73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3    0x3cad  /* 15.5 */
  74 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO   0x3cb8  /* 17.0 */
  75
  76         /*
  77          * Currently, unused, but will be needed in the future
  78          * implementations, as they hold the error counters
  79          */
  80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0    0x3c72  /* 16.2 */
  81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1    0x3c73  /* 16.3 */
  82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2    0x3c76  /* 16.6 */
  83 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3    0x3c77  /* 16.7 */
  84
  85 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  86 static const u32 sbridge_dram_rule[] = {
  87         0x80, 0x88, 0x90, 0x98, 0xa0,
  88         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  89 };
  90
  91 static const u32 ibridge_dram_rule[] = {
  92         0x60, 0x68, 0x70, 0x78, 0x80,
  93         0x88, 0x90, 0x98, 0xa0, 0xa8,
  94         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  95         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  96 };
  97
  98 #define SAD_LIMIT(reg)          ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
  99 #define DRAM_ATTR(reg)          GET_BITFIELD(reg, 2,  3)
 100 #define INTERLEAVE_MODE(reg)    GET_BITFIELD(reg, 1,  1)
 101 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
 102 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
 103
 104 static char *get_dram_attr(u32 reg)
 105 {
 106         switch(DRAM_ATTR(reg)) {
 107                 case 0:
 108                         return "DRAM";
 109                 case 1:
 110                         return "MMCFG";
 111                 case 2:
 112                         return "NXM";
 113                 default:
 114                         return "unknown";
 115         }
 116 }
 117
 118 static const u32 sbridge_interleave_list[] = {
 119         0x84, 0x8c, 0x94, 0x9c, 0xa4,
 120         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
 121 };
 122
 123 static const u32 ibridge_interleave_list[] = {
 124         0x64, 0x6c, 0x74, 0x7c, 0x84,
 125         0x8c, 0x94, 0x9c, 0xa4, 0xac,
 126         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
 127         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
 128 };
 129
 130 struct interleave_pkg {
 131         unsigned char start;
 132         unsigned char end;
 133 };
 134
 135 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 136         { 0, 2 },
 137         { 3, 5 },
 138         { 8, 10 },
 139         { 11, 13 },
 140         { 16, 18 },
 141         { 19, 21 },
 142         { 24, 26 },
 143         { 27, 29 },
 144 };
 145
 146 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 147         { 0, 3 },
 148         { 4, 7 },
 149         { 8, 11 },
 150         { 12, 15 },
 151         { 16, 19 },
 152         { 20, 23 },
 153         { 24, 27 },
 154         { 28, 31 },
 155 };
 156
 157 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 158                           int interleave)
 159 {
 160         return GET_BITFIELD(reg, table[interleave].start,
 161                             table[interleave].end);
 162 }
 163
 164 /* Devices 12 Function 7 */
 165
 166 #define TOLM            0x80
 167 #define TOHM            0x84
 168 #define HASWELL_TOHM_0  0xd4
 169 #define HASWELL_TOHM_1  0xd8
 170
 171 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 172 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 173
 174 /* Device 13 Function 6 */
 175
 176 #define SAD_TARGET      0xf0
 177
 178 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 179
 180 #define SAD_CONTROL     0xf4
 181
 182 /* Device 14 function 0 */
 183
 184 static const u32 tad_dram_rule[] = {
 185         0x40, 0x44, 0x48, 0x4c,
 186         0x50, 0x54, 0x58, 0x5c,
 187         0x60, 0x64, 0x68, 0x6c,
 188 };
 189 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 190
 191 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 192 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 193 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 194 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 195 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 196 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 197 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 198
 199 /* Device 15, function 0 */
 200
 201 #define MCMTR                   0x7c
 202
 203 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 204 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 205 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 206
 207 /* Device 15, function 1 */
 208
 209 #define RASENABLES              0xac
 210 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 211
 212 /* Device 15, functions 2-5 */
 213
 214 static const int mtr_regs[] = {
 215         0x80, 0x84, 0x88,
 216 };
 217
 218 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 219 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 220 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 221 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 222 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 223
 224 static const u32 tad_ch_nilv_offset[] = {
 225         0x90, 0x94, 0x98, 0x9c,
 226         0xa0, 0xa4, 0xa8, 0xac,
 227         0xb0, 0xb4, 0xb8, 0xbc,
 228 };
 229 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 230 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 231
 232 static const u32 rir_way_limit[] = {
 233         0x108, 0x10c, 0x110, 0x114, 0x118,
 234 };
 235 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 236
 237 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 238 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 239
 240 #define MAX_RIR_WAY     8
 241
 242 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 243         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 244         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 245         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 246         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 247         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 248 };
 249
 250 #define RIR_RNK_TGT(reg)                GET_BITFIELD(reg, 16, 19)
 251 #define RIR_OFFSET(reg)         GET_BITFIELD(reg,  2, 14)
 252
 253 /* Device 16, functions 2-7 */
 254
 255 /*
 256  * FIXME: Implement the error count reads directly
 257  */
 258
 259 static const u32 correrrcnt[] = {
 260         0x104, 0x108, 0x10c, 0x110,
 261 };
 262
 263 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 264 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 265 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 266 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 267
 268 static const u32 correrrthrsld[] = {
 269         0x11c, 0x120, 0x124, 0x128,
 270 };
 271
 272 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 273 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 274
 275
 276 /* Device 17, function 0 */
 277
 278 #define SB_RANK_CFG_A           0x0328
 279
 280 #define IB_RANK_CFG_A           0x0320
 281
 282 /*
 283  * sbridge structs
 284  */
 285
 286 #define NUM_CHANNELS            4
 287 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 288 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 289
 290 enum type {
 291         SANDY_BRIDGE,
 292         IVY_BRIDGE,
 293         HASWELL,
 294 };
 295
 296 struct sbridge_pvt;
 297 struct sbridge_info {
 298         enum type       type;
 299         u32             mcmtr;
 300         u32             rankcfgr;
 301         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 302         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 303         u64             (*rir_limit)(u32 reg);
 304         const u32       *dram_rule;
 305         const u32       *interleave_list;
 306         const struct interleave_pkg *interleave_pkg;
 307         u8              max_sad;
 308         u8              max_interleave;
 309         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 310         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 311         struct pci_dev  *pci_vtd;
 312 };
 313
 314 struct sbridge_channel {
 315         u32             ranks;
 316         u32             dimms;
 317 };
 318
 319 struct pci_id_descr {
 320         int                     dev_id;
 321         int                     optional;
 322 };
 323
 324 struct pci_id_table {
 325         const struct pci_id_descr       *descr;
 326         int                             n_devs;
 327 };
 328
 329 struct sbridge_dev {
 330         struct list_head        list;
 331         u8                      bus, mc;
 332         u8                      node_id, source_id;
 333         struct pci_dev          **pdev;
 334         int                     n_devs;
 335         struct mem_ctl_info     *mci;
 336 };
 337
 338 struct sbridge_pvt {
 339         struct pci_dev          *pci_ta, *pci_ddrio, *pci_ras;
 340         struct pci_dev          *pci_sad0, *pci_sad1;
 341         struct pci_dev          *pci_ha0, *pci_ha1;
 342         struct pci_dev          *pci_br0, *pci_br1;
 343         struct pci_dev          *pci_ha1_ta;
 344         struct pci_dev          *pci_tad[NUM_CHANNELS];
 345
 346         struct sbridge_dev      *sbridge_dev;
 347
 348         struct sbridge_info     info;
 349         struct sbridge_channel  channel[NUM_CHANNELS];
 350
 351         /* Memory type detection */
 352         bool                    is_mirrored, is_lockstep, is_close_pg;
 353
 354         /* Fifo double buffers */
 355         struct mce              mce_entry[MCE_LOG_LEN];
 356         struct mce              mce_outentry[MCE_LOG_LEN];
 357
 358         /* Fifo in/out counters */
 359         unsigned                mce_in, mce_out;
 360
 361         /* Count indicator to show errors not got */
 362         unsigned                mce_overrun;
 363
 364         /* Memory description */
 365         u64                     tolm, tohm;
 366 };
 367
 368 #define PCI_DESCR(device_id, opt)       \
 369         .dev_id = (device_id),          \
 370         .optional = opt
 371
 372 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 373                 /* Processor Home Agent */
 374         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0)     },
 375
 376                 /* Memory controller */
 377         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0)      },
 378         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0)     },
 379         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0)    },
 380         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0)    },
 381         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0)    },
 382         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0)    },
 383         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1)   },
 384
 385                 /* System Address Decoder */
 386         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0)        },
 387         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0)        },
 388
 389                 /* Broadcast Registers */
 390         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0)          },
 391 };
 392
 393 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
 394 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 395         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
 396         {0,}                    /* 0 terminated list. */
 397 };
 398
 399 /* This changes depending if 1HA or 2HA:
 400  * 1HA:
 401  *      0x0eb8 (17.0) is DDRIO0
 402  * 2HA:
 403  *      0x0ebc (17.4) is DDRIO0
 404  */
 405 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 406 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 407
 408 /* pci ids */
 409 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 410 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 411 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 412 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 413 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 414 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 415 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 416 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 417 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 418 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 419 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 420 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 421 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 422 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 423 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 424
 425 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 426                 /* Processor Home Agent */
 427         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0)             },
 428
 429                 /* Memory controller */
 430         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0)          },
 431         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0)         },
 432         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0)        },
 433         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0)        },
 434         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0)        },
 435         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0)        },
 436
 437                 /* System Address Decoder */
 438         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0)                 },
 439
 440                 /* Broadcast Registers */
 441         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1)                 },
 442         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0)                 },
 443
 444                 /* Optional, mode 2HA */
 445         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1)             },
 446 #if 0
 447         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1)  },
 448         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
 449 #endif
 450         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1)        },
 451         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1)        },
 452
 453         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1)      },
 454         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1)      },
 455 };
 456
 457 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 458         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
 459         {0,}                    /* 0 terminated list. */
 460 };
 461
 462 /* Haswell support */
 463 /* EN processor:
 464  *      - 1 IMC
 465  *      - 3 DDR3 channels, 2 DPC per channel
 466  * EP processor:
 467  *      - 1 or 2 IMC
 468  *      - 4 DDR4 channels, 3 DPC per channel
 469  * EP 4S processor:
 470  *      - 2 IMC
 471  *      - 4 DDR4 channels, 3 DPC per channel
 472  * EX processor:
 473  *      - 2 IMC
 474  *      - each IMC interfaces with a SMI 2 channel
 475  *      - each SMI channel interfaces with a scalable memory buffer
 476  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 477  */
 478 #define HASWELL_DDRCRCLKCONTROLS 0xa10
 479 #define HASWELL_HASYSDEFEATURE2 0x84
 480 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 481 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 482 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 483 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 484 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
 485 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 486 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
 487 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 488 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 489 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 490 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 491 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 492 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 493 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 494 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 495 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 496 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 497 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 498 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 499         /* first item must be the HA */
 500         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0)             },
 501
 502         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0)        },
 503         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0)        },
 504
 505         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1)             },
 506
 507         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0)          },
 508         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0)     },
 509         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0)        },
 510         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0)        },
 511         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1)        },
 512         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1)        },
 513
 514         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1)          },
 515
 516         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1)          },
 517         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1)     },
 518         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1)        },
 519         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1)        },
 520         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1)        },
 521         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1)        },
 522 };
 523
 524 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 525         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
 526         {0,}                    /* 0 terminated list. */
 527 };
 528
 529 /*
 530  *      pci_device_id   table for which devices we are looking for
 531  */
 532 static const struct pci_device_id sbridge_pci_tbl[] = {
 533         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
 534         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
 535         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
 536         {0,}                    /* 0 terminated list. */
 537 };
 538
 539
 540 /****************************************************************************
 541                         Ancillary status routines
 542  ****************************************************************************/
 543
 544 static inline int numrank(enum type type, u32 mtr)
 545 {
 546         int ranks = (1 << RANK_CNT_BITS(mtr));
 547         int max = 4;
 548
 549         if (type == HASWELL)
 550                 max = 8;
 551
 552         if (ranks > max) {
 553                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 554                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 555                 return -EINVAL;
 556         }
 557
 558         return ranks;
 559 }
 560
 561 static inline int numrow(u32 mtr)
 562 {
 563         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 564
 565         if (rows < 13 || rows > 18) {
 566                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 567                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 568                 return -EINVAL;
 569         }
 570
 571         return 1 << rows;
 572 }
 573
 574 static inline int numcol(u32 mtr)
 575 {
 576         int cols = (COL_WIDTH_BITS(mtr) + 10);
 577
 578         if (cols > 12) {
 579                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 580                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 581                 return -EINVAL;
 582         }
 583
 584         return 1 << cols;
 585 }
 586
 587 static struct sbridge_dev *get_sbridge_dev(u8 bus)
 588 {
 589         struct sbridge_dev *sbridge_dev;
 590
 591         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
 592                 if (sbridge_dev->bus == bus)
 593                         return sbridge_dev;
 594         }
 595
 596         return NULL;
 597 }
 598
 599 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
 600                                            const struct pci_id_table *table)
 601 {
 602         struct sbridge_dev *sbridge_dev;
 603
 604         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 605         if (!sbridge_dev)
 606                 return NULL;
 607
 608         sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
 609                                    GFP_KERNEL);
 610         if (!sbridge_dev->pdev) {
 611                 kfree(sbridge_dev);
 612                 return NULL;
 613         }
 614
 615         sbridge_dev->bus = bus;
 616         sbridge_dev->n_devs = table->n_devs;
 617         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 618
 619         return sbridge_dev;
 620 }
 621
 622 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 623 {
 624         list_del(&sbridge_dev->list);
 625         kfree(sbridge_dev->pdev);
 626         kfree(sbridge_dev);
 627 }
 628
 629 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 630 {
 631         u32 reg;
 632
 633         /* Address range is 32:28 */
 634         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 635         return GET_TOLM(reg);
 636 }
 637
 638 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 639 {
 640         u32 reg;
 641
 642         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 643         return GET_TOHM(reg);
 644 }
 645
 646 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 647 {
 648         u32 reg;
 649
 650         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 651
 652         return GET_TOLM(reg);
 653 }
 654
 655 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 656 {
 657         u32 reg;
 658
 659         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 660
 661         return GET_TOHM(reg);
 662 }
 663
 664 static u64 rir_limit(u32 reg)
 665 {
 666         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 667 }
 668
 669 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 670 {
 671         u32 reg;
 672         enum mem_type mtype;
 673
 674         if (pvt->pci_ddrio) {
 675                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 676                                       &reg);
 677                 if (GET_BITFIELD(reg, 11, 11))
 678                         /* FIXME: Can also be LRDIMM */
 679                         mtype = MEM_RDDR3;
 680                 else
 681                         mtype = MEM_DDR3;
 682         } else
 683                 mtype = MEM_UNKNOWN;
 684
 685         return mtype;
 686 }
 687
 688 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 689 {
 690         u32 reg;
 691         bool registered = false;
 692         enum mem_type mtype = MEM_UNKNOWN;
 693
 694         if (!pvt->pci_ddrio)
 695                 goto out;
 696
 697         pci_read_config_dword(pvt->pci_ddrio,
 698                               HASWELL_DDRCRCLKCONTROLS, &reg);
 699         /* Is_Rdimm */
 700         if (GET_BITFIELD(reg, 16, 16))
 701                 registered = true;
 702
 703         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 704         if (GET_BITFIELD(reg, 14, 14)) {
 705                 if (registered)
 706                         mtype = MEM_RDDR4;
 707                 else
 708                         mtype = MEM_DDR4;
 709         } else {
 710                 if (registered)
 711                         mtype = MEM_RDDR3;
 712                 else
 713                         mtype = MEM_DDR3;
 714         }
 715
 716 out:
 717         return mtype;
 718 }
 719
 720 static u8 get_node_id(struct sbridge_pvt *pvt)
 721 {
 722         u32 reg;
 723         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 724         return GET_BITFIELD(reg, 0, 2);
 725 }
 726
 727 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 728 {
 729         u32 reg;
 730
 731         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 732         return GET_BITFIELD(reg, 0, 3);
 733 }
 734
 735 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
 736 {
 737         u32 reg;
 738
 739         pci_read_config_dword(pvt->info.pci_vtd, TOLM, &reg);
 740         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x1ffffff;
 741 }
 742
 743 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
 744 {
 745         u64 rc;
 746         u32 reg;
 747
 748         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
 749         rc = GET_BITFIELD(reg, 26, 31);
 750         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
 751         rc = ((reg << 6) | rc) << 26;
 752
 753         return rc | 0x1ffffff;
 754 }
 755
 756 static u64 haswell_rir_limit(u32 reg)
 757 {
 758         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
 759 }
 760
 761 static inline u8 sad_pkg_socket(u8 pkg)
 762 {
 763         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
 764         return ((pkg >> 3) << 2) | (pkg & 0x3);
 765 }
 766
 767 static inline u8 sad_pkg_ha(u8 pkg)
 768 {
 769         return (pkg >> 2) & 0x1;
 770 }
 771
 772 /****************************************************************************
 773                         Memory check routines
 774  ****************************************************************************/
 775 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
 776 {
 777         struct pci_dev *pdev = NULL;
 778
 779         do {
 780                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
 781                 if (pdev && pdev->bus->number == bus)
 782                         break;
 783         } while (pdev);
 784
 785         return pdev;
 786 }
 787
 788 /**
 789  * check_if_ecc_is_active() - Checks if ECC is active
 790  * @bus:        Device bus
 791  * @type:       Memory controller type
 792  * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
 793  *          disabled
 794  */
 795 static int check_if_ecc_is_active(const u8 bus, enum type type)
 796 {
 797         struct pci_dev *pdev = NULL;
 798         u32 mcmtr, id;
 799
 800         if (type == IVY_BRIDGE)
 801                 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
 802         else if (type == HASWELL)
 803                 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
 804         else
 805                 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
 806
 807         pdev = get_pdev_same_bus(bus, id);
 808         if (!pdev) {
 809                 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
 810                                         "%04x:%04x! on bus %02d\n",
 811                                         PCI_VENDOR_ID_INTEL, id, bus);
 812                 return -ENODEV;
 813         }
 814
 815         pci_read_config_dword(pdev, MCMTR, &mcmtr);
 816         if (!IS_ECC_ENABLED(mcmtr)) {
 817                 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
 818                 return -ENODEV;
 819         }
 820         return 0;
 821 }
 822
 823 static int get_dimm_config(struct mem_ctl_info *mci)
 824 {
 825         struct sbridge_pvt *pvt = mci->pvt_info;
 826         struct dimm_info *dimm;
 827         unsigned i, j, banks, ranks, rows, cols, npages;
 828         u64 size;
 829         u32 reg;
 830         enum edac_type mode;
 831         enum mem_type mtype;
 832
 833         if (pvt->info.type == HASWELL)
 834                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
 835         else
 836                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
 837
 838         pvt->sbridge_dev->source_id = SOURCE_ID(reg);
 839
 840         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
 841         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
 842                  pvt->sbridge_dev->mc,
 843                  pvt->sbridge_dev->node_id,
 844                  pvt->sbridge_dev->source_id);
 845
 846         pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
 847         if (IS_MIRROR_ENABLED(reg)) {
 848                 edac_dbg(0, "Memory mirror is enabled\n");
 849                 pvt->is_mirrored = true;
 850         } else {
 851                 edac_dbg(0, "Memory mirror is disabled\n");
 852                 pvt->is_mirrored = false;
 853         }
 854
 855         pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
 856         if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
 857                 edac_dbg(0, "Lockstep is enabled\n");
 858                 mode = EDAC_S8ECD8ED;
 859                 pvt->is_lockstep = true;
 860         } else {
 861                 edac_dbg(0, "Lockstep is disabled\n");
 862                 mode = EDAC_S4ECD4ED;
 863                 pvt->is_lockstep = false;
 864         }
 865         if (IS_CLOSE_PG(pvt->info.mcmtr)) {
 866                 edac_dbg(0, "address map is on closed page mode\n");
 867                 pvt->is_close_pg = true;
 868         } else {
 869                 edac_dbg(0, "address map is on open page mode\n");
 870                 pvt->is_close_pg = false;
 871         }
 872
 873         mtype = pvt->info.get_memory_type(pvt);
 874         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
 875                 edac_dbg(0, "Memory is registered\n");
 876         else if (mtype == MEM_UNKNOWN)
 877                 edac_dbg(0, "Cannot determine memory type\n");
 878         else
 879                 edac_dbg(0, "Memory is unregistered\n");
 880
 881         if (mtype == MEM_DDR4 || MEM_RDDR4)
 882                 banks = 16;
 883         else
 884                 banks = 8;
 885
 886         for (i = 0; i < NUM_CHANNELS; i++) {
 887                 u32 mtr;
 888
 889                 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
 890                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
 891                                        i, j, 0);
 892                         pci_read_config_dword(pvt->pci_tad[i],
 893                                               mtr_regs[j], &mtr);
 894                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
 895                         if (IS_DIMM_PRESENT(mtr)) {
 896                                 pvt->channel[i].dimms++;
 897
 898                                 ranks = numrank(pvt->info.type, mtr);
 899                                 rows = numrow(mtr);
 900                                 cols = numcol(mtr);
 901
 902                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
 903                                 npages = MiB_TO_PAGES(size);
 904
 905                                 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
 906                                          pvt->sbridge_dev->mc, i, j,
 907                                          size, npages,
 908                                          banks, ranks, rows, cols);
 909
 910                                 dimm->nr_pages = npages;
 911                                 dimm->grain = 32;
 912                                 switch (banks) {
 913                                 case 16:
 914                                         dimm->dtype = DEV_X16;
 915                                         break;
 916                                 case 8:
 917                                         dimm->dtype = DEV_X8;
 918                                         break;
 919                                 case 4:
 920                                         dimm->dtype = DEV_X4;
 921                                         break;
 922                                 }
 923                                 dimm->mtype = mtype;
 924                                 dimm->edac_mode = mode;
 925                                 snprintf(dimm->label, sizeof(dimm->label),
 926                                          "CPU_SrcID#%u_Channel#%u_DIMM#%u",
 927                                          pvt->sbridge_dev->source_id, i, j);
 928                         }
 929                 }
 930         }
 931
 932         return 0;
 933 }
 934
 935 static void get_memory_layout(const struct mem_ctl_info *mci)
 936 {
 937         struct sbridge_pvt *pvt = mci->pvt_info;
 938         int i, j, k, n_sads, n_tads, sad_interl;
 939         u32 reg;
 940         u64 limit, prv = 0;
 941         u64 tmp_mb;
 942         u32 mb, kb;
 943         u32 rir_way;
 944
 945         /*
 946          * Step 1) Get TOLM/TOHM ranges
 947          */
 948
 949         pvt->tolm = pvt->info.get_tolm(pvt);
 950         tmp_mb = (1 + pvt->tolm) >> 20;
 951
 952         mb = div_u64_rem(tmp_mb, 1000, &kb);
 953         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);
 954
 955         /* Address range is already 45:25 */
 956         pvt->tohm = pvt->info.get_tohm(pvt);
 957         tmp_mb = (1 + pvt->tohm) >> 20;
 958
 959         mb = div_u64_rem(tmp_mb, 1000, &kb);
 960         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm);
 961
 962         /*
 963          * Step 2) Get SAD range and SAD Interleave list
 964          * TAD registers contain the interleave wayness. However, it
 965          * seems simpler to just discover it indirectly, with the
 966          * algorithm bellow.
 967          */
 968         prv = 0;
 969         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
 970                 /* SAD_LIMIT Address range is 45:26 */
 971                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
 972                                       &reg);
 973                 limit = SAD_LIMIT(reg);
 974
 975                 if (!DRAM_RULE_ENABLE(reg))
 976                         continue;
 977
 978                 if (limit <= prv)
 979                         break;
 980
 981                 tmp_mb = (limit + 1) >> 20;
 982                 mb = div_u64_rem(tmp_mb, 1000, &kb);
 983                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
 984                          n_sads,
 985                          get_dram_attr(reg),
 986                          mb, kb,
 987                          ((u64)tmp_mb) << 20L,
 988                          INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
 989                          reg);
 990                 prv = limit;
 991
 992                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
 993                                       &reg);
 994                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
 995                 for (j = 0; j < 8; j++) {
 996                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
 997                         if (j > 0 && sad_interl == pkg)
 998                                 break;
 999
1000                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1001                                  n_sads, j, pkg);
1002                 }
1003         }
1004
1005         /*
1006          * Step 3) Get TAD range
1007          */
1008         prv = 0;
1009         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1010                 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1011                                       &reg);
1012                 limit = TAD_LIMIT(reg);
1013                 if (limit <= prv)
1014                         break;
1015                 tmp_mb = (limit + 1) >> 20;
1016
1017                 mb = div_u64_rem(tmp_mb, 1000, &kb);
1018                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1019                          n_tads, mb, kb,
1020                          ((u64)tmp_mb) << 20L,
1021                          (u32)TAD_SOCK(reg),
1022                          (u32)TAD_CH(reg),
1023                          (u32)TAD_TGT0(reg),
1024                          (u32)TAD_TGT1(reg),
1025                          (u32)TAD_TGT2(reg),
1026                          (u32)TAD_TGT3(reg),
1027                          reg);
1028                 prv = limit;
1029         }
1030
1031         /*
1032          * Step 4) Get TAD offsets, per each channel
1033          */
1034         for (i = 0; i < NUM_CHANNELS; i++) {
1035                 if (!pvt->channel[i].dimms)
1036                         continue;
1037                 for (j = 0; j < n_tads; j++) {
1038                         pci_read_config_dword(pvt->pci_tad[i],
1039                                               tad_ch_nilv_offset[j],
1040                                               &reg);
1041                         tmp_mb = TAD_OFFSET(reg) >> 20;
1042                         mb = div_u64_rem(tmp_mb, 1000, &kb);
1043                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1044                                  i, j,
1045                                  mb, kb,
1046                                  ((u64)tmp_mb) << 20L,
1047                                  reg);
1048                 }
1049         }
1050
1051         /*
1052          * Step 6) Get RIR Wayness/Limit, per each channel
1053          */
1054         for (i = 0; i < NUM_CHANNELS; i++) {
1055                 if (!pvt->channel[i].dimms)
1056                         continue;
1057                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1058                         pci_read_config_dword(pvt->pci_tad[i],
1059                                               rir_way_limit[j],
1060                                               &reg);
1061
1062                         if (!IS_RIR_VALID(reg))
1063                                 continue;
1064
1065                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1066                         rir_way = 1 << RIR_WAY(reg);
1067                         mb = div_u64_rem(tmp_mb, 1000, &kb);
1068                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1069                                  i, j,
1070                                  mb, kb,
1071                                  ((u64)tmp_mb) << 20L,
1072                                  rir_way,
1073                                  reg);
1074
1075                         for (k = 0; k < rir_way; k++) {
1076                                 pci_read_config_dword(pvt->pci_tad[i],
1077                                                       rir_offset[j][k],
1078                                                       &reg);
1079                                 tmp_mb = RIR_OFFSET(reg) << 6;
1080
1081                                 mb = div_u64_rem(tmp_mb, 1000, &kb);
1082                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1083                                          i, j, k,
1084                                          mb, kb,
1085                                          ((u64)tmp_mb) << 20L,
1086                                          (u32)RIR_RNK_TGT(reg),
1087                                          reg);
1088                         }
1089                 }
1090         }
1091 }
1092
1093 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1094 {
1095         struct sbridge_dev *sbridge_dev;
1096
1097         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1098                 if (sbridge_dev->node_id == node_id)
1099                         return sbridge_dev->mci;
1100         }
1101         return NULL;
1102 }
1103
1104 static int get_memory_error_data(struct mem_ctl_info *mci,
1105                                  u64 addr,
1106                                  u8 *socket,
1107                                  long *channel_mask,
1108                                  u8 *rank,
1109                                  char **area_type, char *msg)
1110 {
1111         struct mem_ctl_info     *new_mci;
1112         struct sbridge_pvt *pvt = mci->pvt_info;
1113         struct pci_dev          *pci_ha;
1114         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1115         int                     sad_interl, idx, base_ch;
1116         int                     interleave_mode, shiftup = 0;
1117         unsigned                sad_interleave[pvt->info.max_interleave];
1118         u32                     reg, dram_rule;
1119         u8                      ch_way, sck_way, pkg, sad_ha = 0;
1120         u32                     tad_offset;
1121         u32                     rir_way;
1122         u32                     mb, kb;
1123         u64                     ch_addr, offset, limit = 0, prv = 0;
1124
1125
1126         /*
1127          * Step 0) Check if the address is at special memory ranges
1128          * The check bellow is probably enough to fill all cases where
1129          * the error is not inside a memory, except for the legacy
1130          * range (e. g. VGA addresses). It is unlikely, however, that the
1131          * memory controller would generate an error on that range.
1132          */
1133         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1134                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1135                 return -EINVAL;
1136         }
1137         if (addr >= (u64)pvt->tohm) {
1138                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1139                 return -EINVAL;
1140         }
1141
1142         /*
1143          * Step 1) Get socket
1144          */
1145         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1146                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1147                                       &reg);
1148
1149                 if (!DRAM_RULE_ENABLE(reg))
1150                         continue;
1151
1152                 limit = SAD_LIMIT(reg);
1153                 if (limit <= prv) {
1154                         sprintf(msg, "Can't discover the memory socket");
1155                         return -EINVAL;
1156                 }
1157                 if  (addr <= limit)
1158                         break;
1159                 prv = limit;
1160         }
1161         if (n_sads == pvt->info.max_sad) {
1162                 sprintf(msg, "Can't discover the memory socket");
1163                 return -EINVAL;
1164         }
1165         dram_rule = reg;
1166         *area_type = get_dram_attr(dram_rule);
1167         interleave_mode = INTERLEAVE_MODE(dram_rule);
1168
1169         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1170                               &reg);
1171
1172         if (pvt->info.type == SANDY_BRIDGE) {
1173                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1174                 for (sad_way = 0; sad_way < 8; sad_way++) {
1175                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1176                         if (sad_way > 0 && sad_interl == pkg)
1177                                 break;
1178                         sad_interleave[sad_way] = pkg;
1179                         edac_dbg(0, "SAD interleave #%d: %d\n",
1180                                  sad_way, sad_interleave[sad_way]);
1181                 }
1182                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1183                          pvt->sbridge_dev->mc,
1184                          n_sads,
1185                          addr,
1186                          limit,
1187                          sad_way + 7,
1188                          !interleave_mode ? "" : "XOR[18:16]");
1189                 if (interleave_mode)
1190                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1191                 else
1192                         idx = (addr >> 6) & 7;
1193                 switch (sad_way) {
1194                 case 1:
1195                         idx = 0;
1196                         break;
1197                 case 2:
1198                         idx = idx & 1;
1199                         break;
1200                 case 4:
1201                         idx = idx & 3;
1202                         break;
1203                 case 8:
1204                         break;
1205                 default:
1206                         sprintf(msg, "Can't discover socket interleave");
1207                         return -EINVAL;
1208                 }
1209                 *socket = sad_interleave[idx];
1210                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1211                          idx, sad_way, *socket);
1212         } else if (pvt->info.type == HASWELL) {
1213                 int bits, a7mode = A7MODE(dram_rule);
1214
1215                 if (a7mode) {
1216                         /* A7 mode swaps P9 with P6 */
1217                         bits = GET_BITFIELD(addr, 7, 8) << 1;
1218                         bits |= GET_BITFIELD(addr, 9, 9);
1219                 } else
1220                         bits = GET_BITFIELD(addr, 7, 9);
1221
1222                 if (interleave_mode) {
1223                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
1224                         idx = GET_BITFIELD(addr, 16, 18);
1225                         idx ^= bits;
1226                 } else
1227                         idx = bits;
1228
1229                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1230                 *socket = sad_pkg_socket(pkg);
1231                 sad_ha = sad_pkg_ha(pkg);
1232
1233                 if (a7mode) {
1234                         /* MCChanShiftUpEnable */
1235                         pci_read_config_dword(pvt->pci_ha0,
1236                                               HASWELL_HASYSDEFEATURE2, &reg);
1237                         shiftup = GET_BITFIELD(reg, 22, 22);
1238                 }
1239
1240                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1241                          idx, *socket, sad_ha, shiftup);
1242         } else {
1243                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1244                 idx = (addr >> 6) & 7;
1245                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1246                 *socket = sad_pkg_socket(pkg);
1247                 sad_ha = sad_pkg_ha(pkg);
1248                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1249                          idx, *socket, sad_ha);
1250         }
1251
1252         /*
1253          * Move to the proper node structure, in order to access the
1254          * right PCI registers
1255          */
1256         new_mci = get_mci_for_node_id(*socket);
1257         if (!new_mci) {
1258                 sprintf(msg, "Struct for socket #%u wasn't initialized",
1259                         *socket);
1260                 return -EINVAL;
1261         }
1262         mci = new_mci;
1263         pvt = mci->pvt_info;
1264
1265         /*
1266          * Step 2) Get memory channel
1267          */
1268         prv = 0;
1269         if (pvt->info.type == SANDY_BRIDGE)
1270                 pci_ha = pvt->pci_ha0;
1271         else {
1272                 if (sad_ha)
1273                         pci_ha = pvt->pci_ha1;
1274                 else
1275                         pci_ha = pvt->pci_ha0;
1276         }
1277         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1278                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
1279                 limit = TAD_LIMIT(reg);
1280                 if (limit <= prv) {
1281                         sprintf(msg, "Can't discover the memory channel");
1282                         return -EINVAL;
1283                 }
1284                 if  (addr <= limit)
1285                         break;
1286                 prv = limit;
1287         }
1288         if (n_tads == MAX_TAD) {
1289                 sprintf(msg, "Can't discover the memory channel");
1290                 return -EINVAL;
1291         }
1292
1293         ch_way = TAD_CH(reg) + 1;
1294         sck_way = TAD_SOCK(reg) + 1;
1295
1296         if (ch_way == 3)
1297                 idx = addr >> 6;
1298         else
1299                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1300         idx = idx % ch_way;
1301
1302         /*
1303          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1304          */
1305         switch (idx) {
1306         case 0:
1307                 base_ch = TAD_TGT0(reg);
1308                 break;
1309         case 1:
1310                 base_ch = TAD_TGT1(reg);
1311                 break;
1312         case 2:
1313                 base_ch = TAD_TGT2(reg);
1314                 break;
1315         case 3:
1316                 base_ch = TAD_TGT3(reg);
1317                 break;
1318         default:
1319                 sprintf(msg, "Can't discover the TAD target");
1320                 return -EINVAL;
1321         }
1322         *channel_mask = 1 << base_ch;
1323
1324         pci_read_config_dword(pvt->pci_tad[base_ch],
1325                                 tad_ch_nilv_offset[n_tads],
1326                                 &tad_offset);
1327
1328         if (pvt->is_mirrored) {
1329                 *channel_mask |= 1 << ((base_ch + 2) % 4);
1330                 switch(ch_way) {
1331                 case 2:
1332                 case 4:
1333                         sck_xch = 1 << sck_way * (ch_way >> 1);
1334                         break;
1335                 default:
1336                         sprintf(msg, "Invalid mirror set. Can't decode addr");
1337                         return -EINVAL;
1338                 }
1339         } else
1340                 sck_xch = (1 << sck_way) * ch_way;
1341
1342         if (pvt->is_lockstep)
1343                 *channel_mask |= 1 << ((base_ch + 1) % 4);
1344
1345         offset = TAD_OFFSET(tad_offset);
1346
1347         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1348                  n_tads,
1349                  addr,
1350                  limit,
1351                  (u32)TAD_SOCK(reg),
1352                  ch_way,
1353                  offset,
1354                  idx,
1355                  base_ch,
1356                  *channel_mask);
1357
1358         /* Calculate channel address */
1359         /* Remove the TAD offset */
1360
1361         if (offset > addr) {
1362                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1363                         offset, addr);
1364                 return -EINVAL;
1365         }
1366         addr -= offset;
1367         /* Store the low bits [0:6] of the addr */
1368         ch_addr = addr & 0x7f;
1369         /* Remove socket wayness and remove 6 bits */
1370         addr >>= 6;
1371         addr = div_u64(addr, sck_xch);
1372 #if 0
1373         /* Divide by channel way */
1374         addr = addr / ch_way;
1375 #endif
1376         /* Recover the last 6 bits */
1377         ch_addr |= addr << 6;
1378
1379         /*
1380          * Step 3) Decode rank
1381          */
1382         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1383                 pci_read_config_dword(pvt->pci_tad[base_ch],
1384                                       rir_way_limit[n_rir],
1385                                       &reg);
1386
1387                 if (!IS_RIR_VALID(reg))
1388                         continue;
1389
1390                 limit = pvt->info.rir_limit(reg);
1391                 mb = div_u64_rem(limit >> 20, 1000, &kb);
1392                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1393                          n_rir,
1394                          mb, kb,
1395                          limit,
1396                          1 << RIR_WAY(reg));
1397                 if  (ch_addr <= limit)
1398                         break;
1399         }
1400         if (n_rir == MAX_RIR_RANGES) {
1401                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1402                         ch_addr);
1403                 return -EINVAL;
1404         }
1405         rir_way = RIR_WAY(reg);
1406
1407         if (pvt->is_close_pg)
1408                 idx = (ch_addr >> 6);
1409         else
1410                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
1411         idx %= 1 << rir_way;
1412
1413         pci_read_config_dword(pvt->pci_tad[base_ch],
1414                               rir_offset[n_rir][idx],
1415                               &reg);
1416         *rank = RIR_RNK_TGT(reg);
1417
1418         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1419                  n_rir,
1420                  ch_addr,
1421                  limit,
1422                  rir_way,
1423                  idx);
1424
1425         return 0;
1426 }
1427
1428 /****************************************************************************
1429         Device initialization routines: put/get, init/exit
1430  ****************************************************************************/
1431
1432 /*
1433  *      sbridge_put_all_devices 'put' all the devices that we have
1434  *                              reserved via 'get'
1435  */
1436 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1437 {
1438         int i;
1439
1440         edac_dbg(0, "\n");
1441         for (i = 0; i < sbridge_dev->n_devs; i++) {
1442                 struct pci_dev *pdev = sbridge_dev->pdev[i];
1443                 if (!pdev)
1444                         continue;
1445                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1446                          pdev->bus->number,
1447                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1448                 pci_dev_put(pdev);
1449         }
1450 }
1451
1452 static void sbridge_put_all_devices(void)
1453 {
1454         struct sbridge_dev *sbridge_dev, *tmp;
1455
1456         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1457                 sbridge_put_devices(sbridge_dev);
1458                 free_sbridge_dev(sbridge_dev);
1459         }
1460 }
1461
1462 static int sbridge_get_onedevice(struct pci_dev **prev,
1463                                  u8 *num_mc,
1464                                  const struct pci_id_table *table,
1465                                  const unsigned devno)
1466 {
1467         struct sbridge_dev *sbridge_dev;
1468         const struct pci_id_descr *dev_descr = &table->descr[devno];
1469         struct pci_dev *pdev = NULL;
1470         u8 bus = 0;
1471
1472         sbridge_printk(KERN_DEBUG,
1473                 "Seeking for: PCI ID %04x:%04x\n",
1474                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1475
1476         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1477                               dev_descr->dev_id, *prev);
1478
1479         if (!pdev) {
1480                 if (*prev) {
1481                         *prev = pdev;
1482                         return 0;
1483                 }
1484
1485                 if (dev_descr->optional)
1486                         return 0;
1487
1488                 /* if the HA wasn't found */
1489                 if (devno == 0)
1490                         return -ENODEV;
1491
1492                 sbridge_printk(KERN_INFO,
1493                         "Device not found: %04x:%04x\n",
1494                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1495
1496                 /* End of list, leave */
1497                 return -ENODEV;
1498         }
1499         bus = pdev->bus->number;
1500
1501         sbridge_dev = get_sbridge_dev(bus);
1502         if (!sbridge_dev) {
1503                 sbridge_dev = alloc_sbridge_dev(bus, table);
1504                 if (!sbridge_dev) {
1505                         pci_dev_put(pdev);
1506                         return -ENOMEM;
1507                 }
1508                 (*num_mc)++;
1509         }
1510
1511         if (sbridge_dev->pdev[devno]) {
1512                 sbridge_printk(KERN_ERR,
1513                         "Duplicated device for %04x:%04x\n",
1514                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1515                 pci_dev_put(pdev);
1516                 return -ENODEV;
1517         }
1518
1519         sbridge_dev->pdev[devno] = pdev;
1520
1521         /* Be sure that the device is enabled */
1522         if (unlikely(pci_enable_device(pdev) < 0)) {
1523                 sbridge_printk(KERN_ERR,
1524                         "Couldn't enable %04x:%04x\n",
1525                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1526                 return -ENODEV;
1527         }
1528
1529         edac_dbg(0, "Detected %04x:%04x\n",
1530                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1531
1532         /*
1533          * As stated on drivers/pci/search.c, the reference count for
1534          * @from is always decremented if it is not %NULL. So, as we need
1535          * to get all devices up to null, we need to do a get for the device
1536          */
1537         pci_dev_get(pdev);
1538
1539         *prev = pdev;
1540
1541         return 0;
1542 }
1543
1544 /*
1545  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1546  *                           devices we want to reference for this driver.
1547  * @num_mc: pointer to the memory controllers count, to be incremented in case
1548  *          of success.
1549  * @table: model specific table
1550  *
1551  * returns 0 in case of success or error code
1552  */
1553 static int sbridge_get_all_devices(u8 *num_mc,
1554                                    const struct pci_id_table *table)
1555 {
1556         int i, rc;
1557         struct pci_dev *pdev = NULL;
1558
1559         while (table && table->descr) {
1560                 for (i = 0; i < table->n_devs; i++) {
1561                         pdev = NULL;
1562                         do {
1563                                 rc = sbridge_get_onedevice(&pdev, num_mc,
1564                                                            table, i);
1565                                 if (rc < 0) {
1566                                         if (i == 0) {
1567                                                 i = table->n_devs;
1568                                                 break;
1569                                         }
1570                                         sbridge_put_all_devices();
1571                                         return -ENODEV;
1572                                 }
1573                         } while (pdev);
1574                 }
1575                 table++;
1576         }
1577
1578         return 0;
1579 }
1580
1581 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1582                                  struct sbridge_dev *sbridge_dev)
1583 {
1584         struct sbridge_pvt *pvt = mci->pvt_info;
1585         struct pci_dev *pdev;
1586         int i;
1587
1588         for (i = 0; i < sbridge_dev->n_devs; i++) {
1589                 pdev = sbridge_dev->pdev[i];
1590                 if (!pdev)
1591                         continue;
1592
1593                 switch (pdev->device) {
1594                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1595                         pvt->pci_sad0 = pdev;
1596                         break;
1597                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1598                         pvt->pci_sad1 = pdev;
1599                         break;
1600                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1601                         pvt->pci_br0 = pdev;
1602                         break;
1603                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1604                         pvt->pci_ha0 = pdev;
1605                         break;
1606                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1607                         pvt->pci_ta = pdev;
1608                         break;
1609                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1610                         pvt->pci_ras = pdev;
1611                         break;
1612                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1613                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1614                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1615                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1616                 {
1617                         int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1618                         pvt->pci_tad[id] = pdev;
1619                 }
1620                         break;
1621                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1622                         pvt->pci_ddrio = pdev;
1623                         break;
1624                 default:
1625                         goto error;
1626                 }
1627
1628                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1629                          pdev->vendor, pdev->device,
1630                          sbridge_dev->bus,
1631                          pdev);
1632         }
1633
1634         /* Check if everything were registered */
1635         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1636             !pvt-> pci_tad || !pvt->pci_ras  || !pvt->pci_ta)
1637                 goto enodev;
1638
1639         for (i = 0; i < NUM_CHANNELS; i++) {
1640                 if (!pvt->pci_tad[i])
1641                         goto enodev;
1642         }
1643         return 0;
1644
1645 enodev:
1646         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1647         return -ENODEV;
1648
1649 error:
1650         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1651                        PCI_VENDOR_ID_INTEL, pdev->device);
1652         return -EINVAL;
1653 }
1654
1655 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1656                                  struct sbridge_dev *sbridge_dev)
1657 {
1658         struct sbridge_pvt *pvt = mci->pvt_info;
1659         struct pci_dev *pdev, *tmp;
1660         int i;
1661         bool mode_2ha = false;
1662
1663         tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1664                              PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL);
1665         if (tmp) {
1666                 mode_2ha = true;
1667                 pci_dev_put(tmp);
1668         }
1669
1670         for (i = 0; i < sbridge_dev->n_devs; i++) {
1671                 pdev = sbridge_dev->pdev[i];
1672                 if (!pdev)
1673                         continue;
1674
1675                 switch (pdev->device) {
1676                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1677                         pvt->pci_ha0 = pdev;
1678                         break;
1679                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1680                         pvt->pci_ta = pdev;
1681                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1682                         pvt->pci_ras = pdev;
1683                         break;
1684                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1685                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1686                         /* if we have 2 HAs active, channels 2 and 3
1687                          * are in other device */
1688                         if (mode_2ha)
1689                                 break;
1690                         /* fall through */
1691                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1692                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1693                 {
1694                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1695                         pvt->pci_tad[id] = pdev;
1696                 }
1697                         break;
1698                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1699                         pvt->pci_ddrio = pdev;
1700                         break;
1701                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1702                         if (!mode_2ha)
1703                                 pvt->pci_ddrio = pdev;
1704                         break;
1705                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1706                         pvt->pci_sad0 = pdev;
1707                         break;
1708                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1709                         pvt->pci_br0 = pdev;
1710                         break;
1711                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1712                         pvt->pci_br1 = pdev;
1713                         break;
1714                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1715                         pvt->pci_ha1 = pdev;
1716                         break;
1717                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1718                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1719                 {
1720                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2;
1721
1722                         /* we shouldn't have this device if we have just one
1723                          * HA present */
1724                         WARN_ON(!mode_2ha);
1725                         pvt->pci_tad[id] = pdev;
1726                 }
1727                         break;
1728                 default:
1729                         goto error;
1730                 }
1731
1732                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1733                          sbridge_dev->bus,
1734                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1735                          pdev);
1736         }
1737
1738         /* Check if everything were registered */
1739         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1740             !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras  ||
1741             !pvt->pci_ta)
1742                 goto enodev;
1743
1744         for (i = 0; i < NUM_CHANNELS; i++) {
1745                 if (!pvt->pci_tad[i])
1746                         goto enodev;
1747         }
1748         return 0;
1749
1750 enodev:
1751         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1752         return -ENODEV;
1753
1754 error:
1755         sbridge_printk(KERN_ERR,
1756                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1757                         pdev->device);
1758         return -EINVAL;
1759 }
1760
1761 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1762                                  struct sbridge_dev *sbridge_dev)
1763 {
1764         struct sbridge_pvt *pvt = mci->pvt_info;
1765         struct pci_dev *pdev, *tmp;
1766         int i;
1767         bool mode_2ha = false;
1768
1769         tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
1770                              PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL);
1771         if (tmp) {
1772                 mode_2ha = true;
1773                 pci_dev_put(tmp);
1774         }
1775
1776         /* there's only one device per system; not tied to any bus */
1777         if (pvt->info.pci_vtd == NULL)
1778                 /* result will be checked later */
1779                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1780                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1781                                                    NULL);
1782
1783         for (i = 0; i < sbridge_dev->n_devs; i++) {
1784                 pdev = sbridge_dev->pdev[i];
1785                 if (!pdev)
1786                         continue;
1787
1788                 switch (pdev->device) {
1789                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1790                         pvt->pci_sad0 = pdev;
1791                         break;
1792                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1793                         pvt->pci_sad1 = pdev;
1794                         break;
1795                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1796                         pvt->pci_ha0 = pdev;
1797                         break;
1798                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1799                         pvt->pci_ta = pdev;
1800                         break;
1801                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1802                         pvt->pci_ras = pdev;
1803                         break;
1804                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1805                         pvt->pci_tad[0] = pdev;
1806                         break;
1807                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1808                         pvt->pci_tad[1] = pdev;
1809                         break;
1810                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1811                         if (!mode_2ha)
1812                                 pvt->pci_tad[2] = pdev;
1813                         break;
1814                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1815                         if (!mode_2ha)
1816                                 pvt->pci_tad[3] = pdev;
1817                         break;
1818                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1819                         pvt->pci_ddrio = pdev;
1820                         break;
1821                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1822                         pvt->pci_ha1 = pdev;
1823                         break;
1824                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1825                         pvt->pci_ha1_ta = pdev;
1826                         break;
1827                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1828                         if (mode_2ha)
1829                                 pvt->pci_tad[2] = pdev;
1830                         break;
1831                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1832                         if (mode_2ha)
1833                                 pvt->pci_tad[3] = pdev;
1834                         break;
1835                 default:
1836                         break;
1837                 }
1838
1839                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1840                          sbridge_dev->bus,
1841                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1842                          pdev);
1843         }
1844
1845         /* Check if everything were registered */
1846         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1847             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
1848                 goto enodev;
1849
1850         for (i = 0; i < NUM_CHANNELS; i++) {
1851                 if (!pvt->pci_tad[i])
1852                         goto enodev;
1853         }
1854         return 0;
1855
1856 enodev:
1857         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1858         return -ENODEV;
1859 }
1860
1861 /****************************************************************************
1862                         Error check routines
1863  ****************************************************************************/
1864
1865 /*
1866  * While Sandy Bridge has error count registers, SMI BIOS read values from
1867  * and resets the counters. So, they are not reliable for the OS to read
1868  * from them. So, we have no option but to just trust on whatever MCE is
1869  * telling us about the errors.
1870  */
1871 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1872                                     const struct mce *m)
1873 {
1874         struct mem_ctl_info *new_mci;
1875         struct sbridge_pvt *pvt = mci->pvt_info;
1876         enum hw_event_mc_err_type tp_event;
1877         char *type, *optype, msg[256];
1878         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1879         bool overflow = GET_BITFIELD(m->status, 62, 62);
1880         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1881         bool recoverable;
1882         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1883         u32 mscod = GET_BITFIELD(m->status, 16, 31);
1884         u32 errcode = GET_BITFIELD(m->status, 0, 15);
1885         u32 channel = GET_BITFIELD(m->status, 0, 3);
1886         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1887         long channel_mask, first_channel;
1888         u8  rank, socket;
1889         int rc, dimm;
1890         char *area_type = NULL;
1891
1892         if (pvt->info.type == IVY_BRIDGE)
1893                 recoverable = true;
1894         else
1895                 recoverable = GET_BITFIELD(m->status, 56, 56);
1896
1897         if (uncorrected_error) {
1898                 if (ripv) {
1899                         type = "FATAL";
1900                         tp_event = HW_EVENT_ERR_FATAL;
1901                 } else {
1902                         type = "NON_FATAL";
1903                         tp_event = HW_EVENT_ERR_UNCORRECTED;
1904                 }
1905         } else {
1906                 type = "CORRECTED";
1907                 tp_event = HW_EVENT_ERR_CORRECTED;
1908         }
1909
1910         /*
1911          * According with Table 15-9 of the Intel Architecture spec vol 3A,
1912          * memory errors should fit in this mask:
1913          *      000f 0000 1mmm cccc (binary)
1914          * where:
1915          *      f = Correction Report Filtering Bit. If 1, subsequent errors
1916          *          won't be shown
1917          *      mmm = error type
1918          *      cccc = channel
1919          * If the mask doesn't match, report an error to the parsing logic
1920          */
1921         if (! ((errcode & 0xef80) == 0x80)) {
1922                 optype = "Can't parse: it is not a mem";
1923         } else {
1924                 switch (optypenum) {
1925                 case 0:
1926                         optype = "generic undef request error";
1927                         break;
1928                 case 1:
1929                         optype = "memory read error";
1930                         break;
1931                 case 2:
1932                         optype = "memory write error";
1933                         break;
1934                 case 3:
1935                         optype = "addr/cmd error";
1936                         break;
1937                 case 4:
1938                         optype = "memory scrubbing error";
1939                         break;
1940                 default:
1941                         optype = "reserved";
1942                         break;
1943                 }
1944         }
1945
1946         /* Only decode errors with an valid address (ADDRV) */
1947         if (!GET_BITFIELD(m->status, 58, 58))
1948                 return;
1949
1950         rc = get_memory_error_data(mci, m->addr, &socket,
1951                                    &channel_mask, &rank, &area_type, msg);
1952         if (rc < 0)
1953                 goto err_parsing;
1954         new_mci = get_mci_for_node_id(socket);
1955         if (!new_mci) {
1956                 strcpy(msg, "Error: socket got corrupted!");
1957                 goto err_parsing;
1958         }
1959         mci = new_mci;
1960         pvt = mci->pvt_info;
1961
1962         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1963
1964         if (rank < 4)
1965                 dimm = 0;
1966         else if (rank < 8)
1967                 dimm = 1;
1968         else
1969                 dimm = 2;
1970
1971
1972         /*
1973          * FIXME: On some memory configurations (mirror, lockstep), the
1974          * Memory Controller can't point the error to a single DIMM. The
1975          * EDAC core should be handling the channel mask, in order to point
1976          * to the group of dimm's where the error may be happening.
1977          */
1978         if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
1979                 channel = first_channel;
1980
1981         snprintf(msg, sizeof(msg),
1982                  "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
1983                  overflow ? " OVERFLOW" : "",
1984                  (uncorrected_error && recoverable) ? " recoverable" : "",
1985                  area_type,
1986                  mscod, errcode,
1987                  socket,
1988                  channel_mask,
1989                  rank);
1990
1991         edac_dbg(0, "%s\n", msg);
1992
1993         /* FIXME: need support for channel mask */
1994
1995         if (channel == CHANNEL_UNSPECIFIED)
1996                 channel = -1;
1997
1998         /* Call the helper to output message */
1999         edac_mc_handle_error(tp_event, mci, core_err_cnt,
2000                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2001                              channel, dimm, -1,
2002                              optype, msg);
2003         return;
2004 err_parsing:
2005         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
2006                              -1, -1, -1,
2007                              msg, "");
2008
2009 }
2010
2011 /*
2012  *      sbridge_check_error     Retrieve and process errors reported by the
2013  *                              hardware. Called by the Core module.
2014  */
2015 static void sbridge_check_error(struct mem_ctl_info *mci)
2016 {
2017         struct sbridge_pvt *pvt = mci->pvt_info;
2018         int i;
2019         unsigned count = 0;
2020         struct mce *m;
2021
2022         /*
2023          * MCE first step: Copy all mce errors into a temporary buffer
2024          * We use a double buffering here, to reduce the risk of
2025          * loosing an error.
2026          */
2027         smp_rmb();
2028         count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2029                 % MCE_LOG_LEN;
2030         if (!count)
2031                 return;
2032
2033         m = pvt->mce_outentry;
2034         if (pvt->mce_in + count > MCE_LOG_LEN) {
2035                 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2036
2037                 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2038                 smp_wmb();
2039                 pvt->mce_in = 0;
2040                 count -= l;
2041                 m += l;
2042         }
2043         memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2044         smp_wmb();
2045         pvt->mce_in += count;
2046
2047         smp_rmb();
2048         if (pvt->mce_overrun) {
2049                 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2050                               pvt->mce_overrun);
2051                 smp_wmb();
2052                 pvt->mce_overrun = 0;
2053         }
2054
2055         /*
2056          * MCE second step: parse errors and display
2057          */
2058         for (i = 0; i < count; i++)
2059                 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2060 }
2061
2062 /*
2063  * sbridge_mce_check_error      Replicates mcelog routine to get errors
2064  *                              This routine simply queues mcelog errors, and
2065  *                              return. The error itself should be handled later
2066  *                              by sbridge_check_error.
2067  * WARNING: As this routine should be called at NMI time, extra care should
2068  * be taken to avoid deadlocks, and to be as fast as possible.
2069  */
2070 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2071                                    void *data)
2072 {
2073         struct mce *mce = (struct mce *)data;
2074         struct mem_ctl_info *mci;
2075         struct sbridge_pvt *pvt;
2076         char *type;
2077
2078         if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2079                 return NOTIFY_DONE;
2080
2081         mci = get_mci_for_node_id(mce->socketid);
2082         if (!mci)
2083                 return NOTIFY_BAD;
2084         pvt = mci->pvt_info;
2085
2086         /*
2087          * Just let mcelog handle it if the error is
2088          * outside the memory controller. A memory error
2089          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2090          * bit 12 has an special meaning.
2091          */
2092         if ((mce->status & 0xefff) >> 7 != 1)
2093                 return NOTIFY_DONE;
2094
2095         if (mce->mcgstatus & MCG_STATUS_MCIP)
2096                 type = "Exception";
2097         else
2098                 type = "Event";
2099
2100         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2101
2102         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2103                           "Bank %d: %016Lx\n", mce->extcpu, type,
2104                           mce->mcgstatus, mce->bank, mce->status);
2105         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2106         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2107         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2108
2109         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2110                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2111                           mce->time, mce->socketid, mce->apicid);
2112
2113         smp_rmb();
2114         if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2115                 smp_wmb();
2116                 pvt->mce_overrun++;
2117                 return NOTIFY_DONE;
2118         }
2119
2120         /* Copy memory error at the ringbuffer */
2121         memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2122         smp_wmb();
2123         pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2124
2125         /* Handle fatal errors immediately */
2126         if (mce->mcgstatus & 1)
2127                 sbridge_check_error(mci);
2128
2129         /* Advice mcelog that the error were handled */
2130         return NOTIFY_STOP;
2131 }
2132
2133 static struct notifier_block sbridge_mce_dec = {
2134         .notifier_call      = sbridge_mce_check_error,
2135 };
2136
2137 /****************************************************************************
2138                         EDAC register/unregister logic
2139  ****************************************************************************/
2140
2141 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2142 {
2143         struct mem_ctl_info *mci = sbridge_dev->mci;
2144         struct sbridge_pvt *pvt;
2145
2146         if (unlikely(!mci || !mci->pvt_info)) {
2147                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2148
2149                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2150                 return;
2151         }
2152
2153         pvt = mci->pvt_info;
2154
2155         edac_dbg(0, "MC: mci = %p, dev = %p\n",
2156                  mci, &sbridge_dev->pdev[0]->dev);
2157
2158         /* Remove MC sysfs nodes */
2159         edac_mc_del_mc(mci->pdev);
2160
2161         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2162         kfree(mci->ctl_name);
2163         edac_mc_free(mci);
2164         sbridge_dev->mci = NULL;
2165 }
2166
2167 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2168 {
2169         struct mem_ctl_info *mci;
2170         struct edac_mc_layer layers[2];
2171         struct sbridge_pvt *pvt;
2172         struct pci_dev *pdev = sbridge_dev->pdev[0];
2173         int rc;
2174
2175         /* Check the number of active and not disabled channels */
2176         rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2177         if (unlikely(rc < 0))
2178                 return rc;
2179
2180         /* allocate a new MC control structure */
2181         layers[0].type = EDAC_MC_LAYER_CHANNEL;
2182         layers[0].size = NUM_CHANNELS;
2183         layers[0].is_virt_csrow = false;
2184         layers[1].type = EDAC_MC_LAYER_SLOT;
2185         layers[1].size = MAX_DIMMS;
2186         layers[1].is_virt_csrow = true;
2187         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2188                             sizeof(*pvt));
2189
2190         if (unlikely(!mci))
2191                 return -ENOMEM;
2192
2193         edac_dbg(0, "MC: mci = %p, dev = %p\n",
2194                  mci, &pdev->dev);
2195
2196         pvt = mci->pvt_info;
2197         memset(pvt, 0, sizeof(*pvt));
2198
2199         /* Associate sbridge_dev and mci for future usage */
2200         pvt->sbridge_dev = sbridge_dev;
2201         sbridge_dev->mci = mci;
2202
2203         mci->mtype_cap = MEM_FLAG_DDR3;
2204         mci->edac_ctl_cap = EDAC_FLAG_NONE;
2205         mci->edac_cap = EDAC_FLAG_NONE;
2206         mci->mod_name = "sbridge_edac.c";
2207         mci->mod_ver = SBRIDGE_REVISION;
2208         mci->dev_name = pci_name(pdev);
2209         mci->ctl_page_to_phys = NULL;
2210
2211         /* Set the function pointer to an actual operation function */
2212         mci->edac_check = sbridge_check_error;
2213
2214         pvt->info.type = type;
2215         switch (type) {
2216         case IVY_BRIDGE:
2217                 pvt->info.rankcfgr = IB_RANK_CFG_A;
2218                 pvt->info.get_tolm = ibridge_get_tolm;
2219                 pvt->info.get_tohm = ibridge_get_tohm;
2220                 pvt->info.dram_rule = ibridge_dram_rule;
2221                 pvt->info.get_memory_type = get_memory_type;
2222                 pvt->info.get_node_id = get_node_id;
2223                 pvt->info.rir_limit = rir_limit;
2224                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2225                 pvt->info.interleave_list = ibridge_interleave_list;
2226                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2227                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2228                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2229
2230                 /* Store pci devices at mci for faster access */
2231                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2232                 if (unlikely(rc < 0))
2233                         goto fail0;
2234                 break;
2235         case SANDY_BRIDGE:
2236                 pvt->info.rankcfgr = SB_RANK_CFG_A;
2237                 pvt->info.get_tolm = sbridge_get_tolm;
2238                 pvt->info.get_tohm = sbridge_get_tohm;
2239                 pvt->info.dram_rule = sbridge_dram_rule;
2240                 pvt->info.get_memory_type = get_memory_type;
2241                 pvt->info.get_node_id = get_node_id;
2242                 pvt->info.rir_limit = rir_limit;
2243                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2244                 pvt->info.interleave_list = sbridge_interleave_list;
2245                 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2246                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2247                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2248
2249                 /* Store pci devices at mci for faster access */
2250                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2251                 if (unlikely(rc < 0))
2252                         goto fail0;
2253                 break;
2254         case HASWELL:
2255                 /* rankcfgr isn't used */
2256                 pvt->info.get_tolm = haswell_get_tolm;
2257                 pvt->info.get_tohm = haswell_get_tohm;
2258                 pvt->info.dram_rule = ibridge_dram_rule;
2259                 pvt->info.get_memory_type = haswell_get_memory_type;
2260                 pvt->info.get_node_id = haswell_get_node_id;
2261                 pvt->info.rir_limit = haswell_rir_limit;
2262                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2263                 pvt->info.interleave_list = ibridge_interleave_list;
2264                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2265                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2266                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2267
2268                 /* Store pci devices at mci for faster access */
2269                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2270                 if (unlikely(rc < 0))
2271                         goto fail0;
2272                 break;
2273         }
2274
2275         /* Get dimm basic config and the memory layout */
2276         get_dimm_config(mci);
2277         get_memory_layout(mci);
2278
2279         /* record ptr to the generic device */
2280         mci->pdev = &pdev->dev;
2281
2282         /* add this new MC control structure to EDAC's list of MCs */
2283         if (unlikely(edac_mc_add_mc(mci))) {
2284                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2285                 rc = -EINVAL;
2286                 goto fail0;
2287         }
2288
2289         return 0;
2290
2291 fail0:
2292         kfree(mci->ctl_name);
2293         edac_mc_free(mci);
2294         sbridge_dev->mci = NULL;
2295         return rc;
2296 }
2297
2298 /*
2299  *      sbridge_probe   Probe for ONE instance of device to see if it is
2300  *                      present.
2301  *      return:
2302  *              0 for FOUND a device
2303  *              < 0 for error code
2304  */
2305
2306 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2307 {
2308         int rc = -ENODEV;
2309         u8 mc, num_mc = 0;
2310         struct sbridge_dev *sbridge_dev;
2311         enum type type = SANDY_BRIDGE;
2312
2313         /* get the pci devices we want to reserve for our use */
2314         mutex_lock(&sbridge_edac_lock);
2315
2316         /*
2317          * All memory controllers are allocated at the first pass.
2318          */
2319         if (unlikely(probed >= 1)) {
2320                 mutex_unlock(&sbridge_edac_lock);
2321                 return -ENODEV;
2322         }
2323         probed++;
2324
2325         switch (pdev->device) {
2326         case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2327                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2328                 type = IVY_BRIDGE;
2329                 break;
2330         case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2331                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2332                 type = SANDY_BRIDGE;
2333                 break;
2334         case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2335                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2336                 type = HASWELL;
2337                 break;
2338         }
2339         if (unlikely(rc < 0))
2340                 goto fail0;
2341         mc = 0;
2342
2343         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2344                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2345                          mc, mc + 1, num_mc);
2346
2347                 sbridge_dev->mc = mc++;
2348                 rc = sbridge_register_mci(sbridge_dev, type);
2349                 if (unlikely(rc < 0))
2350                         goto fail1;
2351         }
2352
2353         sbridge_printk(KERN_INFO, "Driver loaded.\n");
2354
2355         mutex_unlock(&sbridge_edac_lock);
2356         return 0;
2357
2358 fail1:
2359         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2360                 sbridge_unregister_mci(sbridge_dev);
2361
2362         sbridge_put_all_devices();
2363 fail0:
2364         mutex_unlock(&sbridge_edac_lock);
2365         return rc;
2366 }
2367
2368 /*
2369  *      sbridge_remove  destructor for one instance of device
2370  *
2371  */
2372 static void sbridge_remove(struct pci_dev *pdev)
2373 {
2374         struct sbridge_dev *sbridge_dev;
2375
2376         edac_dbg(0, "\n");
2377
2378         /*
2379          * we have a trouble here: pdev value for removal will be wrong, since
2380          * it will point to the X58 register used to detect that the machine
2381          * is a Nehalem or upper design. However, due to the way several PCI
2382          * devices are grouped together to provide MC functionality, we need
2383          * to use a different method for releasing the devices
2384          */
2385
2386         mutex_lock(&sbridge_edac_lock);
2387
2388         if (unlikely(!probed)) {
2389                 mutex_unlock(&sbridge_edac_lock);
2390                 return;
2391         }
2392
2393         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2394                 sbridge_unregister_mci(sbridge_dev);
2395
2396         /* Release PCI resources */
2397         sbridge_put_all_devices();
2398
2399         probed--;
2400
2401         mutex_unlock(&sbridge_edac_lock);
2402 }
2403
2404 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2405
2406 /*
2407  *      sbridge_driver  pci_driver structure for this module
2408  *
2409  */
2410 static struct pci_driver sbridge_driver = {
2411         .name     = "sbridge_edac",
2412         .probe    = sbridge_probe,
2413         .remove   = sbridge_remove,
2414         .id_table = sbridge_pci_tbl,
2415 };
2416
2417 /*
2418  *      sbridge_init            Module entry function
2419  *                      Try to initialize this module for its devices
2420  */
2421 static int __init sbridge_init(void)
2422 {
2423         int pci_rc;
2424
2425         edac_dbg(2, "\n");
2426
2427         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2428         opstate_init();
2429
2430         pci_rc = pci_register_driver(&sbridge_driver);
2431         if (pci_rc >= 0) {
2432                 mce_register_decode_chain(&sbridge_mce_dec);
2433                 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2434                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2435                 return 0;
2436         }
2437
2438         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2439                       pci_rc);
2440
2441         return pci_rc;
2442 }
2443
2444 /*
2445  *      sbridge_exit()  Module exit function
2446  *                      Unregister the driver
2447  */
2448 static void __exit sbridge_exit(void)
2449 {
2450         edac_dbg(2, "\n");
2451         pci_unregister_driver(&sbridge_driver);
2452         mce_unregister_decode_chain(&sbridge_mce_dec);
2453 }
2454
2455 module_init(sbridge_init);
2456 module_exit(sbridge_exit);
2457
2458 module_param(edac_op_state, int, 0444);
2459 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2460
2461 MODULE_LICENSE("GPL");
2462 MODULE_AUTHOR("Mauro Carvalho Chehab");
2463 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2464 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
2465                    SBRIDGE_REVISION);