1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
27 #include "edac_core.h"
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
35 * Alter this version for the module when modifications are made
37 #define SBRIDGE_REVISION " Ver: 1.1.1 "
38 #define EDAC_MOD_STR "sbridge_edac"
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
56 static const u32 sbridge_dram_rule[] = {
57 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
61 static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
68 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
69 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
70 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
71 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
72 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
74 static char *get_dram_attr(u32 reg)
76 switch(DRAM_ATTR(reg)) {
88 static const u32 sbridge_interleave_list[] = {
89 0x84, 0x8c, 0x94, 0x9c, 0xa4,
90 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
93 static const u32 ibridge_interleave_list[] = {
94 0x64, 0x6c, 0x74, 0x7c, 0x84,
95 0x8c, 0x94, 0x9c, 0xa4, 0xac,
96 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
97 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
100 struct interleave_pkg {
105 static const struct interleave_pkg sbridge_interleave_pkg[] = {
116 static const struct interleave_pkg ibridge_interleave_pkg[] = {
127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
130 return GET_BITFIELD(reg, table[interleave].start,
131 table[interleave].end);
134 /* Devices 12 Function 7 */
138 #define HASWELL_TOLM 0xd0
139 #define HASWELL_TOHM_0 0xd4
140 #define HASWELL_TOHM_1 0xd8
142 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
143 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
145 /* Device 13 Function 6 */
147 #define SAD_TARGET 0xf0
149 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
151 #define SAD_CONTROL 0xf4
153 /* Device 14 function 0 */
155 static const u32 tad_dram_rule[] = {
156 0x40, 0x44, 0x48, 0x4c,
157 0x50, 0x54, 0x58, 0x5c,
158 0x60, 0x64, 0x68, 0x6c,
160 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
162 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
163 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
164 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
165 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
166 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
167 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
168 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
170 /* Device 15, function 0 */
174 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
175 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
176 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
178 /* Device 15, function 1 */
180 #define RASENABLES 0xac
181 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
183 /* Device 15, functions 2-5 */
185 static const int mtr_regs[] = {
189 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
190 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
191 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
192 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
193 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
195 static const u32 tad_ch_nilv_offset[] = {
196 0x90, 0x94, 0x98, 0x9c,
197 0xa0, 0xa4, 0xa8, 0xac,
198 0xb0, 0xb4, 0xb8, 0xbc,
200 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
201 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
203 static const u32 rir_way_limit[] = {
204 0x108, 0x10c, 0x110, 0x114, 0x118,
206 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
208 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
209 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
211 #define MAX_RIR_WAY 8
213 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
214 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
215 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
216 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
217 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
218 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
221 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
222 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
224 /* Device 16, functions 2-7 */
227 * FIXME: Implement the error count reads directly
230 static const u32 correrrcnt[] = {
231 0x104, 0x108, 0x10c, 0x110,
234 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
235 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
236 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
237 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
239 static const u32 correrrthrsld[] = {
240 0x11c, 0x120, 0x124, 0x128,
243 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
244 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
247 /* Device 17, function 0 */
249 #define SB_RANK_CFG_A 0x0328
251 #define IB_RANK_CFG_A 0x0320
257 #define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */
258 #define MAX_DIMMS 3 /* Max DIMMS per channel */
259 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
269 struct sbridge_info {
273 u64 (*get_tolm)(struct sbridge_pvt *pvt);
274 u64 (*get_tohm)(struct sbridge_pvt *pvt);
275 u64 (*rir_limit)(u32 reg);
276 const u32 *dram_rule;
277 const u32 *interleave_list;
278 const struct interleave_pkg *interleave_pkg;
281 u8 (*get_node_id)(struct sbridge_pvt *pvt);
282 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
283 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
284 struct pci_dev *pci_vtd;
287 struct sbridge_channel {
292 struct pci_id_descr {
297 struct pci_id_table {
298 const struct pci_id_descr *descr;
303 struct list_head list;
305 u8 node_id, source_id;
306 struct pci_dev **pdev;
308 struct mem_ctl_info *mci;
312 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
313 struct pci_dev *pci_sad0, *pci_sad1;
314 struct pci_dev *pci_ha0, *pci_ha1;
315 struct pci_dev *pci_br0, *pci_br1;
316 struct pci_dev *pci_ha1_ta;
317 struct pci_dev *pci_tad[NUM_CHANNELS];
319 struct sbridge_dev *sbridge_dev;
321 struct sbridge_info info;
322 struct sbridge_channel channel[NUM_CHANNELS];
324 /* Memory type detection */
325 bool is_mirrored, is_lockstep, is_close_pg;
327 /* Fifo double buffers */
328 struct mce mce_entry[MCE_LOG_LEN];
329 struct mce mce_outentry[MCE_LOG_LEN];
331 /* Fifo in/out counters */
332 unsigned mce_in, mce_out;
334 /* Count indicator to show errors not got */
335 unsigned mce_overrun;
337 /* Memory description */
341 #define PCI_DESCR(device_id, opt) \
342 .dev_id = (device_id), \
345 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
346 /* Processor Home Agent */
347 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
349 /* Memory controller */
350 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
351 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
352 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
353 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
354 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
355 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
356 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
358 /* System Address Decoder */
359 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
360 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
362 /* Broadcast Registers */
363 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
366 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
367 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
368 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
369 {0,} /* 0 terminated list. */
372 /* This changes depending if 1HA or 2HA:
374 * 0x0eb8 (17.0) is DDRIO0
376 * 0x0ebc (17.4) is DDRIO0
378 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
379 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
382 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
383 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
384 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
385 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
386 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
387 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
388 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
389 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
390 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
391 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
392 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
393 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
394 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
395 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
396 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
397 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
398 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
400 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
401 /* Processor Home Agent */
402 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
404 /* Memory controller */
405 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
406 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
407 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
408 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
410 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
412 /* System Address Decoder */
413 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
415 /* Broadcast Registers */
416 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
417 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
419 /* Optional, mode 2HA */
420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
422 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
425 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
426 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
427 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) },
428 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) },
430 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
431 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
434 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
435 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
436 {0,} /* 0 terminated list. */
439 /* Haswell support */
442 * - 3 DDR3 channels, 2 DPC per channel
445 * - 4 DDR4 channels, 3 DPC per channel
448 * - 4 DDR4 channels, 3 DPC per channel
451 * - each IMC interfaces with a SMI 2 channel
452 * - each SMI channel interfaces with a scalable memory buffer
453 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
455 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
456 #define HASWELL_HASYSDEFEATURE2 0x84
457 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
458 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
459 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
460 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
461 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
462 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
463 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
464 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
465 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
466 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
467 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
468 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
469 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
470 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
471 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
472 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
473 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
474 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
475 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
476 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
477 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
478 static const struct pci_id_descr pci_dev_descr_haswell[] = {
479 /* first item must be the HA */
480 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
487 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) },
496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) },
497 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) },
499 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
500 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
501 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
502 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
503 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
504 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
507 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
508 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
509 {0,} /* 0 terminated list. */
517 * - 2 DDR3 channels, 2 DPC per channel
520 * - 4 DDR4 channels, 3 DPC per channel
523 * - 4 DDR4 channels, 3 DPC per channel
526 * - each IMC interfaces with a SMI 2 channel
527 * - each SMI channel interfaces with a scalable memory buffer
528 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
530 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
531 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
532 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
533 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
534 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
535 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
536 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
537 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
538 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
539 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
540 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
541 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
542 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
543 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
544 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
545 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
546 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
547 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
549 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
550 /* first item must be the HA */
551 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
553 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
556 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) },
558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
562 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) },
563 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) },
565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
567 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) },
568 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) },
569 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) },
570 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) },
571 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) },
572 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) },
575 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
576 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
577 {0,} /* 0 terminated list. */
581 * pci_device_id table for which devices we are looking for
583 static const struct pci_device_id sbridge_pci_tbl[] = {
584 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
585 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
586 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
587 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
588 {0,} /* 0 terminated list. */
592 /****************************************************************************
593 Ancillary status routines
594 ****************************************************************************/
596 static inline int numrank(enum type type, u32 mtr)
598 int ranks = (1 << RANK_CNT_BITS(mtr));
601 if (type == HASWELL || type == BROADWELL)
605 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
606 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
613 static inline int numrow(u32 mtr)
615 int rows = (RANK_WIDTH_BITS(mtr) + 12);
617 if (rows < 13 || rows > 18) {
618 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
619 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
626 static inline int numcol(u32 mtr)
628 int cols = (COL_WIDTH_BITS(mtr) + 10);
631 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
632 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
639 static struct sbridge_dev *get_sbridge_dev(u8 bus)
641 struct sbridge_dev *sbridge_dev;
643 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
644 if (sbridge_dev->bus == bus)
651 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
652 const struct pci_id_table *table)
654 struct sbridge_dev *sbridge_dev;
656 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
660 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
662 if (!sbridge_dev->pdev) {
667 sbridge_dev->bus = bus;
668 sbridge_dev->n_devs = table->n_devs;
669 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
674 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
676 list_del(&sbridge_dev->list);
677 kfree(sbridge_dev->pdev);
681 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
685 /* Address range is 32:28 */
686 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
687 return GET_TOLM(reg);
690 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
694 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
695 return GET_TOHM(reg);
698 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
702 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
704 return GET_TOLM(reg);
707 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
711 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
713 return GET_TOHM(reg);
716 static u64 rir_limit(u32 reg)
718 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
721 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
726 if (pvt->pci_ddrio) {
727 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
729 if (GET_BITFIELD(reg, 11, 11))
730 /* FIXME: Can also be LRDIMM */
740 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
743 bool registered = false;
744 enum mem_type mtype = MEM_UNKNOWN;
749 pci_read_config_dword(pvt->pci_ddrio,
750 HASWELL_DDRCRCLKCONTROLS, ®);
752 if (GET_BITFIELD(reg, 16, 16))
755 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
756 if (GET_BITFIELD(reg, 14, 14)) {
772 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
774 /* there's no way to figure out */
778 static enum dev_type __ibridge_get_width(u32 mtr)
800 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
803 * ddr3_width on the documentation but also valid for DDR4 on
806 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
809 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
811 /* ddr3_width on the documentation but also valid for DDR4 */
812 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
815 static u8 get_node_id(struct sbridge_pvt *pvt)
818 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
819 return GET_BITFIELD(reg, 0, 2);
822 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
826 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
827 return GET_BITFIELD(reg, 0, 3);
830 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
834 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
835 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
838 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
843 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
844 rc = GET_BITFIELD(reg, 26, 31);
845 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
846 rc = ((reg << 6) | rc) << 26;
848 return rc | 0x1ffffff;
851 static u64 haswell_rir_limit(u32 reg)
853 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
856 static inline u8 sad_pkg_socket(u8 pkg)
858 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
859 return ((pkg >> 3) << 2) | (pkg & 0x3);
862 static inline u8 sad_pkg_ha(u8 pkg)
864 return (pkg >> 2) & 0x1;
867 /****************************************************************************
868 Memory check routines
869 ****************************************************************************/
870 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
872 struct pci_dev *pdev = NULL;
875 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
876 if (pdev && pdev->bus->number == bus)
884 * check_if_ecc_is_active() - Checks if ECC is active
886 * @type: Memory controller type
887 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
890 static int check_if_ecc_is_active(const u8 bus, enum type type)
892 struct pci_dev *pdev = NULL;
897 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
900 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
903 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
906 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
912 pdev = get_pdev_same_bus(bus, id);
914 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
915 "%04x:%04x! on bus %02d\n",
916 PCI_VENDOR_ID_INTEL, id, bus);
920 pci_read_config_dword(pdev, MCMTR, &mcmtr);
921 if (!IS_ECC_ENABLED(mcmtr)) {
922 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
928 static int get_dimm_config(struct mem_ctl_info *mci)
930 struct sbridge_pvt *pvt = mci->pvt_info;
931 struct dimm_info *dimm;
932 unsigned i, j, banks, ranks, rows, cols, npages;
938 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
939 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
941 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
943 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
945 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
946 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
947 pvt->sbridge_dev->mc,
948 pvt->sbridge_dev->node_id,
949 pvt->sbridge_dev->source_id);
951 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
952 if (IS_MIRROR_ENABLED(reg)) {
953 edac_dbg(0, "Memory mirror is enabled\n");
954 pvt->is_mirrored = true;
956 edac_dbg(0, "Memory mirror is disabled\n");
957 pvt->is_mirrored = false;
960 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
961 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
962 edac_dbg(0, "Lockstep is enabled\n");
963 mode = EDAC_S8ECD8ED;
964 pvt->is_lockstep = true;
966 edac_dbg(0, "Lockstep is disabled\n");
967 mode = EDAC_S4ECD4ED;
968 pvt->is_lockstep = false;
970 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
971 edac_dbg(0, "address map is on closed page mode\n");
972 pvt->is_close_pg = true;
974 edac_dbg(0, "address map is on open page mode\n");
975 pvt->is_close_pg = false;
978 mtype = pvt->info.get_memory_type(pvt);
979 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
980 edac_dbg(0, "Memory is registered\n");
981 else if (mtype == MEM_UNKNOWN)
982 edac_dbg(0, "Cannot determine memory type\n");
984 edac_dbg(0, "Memory is unregistered\n");
986 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
991 for (i = 0; i < NUM_CHANNELS; i++) {
994 if (!pvt->pci_tad[i])
996 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
997 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
999 pci_read_config_dword(pvt->pci_tad[i],
1001 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
1002 if (IS_DIMM_PRESENT(mtr)) {
1003 pvt->channel[i].dimms++;
1005 ranks = numrank(pvt->info.type, mtr);
1009 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1010 npages = MiB_TO_PAGES(size);
1012 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1013 pvt->sbridge_dev->mc, i/4, i%4, j,
1015 banks, ranks, rows, cols);
1017 dimm->nr_pages = npages;
1019 dimm->dtype = pvt->info.get_width(pvt, mtr);
1020 dimm->mtype = mtype;
1021 dimm->edac_mode = mode;
1022 snprintf(dimm->label, sizeof(dimm->label),
1023 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1024 pvt->sbridge_dev->source_id, i/4, i%4, j);
1032 static void get_memory_layout(const struct mem_ctl_info *mci)
1034 struct sbridge_pvt *pvt = mci->pvt_info;
1035 int i, j, k, n_sads, n_tads, sad_interl;
1043 * Step 1) Get TOLM/TOHM ranges
1046 pvt->tolm = pvt->info.get_tolm(pvt);
1047 tmp_mb = (1 + pvt->tolm) >> 20;
1049 gb = div_u64_rem(tmp_mb, 1024, &mb);
1050 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1051 gb, (mb*1000)/1024, (u64)pvt->tolm);
1053 /* Address range is already 45:25 */
1054 pvt->tohm = pvt->info.get_tohm(pvt);
1055 tmp_mb = (1 + pvt->tohm) >> 20;
1057 gb = div_u64_rem(tmp_mb, 1024, &mb);
1058 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1059 gb, (mb*1000)/1024, (u64)pvt->tohm);
1062 * Step 2) Get SAD range and SAD Interleave list
1063 * TAD registers contain the interleave wayness. However, it
1064 * seems simpler to just discover it indirectly, with the
1068 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1069 /* SAD_LIMIT Address range is 45:26 */
1070 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1072 limit = SAD_LIMIT(reg);
1074 if (!DRAM_RULE_ENABLE(reg))
1080 tmp_mb = (limit + 1) >> 20;
1081 gb = div_u64_rem(tmp_mb, 1024, &mb);
1082 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1086 ((u64)tmp_mb) << 20L,
1087 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
1091 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1093 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1094 for (j = 0; j < 8; j++) {
1095 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1096 if (j > 0 && sad_interl == pkg)
1099 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1105 * Step 3) Get TAD range
1108 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1109 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1111 limit = TAD_LIMIT(reg);
1114 tmp_mb = (limit + 1) >> 20;
1116 gb = div_u64_rem(tmp_mb, 1024, &mb);
1117 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1118 n_tads, gb, (mb*1000)/1024,
1119 ((u64)tmp_mb) << 20L,
1120 (u32)(1 << TAD_SOCK(reg)),
1121 (u32)TAD_CH(reg) + 1,
1131 * Step 4) Get TAD offsets, per each channel
1133 for (i = 0; i < NUM_CHANNELS; i++) {
1134 if (!pvt->channel[i].dimms)
1136 for (j = 0; j < n_tads; j++) {
1137 pci_read_config_dword(pvt->pci_tad[i],
1138 tad_ch_nilv_offset[j],
1140 tmp_mb = TAD_OFFSET(reg) >> 20;
1141 gb = div_u64_rem(tmp_mb, 1024, &mb);
1142 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1145 ((u64)tmp_mb) << 20L,
1151 * Step 6) Get RIR Wayness/Limit, per each channel
1153 for (i = 0; i < NUM_CHANNELS; i++) {
1154 if (!pvt->channel[i].dimms)
1156 for (j = 0; j < MAX_RIR_RANGES; j++) {
1157 pci_read_config_dword(pvt->pci_tad[i],
1161 if (!IS_RIR_VALID(reg))
1164 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1165 rir_way = 1 << RIR_WAY(reg);
1166 gb = div_u64_rem(tmp_mb, 1024, &mb);
1167 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1170 ((u64)tmp_mb) << 20L,
1174 for (k = 0; k < rir_way; k++) {
1175 pci_read_config_dword(pvt->pci_tad[i],
1178 tmp_mb = RIR_OFFSET(reg) << 6;
1180 gb = div_u64_rem(tmp_mb, 1024, &mb);
1181 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1184 ((u64)tmp_mb) << 20L,
1185 (u32)RIR_RNK_TGT(reg),
1192 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1194 struct sbridge_dev *sbridge_dev;
1196 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1197 if (sbridge_dev->node_id == node_id)
1198 return sbridge_dev->mci;
1203 static int get_memory_error_data(struct mem_ctl_info *mci,
1208 char **area_type, char *msg)
1210 struct mem_ctl_info *new_mci;
1211 struct sbridge_pvt *pvt = mci->pvt_info;
1212 struct pci_dev *pci_ha;
1213 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1214 int sad_interl, idx, base_ch;
1215 int interleave_mode, shiftup = 0;
1216 unsigned sad_interleave[pvt->info.max_interleave];
1218 u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1222 u64 ch_addr, offset, limit = 0, prv = 0;
1226 * Step 0) Check if the address is at special memory ranges
1227 * The check bellow is probably enough to fill all cases where
1228 * the error is not inside a memory, except for the legacy
1229 * range (e. g. VGA addresses). It is unlikely, however, that the
1230 * memory controller would generate an error on that range.
1232 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1233 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1236 if (addr >= (u64)pvt->tohm) {
1237 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1242 * Step 1) Get socket
1244 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1245 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1248 if (!DRAM_RULE_ENABLE(reg))
1251 limit = SAD_LIMIT(reg);
1253 sprintf(msg, "Can't discover the memory socket");
1260 if (n_sads == pvt->info.max_sad) {
1261 sprintf(msg, "Can't discover the memory socket");
1265 *area_type = get_dram_attr(dram_rule);
1266 interleave_mode = INTERLEAVE_MODE(dram_rule);
1268 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1271 if (pvt->info.type == SANDY_BRIDGE) {
1272 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1273 for (sad_way = 0; sad_way < 8; sad_way++) {
1274 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1275 if (sad_way > 0 && sad_interl == pkg)
1277 sad_interleave[sad_way] = pkg;
1278 edac_dbg(0, "SAD interleave #%d: %d\n",
1279 sad_way, sad_interleave[sad_way]);
1281 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1282 pvt->sbridge_dev->mc,
1287 !interleave_mode ? "" : "XOR[18:16]");
1288 if (interleave_mode)
1289 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1291 idx = (addr >> 6) & 7;
1305 sprintf(msg, "Can't discover socket interleave");
1308 *socket = sad_interleave[idx];
1309 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1310 idx, sad_way, *socket);
1311 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1312 int bits, a7mode = A7MODE(dram_rule);
1315 /* A7 mode swaps P9 with P6 */
1316 bits = GET_BITFIELD(addr, 7, 8) << 1;
1317 bits |= GET_BITFIELD(addr, 9, 9);
1319 bits = GET_BITFIELD(addr, 6, 8);
1321 if (interleave_mode == 0) {
1322 /* interleave mode will XOR {8,7,6} with {18,17,16} */
1323 idx = GET_BITFIELD(addr, 16, 18);
1328 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1329 *socket = sad_pkg_socket(pkg);
1330 sad_ha = sad_pkg_ha(pkg);
1335 /* MCChanShiftUpEnable */
1336 pci_read_config_dword(pvt->pci_ha0,
1337 HASWELL_HASYSDEFEATURE2, ®);
1338 shiftup = GET_BITFIELD(reg, 22, 22);
1341 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1342 idx, *socket, sad_ha, shiftup);
1344 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1345 idx = (addr >> 6) & 7;
1346 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1347 *socket = sad_pkg_socket(pkg);
1348 sad_ha = sad_pkg_ha(pkg);
1351 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1352 idx, *socket, sad_ha);
1358 * Move to the proper node structure, in order to access the
1359 * right PCI registers
1361 new_mci = get_mci_for_node_id(*socket);
1363 sprintf(msg, "Struct for socket #%u wasn't initialized",
1368 pvt = mci->pvt_info;
1371 * Step 2) Get memory channel
1374 if (pvt->info.type == SANDY_BRIDGE)
1375 pci_ha = pvt->pci_ha0;
1378 pci_ha = pvt->pci_ha1;
1380 pci_ha = pvt->pci_ha0;
1382 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1383 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
1384 limit = TAD_LIMIT(reg);
1386 sprintf(msg, "Can't discover the memory channel");
1393 if (n_tads == MAX_TAD) {
1394 sprintf(msg, "Can't discover the memory channel");
1398 ch_way = TAD_CH(reg) + 1;
1399 sck_way = TAD_SOCK(reg);
1404 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1408 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1412 base_ch = TAD_TGT0(reg);
1415 base_ch = TAD_TGT1(reg);
1418 base_ch = TAD_TGT2(reg);
1421 base_ch = TAD_TGT3(reg);
1424 sprintf(msg, "Can't discover the TAD target");
1427 *channel_mask = 1 << base_ch;
1429 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1430 tad_ch_nilv_offset[n_tads],
1433 if (pvt->is_mirrored) {
1434 *channel_mask |= 1 << ((base_ch + 2) % 4);
1438 sck_xch = (1 << sck_way) * (ch_way >> 1);
1441 sprintf(msg, "Invalid mirror set. Can't decode addr");
1445 sck_xch = (1 << sck_way) * ch_way;
1447 if (pvt->is_lockstep)
1448 *channel_mask |= 1 << ((base_ch + 1) % 4);
1450 offset = TAD_OFFSET(tad_offset);
1452 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1463 /* Calculate channel address */
1464 /* Remove the TAD offset */
1466 if (offset > addr) {
1467 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1472 ch_addr = addr - offset;
1473 ch_addr >>= (6 + shiftup);
1475 ch_addr <<= (6 + shiftup);
1476 ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
1479 * Step 3) Decode rank
1481 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1482 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1483 rir_way_limit[n_rir],
1486 if (!IS_RIR_VALID(reg))
1489 limit = pvt->info.rir_limit(reg);
1490 gb = div_u64_rem(limit >> 20, 1024, &mb);
1491 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1496 if (ch_addr <= limit)
1499 if (n_rir == MAX_RIR_RANGES) {
1500 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1504 rir_way = RIR_WAY(reg);
1506 if (pvt->is_close_pg)
1507 idx = (ch_addr >> 6);
1509 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1510 idx %= 1 << rir_way;
1512 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1513 rir_offset[n_rir][idx],
1515 *rank = RIR_RNK_TGT(reg);
1517 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1527 /****************************************************************************
1528 Device initialization routines: put/get, init/exit
1529 ****************************************************************************/
1532 * sbridge_put_all_devices 'put' all the devices that we have
1533 * reserved via 'get'
1535 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1540 for (i = 0; i < sbridge_dev->n_devs; i++) {
1541 struct pci_dev *pdev = sbridge_dev->pdev[i];
1544 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1546 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1551 static void sbridge_put_all_devices(void)
1553 struct sbridge_dev *sbridge_dev, *tmp;
1555 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1556 sbridge_put_devices(sbridge_dev);
1557 free_sbridge_dev(sbridge_dev);
1561 static int sbridge_get_onedevice(struct pci_dev **prev,
1563 const struct pci_id_table *table,
1564 const unsigned devno)
1566 struct sbridge_dev *sbridge_dev;
1567 const struct pci_id_descr *dev_descr = &table->descr[devno];
1568 struct pci_dev *pdev = NULL;
1571 sbridge_printk(KERN_DEBUG,
1572 "Seeking for: PCI ID %04x:%04x\n",
1573 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1575 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1576 dev_descr->dev_id, *prev);
1584 if (dev_descr->optional)
1587 /* if the HA wasn't found */
1591 sbridge_printk(KERN_INFO,
1592 "Device not found: %04x:%04x\n",
1593 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1595 /* End of list, leave */
1598 bus = pdev->bus->number;
1600 sbridge_dev = get_sbridge_dev(bus);
1602 sbridge_dev = alloc_sbridge_dev(bus, table);
1610 if (sbridge_dev->pdev[devno]) {
1611 sbridge_printk(KERN_ERR,
1612 "Duplicated device for %04x:%04x\n",
1613 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1618 sbridge_dev->pdev[devno] = pdev;
1620 /* Be sure that the device is enabled */
1621 if (unlikely(pci_enable_device(pdev) < 0)) {
1622 sbridge_printk(KERN_ERR,
1623 "Couldn't enable %04x:%04x\n",
1624 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1628 edac_dbg(0, "Detected %04x:%04x\n",
1629 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1632 * As stated on drivers/pci/search.c, the reference count for
1633 * @from is always decremented if it is not %NULL. So, as we need
1634 * to get all devices up to null, we need to do a get for the device
1644 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1645 * devices we want to reference for this driver.
1646 * @num_mc: pointer to the memory controllers count, to be incremented in case
1648 * @table: model specific table
1650 * returns 0 in case of success or error code
1652 static int sbridge_get_all_devices(u8 *num_mc,
1653 const struct pci_id_table *table)
1656 struct pci_dev *pdev = NULL;
1658 while (table && table->descr) {
1659 for (i = 0; i < table->n_devs; i++) {
1662 rc = sbridge_get_onedevice(&pdev, num_mc,
1669 sbridge_put_all_devices();
1680 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1681 struct sbridge_dev *sbridge_dev)
1683 struct sbridge_pvt *pvt = mci->pvt_info;
1684 struct pci_dev *pdev;
1685 u8 saw_chan_mask = 0;
1688 for (i = 0; i < sbridge_dev->n_devs; i++) {
1689 pdev = sbridge_dev->pdev[i];
1693 switch (pdev->device) {
1694 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1695 pvt->pci_sad0 = pdev;
1697 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1698 pvt->pci_sad1 = pdev;
1700 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1701 pvt->pci_br0 = pdev;
1703 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1704 pvt->pci_ha0 = pdev;
1706 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1709 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1710 pvt->pci_ras = pdev;
1712 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1713 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1714 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1715 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1717 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1718 pvt->pci_tad[id] = pdev;
1719 saw_chan_mask |= 1 << id;
1722 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1723 pvt->pci_ddrio = pdev;
1729 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1730 pdev->vendor, pdev->device,
1735 /* Check if everything were registered */
1736 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1737 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
1740 if (saw_chan_mask != 0x0f)
1745 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1749 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1750 PCI_VENDOR_ID_INTEL, pdev->device);
1754 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1755 struct sbridge_dev *sbridge_dev)
1757 struct sbridge_pvt *pvt = mci->pvt_info;
1758 struct pci_dev *pdev;
1759 u8 saw_chan_mask = 0;
1762 for (i = 0; i < sbridge_dev->n_devs; i++) {
1763 pdev = sbridge_dev->pdev[i];
1767 switch (pdev->device) {
1768 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1769 pvt->pci_ha0 = pdev;
1771 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1773 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1774 pvt->pci_ras = pdev;
1776 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1777 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1778 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1779 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1781 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1782 pvt->pci_tad[id] = pdev;
1783 saw_chan_mask |= 1 << id;
1786 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1787 pvt->pci_ddrio = pdev;
1789 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1790 pvt->pci_ddrio = pdev;
1792 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1793 pvt->pci_sad0 = pdev;
1795 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1796 pvt->pci_br0 = pdev;
1798 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1799 pvt->pci_br1 = pdev;
1801 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1802 pvt->pci_ha1 = pdev;
1804 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1805 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1806 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
1807 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
1809 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
1810 pvt->pci_tad[id] = pdev;
1811 saw_chan_mask |= 1 << id;
1818 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1820 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1824 /* Check if everything were registered */
1825 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1826 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
1830 if (saw_chan_mask != 0x0f && /* -EN */
1831 saw_chan_mask != 0x33 && /* -EP */
1832 saw_chan_mask != 0xff) /* -EX */
1837 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1841 sbridge_printk(KERN_ERR,
1842 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1847 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1848 struct sbridge_dev *sbridge_dev)
1850 struct sbridge_pvt *pvt = mci->pvt_info;
1851 struct pci_dev *pdev;
1852 u8 saw_chan_mask = 0;
1855 /* there's only one device per system; not tied to any bus */
1856 if (pvt->info.pci_vtd == NULL)
1857 /* result will be checked later */
1858 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1859 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1862 for (i = 0; i < sbridge_dev->n_devs; i++) {
1863 pdev = sbridge_dev->pdev[i];
1867 switch (pdev->device) {
1868 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1869 pvt->pci_sad0 = pdev;
1871 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1872 pvt->pci_sad1 = pdev;
1874 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1875 pvt->pci_ha0 = pdev;
1877 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1880 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1881 pvt->pci_ras = pdev;
1883 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1884 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1885 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1886 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1888 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
1890 pvt->pci_tad[id] = pdev;
1891 saw_chan_mask |= 1 << id;
1894 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1895 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1896 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
1897 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
1899 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
1901 pvt->pci_tad[id] = pdev;
1902 saw_chan_mask |= 1 << id;
1905 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1906 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
1907 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
1908 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
1909 if (!pvt->pci_ddrio)
1910 pvt->pci_ddrio = pdev;
1912 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1913 pvt->pci_ha1 = pdev;
1915 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1916 pvt->pci_ha1_ta = pdev;
1922 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1924 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1928 /* Check if everything were registered */
1929 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1930 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1933 if (saw_chan_mask != 0x0f && /* -EN */
1934 saw_chan_mask != 0x33 && /* -EP */
1935 saw_chan_mask != 0xff) /* -EX */
1940 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1944 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
1945 struct sbridge_dev *sbridge_dev)
1947 struct sbridge_pvt *pvt = mci->pvt_info;
1948 struct pci_dev *pdev;
1949 u8 saw_chan_mask = 0;
1952 /* there's only one device per system; not tied to any bus */
1953 if (pvt->info.pci_vtd == NULL)
1954 /* result will be checked later */
1955 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1956 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
1959 for (i = 0; i < sbridge_dev->n_devs; i++) {
1960 pdev = sbridge_dev->pdev[i];
1964 switch (pdev->device) {
1965 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
1966 pvt->pci_sad0 = pdev;
1968 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
1969 pvt->pci_sad1 = pdev;
1971 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
1972 pvt->pci_ha0 = pdev;
1974 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
1977 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
1978 pvt->pci_ras = pdev;
1980 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
1981 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
1982 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
1983 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
1985 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
1986 pvt->pci_tad[id] = pdev;
1987 saw_chan_mask |= 1 << id;
1990 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
1991 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
1992 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
1993 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
1995 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
1996 pvt->pci_tad[id] = pdev;
1997 saw_chan_mask |= 1 << id;
2000 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2001 pvt->pci_ddrio = pdev;
2003 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2004 pvt->pci_ha1 = pdev;
2006 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2007 pvt->pci_ha1_ta = pdev;
2013 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2015 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2019 /* Check if everything were registered */
2020 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2021 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2024 if (saw_chan_mask != 0x0f && /* -EN */
2025 saw_chan_mask != 0x33 && /* -EP */
2026 saw_chan_mask != 0xff) /* -EX */
2031 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2035 /****************************************************************************
2036 Error check routines
2037 ****************************************************************************/
2040 * While Sandy Bridge has error count registers, SMI BIOS read values from
2041 * and resets the counters. So, they are not reliable for the OS to read
2042 * from them. So, we have no option but to just trust on whatever MCE is
2043 * telling us about the errors.
2045 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2046 const struct mce *m)
2048 struct mem_ctl_info *new_mci;
2049 struct sbridge_pvt *pvt = mci->pvt_info;
2050 enum hw_event_mc_err_type tp_event;
2051 char *type, *optype, msg[256];
2052 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2053 bool overflow = GET_BITFIELD(m->status, 62, 62);
2054 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2056 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2057 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2058 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2059 u32 channel = GET_BITFIELD(m->status, 0, 3);
2060 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2061 long channel_mask, first_channel;
2062 u8 rank, socket, ha;
2064 char *area_type = NULL;
2066 if (pvt->info.type != SANDY_BRIDGE)
2069 recoverable = GET_BITFIELD(m->status, 56, 56);
2071 if (uncorrected_error) {
2074 tp_event = HW_EVENT_ERR_FATAL;
2077 tp_event = HW_EVENT_ERR_UNCORRECTED;
2081 tp_event = HW_EVENT_ERR_CORRECTED;
2085 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2086 * memory errors should fit in this mask:
2087 * 000f 0000 1mmm cccc (binary)
2089 * f = Correction Report Filtering Bit. If 1, subsequent errors
2093 * If the mask doesn't match, report an error to the parsing logic
2095 if (! ((errcode & 0xef80) == 0x80)) {
2096 optype = "Can't parse: it is not a mem";
2098 switch (optypenum) {
2100 optype = "generic undef request error";
2103 optype = "memory read error";
2106 optype = "memory write error";
2109 optype = "addr/cmd error";
2112 optype = "memory scrubbing error";
2115 optype = "reserved";
2120 /* Only decode errors with an valid address (ADDRV) */
2121 if (!GET_BITFIELD(m->status, 58, 58))
2124 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
2125 &channel_mask, &rank, &area_type, msg);
2128 new_mci = get_mci_for_node_id(socket);
2130 strcpy(msg, "Error: socket got corrupted!");
2134 pvt = mci->pvt_info;
2136 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2147 * FIXME: On some memory configurations (mirror, lockstep), the
2148 * Memory Controller can't point the error to a single DIMM. The
2149 * EDAC core should be handling the channel mask, in order to point
2150 * to the group of dimm's where the error may be happening.
2152 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
2153 channel = first_channel;
2155 snprintf(msg, sizeof(msg),
2156 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
2157 overflow ? " OVERFLOW" : "",
2158 (uncorrected_error && recoverable) ? " recoverable" : "",
2165 edac_dbg(0, "%s\n", msg);
2167 /* FIXME: need support for channel mask */
2169 if (channel == CHANNEL_UNSPECIFIED)
2172 /* Call the helper to output message */
2173 edac_mc_handle_error(tp_event, mci, core_err_cnt,
2174 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2175 4*ha+channel, dimm, -1,
2179 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
2186 * sbridge_check_error Retrieve and process errors reported by the
2187 * hardware. Called by the Core module.
2189 static void sbridge_check_error(struct mem_ctl_info *mci)
2191 struct sbridge_pvt *pvt = mci->pvt_info;
2197 * MCE first step: Copy all mce errors into a temporary buffer
2198 * We use a double buffering here, to reduce the risk of
2202 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2207 m = pvt->mce_outentry;
2208 if (pvt->mce_in + count > MCE_LOG_LEN) {
2209 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2211 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2217 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2219 pvt->mce_in += count;
2222 if (pvt->mce_overrun) {
2223 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2226 pvt->mce_overrun = 0;
2230 * MCE second step: parse errors and display
2232 for (i = 0; i < count; i++)
2233 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2237 * sbridge_mce_check_error Replicates mcelog routine to get errors
2238 * This routine simply queues mcelog errors, and
2239 * return. The error itself should be handled later
2240 * by sbridge_check_error.
2241 * WARNING: As this routine should be called at NMI time, extra care should
2242 * be taken to avoid deadlocks, and to be as fast as possible.
2244 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2247 struct mce *mce = (struct mce *)data;
2248 struct mem_ctl_info *mci;
2249 struct sbridge_pvt *pvt;
2252 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2255 mci = get_mci_for_node_id(mce->socketid);
2258 pvt = mci->pvt_info;
2261 * Just let mcelog handle it if the error is
2262 * outside the memory controller. A memory error
2263 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2264 * bit 12 has an special meaning.
2266 if ((mce->status & 0xefff) >> 7 != 1)
2269 if (mce->mcgstatus & MCG_STATUS_MCIP)
2274 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2276 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2277 "Bank %d: %016Lx\n", mce->extcpu, type,
2278 mce->mcgstatus, mce->bank, mce->status);
2279 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2280 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2281 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2283 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2284 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2285 mce->time, mce->socketid, mce->apicid);
2288 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2294 /* Copy memory error at the ringbuffer */
2295 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2297 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2299 /* Handle fatal errors immediately */
2300 if (mce->mcgstatus & 1)
2301 sbridge_check_error(mci);
2303 /* Advice mcelog that the error were handled */
2307 static struct notifier_block sbridge_mce_dec = {
2308 .notifier_call = sbridge_mce_check_error,
2311 /****************************************************************************
2312 EDAC register/unregister logic
2313 ****************************************************************************/
2315 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2317 struct mem_ctl_info *mci = sbridge_dev->mci;
2318 struct sbridge_pvt *pvt;
2320 if (unlikely(!mci || !mci->pvt_info)) {
2321 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2323 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2327 pvt = mci->pvt_info;
2329 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2330 mci, &sbridge_dev->pdev[0]->dev);
2332 /* Remove MC sysfs nodes */
2333 edac_mc_del_mc(mci->pdev);
2335 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2336 kfree(mci->ctl_name);
2338 sbridge_dev->mci = NULL;
2341 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2343 struct mem_ctl_info *mci;
2344 struct edac_mc_layer layers[2];
2345 struct sbridge_pvt *pvt;
2346 struct pci_dev *pdev = sbridge_dev->pdev[0];
2349 /* Check the number of active and not disabled channels */
2350 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2351 if (unlikely(rc < 0))
2354 /* allocate a new MC control structure */
2355 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2356 layers[0].size = NUM_CHANNELS;
2357 layers[0].is_virt_csrow = false;
2358 layers[1].type = EDAC_MC_LAYER_SLOT;
2359 layers[1].size = MAX_DIMMS;
2360 layers[1].is_virt_csrow = true;
2361 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2367 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2370 pvt = mci->pvt_info;
2371 memset(pvt, 0, sizeof(*pvt));
2373 /* Associate sbridge_dev and mci for future usage */
2374 pvt->sbridge_dev = sbridge_dev;
2375 sbridge_dev->mci = mci;
2377 mci->mtype_cap = MEM_FLAG_DDR3;
2378 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2379 mci->edac_cap = EDAC_FLAG_NONE;
2380 mci->mod_name = "sbridge_edac.c";
2381 mci->mod_ver = SBRIDGE_REVISION;
2382 mci->dev_name = pci_name(pdev);
2383 mci->ctl_page_to_phys = NULL;
2385 /* Set the function pointer to an actual operation function */
2386 mci->edac_check = sbridge_check_error;
2388 pvt->info.type = type;
2391 pvt->info.rankcfgr = IB_RANK_CFG_A;
2392 pvt->info.get_tolm = ibridge_get_tolm;
2393 pvt->info.get_tohm = ibridge_get_tohm;
2394 pvt->info.dram_rule = ibridge_dram_rule;
2395 pvt->info.get_memory_type = get_memory_type;
2396 pvt->info.get_node_id = get_node_id;
2397 pvt->info.rir_limit = rir_limit;
2398 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2399 pvt->info.interleave_list = ibridge_interleave_list;
2400 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2401 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2402 pvt->info.get_width = ibridge_get_width;
2403 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2405 /* Store pci devices at mci for faster access */
2406 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2407 if (unlikely(rc < 0))
2411 pvt->info.rankcfgr = SB_RANK_CFG_A;
2412 pvt->info.get_tolm = sbridge_get_tolm;
2413 pvt->info.get_tohm = sbridge_get_tohm;
2414 pvt->info.dram_rule = sbridge_dram_rule;
2415 pvt->info.get_memory_type = get_memory_type;
2416 pvt->info.get_node_id = get_node_id;
2417 pvt->info.rir_limit = rir_limit;
2418 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2419 pvt->info.interleave_list = sbridge_interleave_list;
2420 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2421 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2422 pvt->info.get_width = sbridge_get_width;
2423 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2425 /* Store pci devices at mci for faster access */
2426 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2427 if (unlikely(rc < 0))
2431 /* rankcfgr isn't used */
2432 pvt->info.get_tolm = haswell_get_tolm;
2433 pvt->info.get_tohm = haswell_get_tohm;
2434 pvt->info.dram_rule = ibridge_dram_rule;
2435 pvt->info.get_memory_type = haswell_get_memory_type;
2436 pvt->info.get_node_id = haswell_get_node_id;
2437 pvt->info.rir_limit = haswell_rir_limit;
2438 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2439 pvt->info.interleave_list = ibridge_interleave_list;
2440 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2441 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2442 pvt->info.get_width = ibridge_get_width;
2443 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2445 /* Store pci devices at mci for faster access */
2446 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2447 if (unlikely(rc < 0))
2451 /* rankcfgr isn't used */
2452 pvt->info.get_tolm = haswell_get_tolm;
2453 pvt->info.get_tohm = haswell_get_tohm;
2454 pvt->info.dram_rule = ibridge_dram_rule;
2455 pvt->info.get_memory_type = haswell_get_memory_type;
2456 pvt->info.get_node_id = haswell_get_node_id;
2457 pvt->info.rir_limit = haswell_rir_limit;
2458 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2459 pvt->info.interleave_list = ibridge_interleave_list;
2460 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2461 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2462 pvt->info.get_width = broadwell_get_width;
2463 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
2465 /* Store pci devices at mci for faster access */
2466 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
2467 if (unlikely(rc < 0))
2472 /* Get dimm basic config and the memory layout */
2473 get_dimm_config(mci);
2474 get_memory_layout(mci);
2476 /* record ptr to the generic device */
2477 mci->pdev = &pdev->dev;
2479 /* add this new MC control structure to EDAC's list of MCs */
2480 if (unlikely(edac_mc_add_mc(mci))) {
2481 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2489 kfree(mci->ctl_name);
2491 sbridge_dev->mci = NULL;
2496 * sbridge_probe Probe for ONE instance of device to see if it is
2499 * 0 for FOUND a device
2500 * < 0 for error code
2503 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2507 struct sbridge_dev *sbridge_dev;
2508 enum type type = SANDY_BRIDGE;
2510 /* get the pci devices we want to reserve for our use */
2511 mutex_lock(&sbridge_edac_lock);
2514 * All memory controllers are allocated at the first pass.
2516 if (unlikely(probed >= 1)) {
2517 mutex_unlock(&sbridge_edac_lock);
2522 switch (pdev->device) {
2523 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2524 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2527 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2528 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2529 type = SANDY_BRIDGE;
2531 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2532 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2535 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2536 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
2540 if (unlikely(rc < 0)) {
2541 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
2547 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2548 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2549 mc, mc + 1, num_mc);
2551 sbridge_dev->mc = mc++;
2552 rc = sbridge_register_mci(sbridge_dev, type);
2553 if (unlikely(rc < 0))
2557 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
2559 mutex_unlock(&sbridge_edac_lock);
2563 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2564 sbridge_unregister_mci(sbridge_dev);
2566 sbridge_put_all_devices();
2568 mutex_unlock(&sbridge_edac_lock);
2573 * sbridge_remove destructor for one instance of device
2576 static void sbridge_remove(struct pci_dev *pdev)
2578 struct sbridge_dev *sbridge_dev;
2583 * we have a trouble here: pdev value for removal will be wrong, since
2584 * it will point to the X58 register used to detect that the machine
2585 * is a Nehalem or upper design. However, due to the way several PCI
2586 * devices are grouped together to provide MC functionality, we need
2587 * to use a different method for releasing the devices
2590 mutex_lock(&sbridge_edac_lock);
2592 if (unlikely(!probed)) {
2593 mutex_unlock(&sbridge_edac_lock);
2597 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2598 sbridge_unregister_mci(sbridge_dev);
2600 /* Release PCI resources */
2601 sbridge_put_all_devices();
2605 mutex_unlock(&sbridge_edac_lock);
2608 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2611 * sbridge_driver pci_driver structure for this module
2614 static struct pci_driver sbridge_driver = {
2615 .name = "sbridge_edac",
2616 .probe = sbridge_probe,
2617 .remove = sbridge_remove,
2618 .id_table = sbridge_pci_tbl,
2622 * sbridge_init Module entry function
2623 * Try to initialize this module for its devices
2625 static int __init sbridge_init(void)
2631 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2634 pci_rc = pci_register_driver(&sbridge_driver);
2636 mce_register_decode_chain(&sbridge_mce_dec);
2637 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2638 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2642 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2649 * sbridge_exit() Module exit function
2650 * Unregister the driver
2652 static void __exit sbridge_exit(void)
2655 pci_unregister_driver(&sbridge_driver);
2656 mce_unregister_decode_chain(&sbridge_mce_dec);
2659 module_init(sbridge_init);
2660 module_exit(sbridge_exit);
2662 module_param(edac_op_state, int, 0444);
2663 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2665 MODULE_LICENSE("GPL");
2666 MODULE_AUTHOR("Mauro Carvalho Chehab");
2667 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2668 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "