1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
27 #include "edac_core.h"
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
35 * Alter this version for the module when modifications are made
37 #define SBRIDGE_REVISION " Ver: 1.0.0 "
38 #define EDAC_MOD_STR "sbridge_edac"
43 #define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
46 #define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
52 #define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
56 * sbridge Memory Controller Registers
60 * FIXME: For now, let's order by device function, as it makes
61 * easier for driver's development proccess. This table should be
62 * moved to pci_id.h when submitted upstream
64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
85 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86 static const u32 dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
90 #define MAX_SAD ARRAY_SIZE(dram_rule)
92 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
97 static char *get_dram_attr(u32 reg)
99 switch(DRAM_ATTR(reg)) {
111 static const u32 interleave_list[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
115 #define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
117 #define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118 #define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119 #define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120 #define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121 #define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122 #define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123 #define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124 #define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
126 static inline int sad_pkg(u32 reg, int interleave)
128 switch (interleave) {
130 return SAD_PKG0(reg);
132 return SAD_PKG1(reg);
134 return SAD_PKG2(reg);
136 return SAD_PKG3(reg);
138 return SAD_PKG4(reg);
140 return SAD_PKG5(reg);
142 return SAD_PKG6(reg);
144 return SAD_PKG7(reg);
150 /* Devices 12 Function 7 */
155 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
158 /* Device 13 Function 6 */
160 #define SAD_TARGET 0xf0
162 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
164 #define SAD_CONTROL 0xf4
166 #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
168 /* Device 14 function 0 */
170 static const u32 tad_dram_rule[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
175 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
177 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
185 /* Device 15, function 0 */
189 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
193 /* Device 15, function 1 */
195 #define RASENABLES 0xac
196 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
198 /* Device 15, functions 2-5 */
200 static const int mtr_regs[] = {
204 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
210 static const u32 tad_ch_nilv_offset[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
215 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
218 static const u32 rir_way_limit[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
221 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
223 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225 #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
227 #define MAX_RIR_WAY 8
229 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
237 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
240 /* Device 16, functions 2-7 */
243 * FIXME: Implement the error count reads directly
246 static const u32 correrrcnt[] = {
247 0x104, 0x108, 0x10c, 0x110,
250 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
255 static const u32 correrrthrsld[] = {
256 0x11c, 0x120, 0x124, 0x128,
259 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
263 /* Device 17, function 0 */
265 #define RANK_CFG_A 0x0328
267 #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
273 #define NUM_CHANNELS 4
274 #define MAX_DIMMS 3 /* Max DIMMS per channel */
276 struct sbridge_info {
280 struct sbridge_channel {
285 struct pci_id_descr {
292 struct pci_id_table {
293 const struct pci_id_descr *descr;
298 struct list_head list;
300 u8 node_id, source_id;
301 struct pci_dev **pdev;
303 struct mem_ctl_info *mci;
307 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
308 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
309 struct pci_dev *pci_br;
310 struct pci_dev *pci_tad[NUM_CHANNELS];
312 struct sbridge_dev *sbridge_dev;
314 struct sbridge_info info;
315 struct sbridge_channel channel[NUM_CHANNELS];
317 int csrow_map[NUM_CHANNELS][MAX_DIMMS];
319 /* Memory type detection */
320 bool is_mirrored, is_lockstep, is_close_pg;
322 /* Fifo double buffers */
323 struct mce mce_entry[MCE_LOG_LEN];
324 struct mce mce_outentry[MCE_LOG_LEN];
326 /* Fifo in/out counters */
327 unsigned mce_in, mce_out;
329 /* Count indicator to show errors not got */
330 unsigned mce_overrun;
332 /* Memory description */
336 #define PCI_DESCR(device, function, device_id) \
338 .func = (function), \
339 .dev_id = (device_id)
341 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
342 /* Processor Home Agent */
343 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
345 /* Memory controller */
346 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
347 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
348 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
349 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
350 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
351 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
352 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
354 /* System Address Decoder */
355 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
356 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
358 /* Broadcast Registers */
359 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
362 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
363 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
364 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
365 {0,} /* 0 terminated list. */
369 * pci_device_id table for which devices we are looking for
371 static const struct pci_device_id sbridge_pci_tbl[] __devinitdata = {
372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
373 {0,} /* 0 terminated list. */
377 /****************************************************************************
378 Anciliary status routines
379 ****************************************************************************/
381 static inline int numrank(u32 mtr)
383 int ranks = (1 << RANK_CNT_BITS(mtr));
386 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)",
387 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
394 static inline int numrow(u32 mtr)
396 int rows = (RANK_WIDTH_BITS(mtr) + 12);
398 if (rows < 13 || rows > 18) {
399 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)",
400 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
407 static inline int numcol(u32 mtr)
409 int cols = (COL_WIDTH_BITS(mtr) + 10);
412 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)",
413 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
420 static struct sbridge_dev *get_sbridge_dev(u8 bus)
422 struct sbridge_dev *sbridge_dev;
424 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
425 if (sbridge_dev->bus == bus)
432 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
433 const struct pci_id_table *table)
435 struct sbridge_dev *sbridge_dev;
437 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
441 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
443 if (!sbridge_dev->pdev) {
448 sbridge_dev->bus = bus;
449 sbridge_dev->n_devs = table->n_devs;
450 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
455 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
457 list_del(&sbridge_dev->list);
458 kfree(sbridge_dev->pdev);
462 /****************************************************************************
463 Memory check routines
464 ****************************************************************************/
465 static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
468 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
474 for (i = 0; i < sbridge_dev->n_devs; i++) {
475 if (!sbridge_dev->pdev[i])
478 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
479 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
480 debugf1("Associated %02x.%02x.%d with %p\n",
481 bus, slot, func, sbridge_dev->pdev[i]);
482 return sbridge_dev->pdev[i];
490 * sbridge_get_active_channels() - gets the number of channels and csrows
492 * @channels: Number of channels that will be returned
493 * @csrows: Number of csrows found
495 * Since EDAC core needs to know in advance the number of available channels
496 * and csrows, in order to allocate memory for csrows/channels, it is needed
497 * to run two similar steps. At the first step, implemented on this function,
498 * it checks the number of csrows/channels present at one socket, identified
499 * by the associated PCI bus.
500 * this is used in order to properly allocate the size of mci components.
501 * Note: one csrow is one dimm.
503 static int sbridge_get_active_channels(const u8 bus, unsigned *channels,
506 struct pci_dev *pdev = NULL;
513 pdev = get_pdev_slot_func(bus, 15, 0);
515 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
521 pci_read_config_dword(pdev, MCMTR, &mcmtr);
522 if (!IS_ECC_ENABLED(mcmtr)) {
523 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
527 for (i = 0; i < NUM_CHANNELS; i++) {
530 /* Device 15 functions 2 - 5 */
531 pdev = get_pdev_slot_func(bus, 15, 2 + i);
533 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
540 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
541 pci_read_config_dword(pdev, mtr_regs[j], &mtr);
542 debugf1("Bus#%02x channel #%d MTR%d = %x\n", bus, i, j, mtr);
543 if (IS_DIMM_PRESENT(mtr))
548 debugf0("Number of active channels: %d, number of active dimms: %d\n",
554 static int get_dimm_config(const struct mem_ctl_info *mci)
556 struct sbridge_pvt *pvt = mci->pvt_info;
557 struct csrow_info *csr;
558 int i, j, banks, ranks, rows, cols, size, npages;
560 unsigned long last_page = 0;
565 pci_read_config_dword(pvt->pci_br, SAD_TARGET, ®);
566 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
568 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®);
569 pvt->sbridge_dev->node_id = NODE_ID(reg);
570 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
571 pvt->sbridge_dev->mc,
572 pvt->sbridge_dev->node_id,
573 pvt->sbridge_dev->source_id);
575 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®);
576 if (IS_MIRROR_ENABLED(reg)) {
577 debugf0("Memory mirror is enabled\n");
578 pvt->is_mirrored = true;
580 debugf0("Memory mirror is disabled\n");
581 pvt->is_mirrored = false;
584 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
585 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
586 debugf0("Lockstep is enabled\n");
587 mode = EDAC_S8ECD8ED;
588 pvt->is_lockstep = true;
590 debugf0("Lockstep is disabled\n");
591 mode = EDAC_S4ECD4ED;
592 pvt->is_lockstep = false;
594 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
595 debugf0("address map is on closed page mode\n");
596 pvt->is_close_pg = true;
598 debugf0("address map is on open page mode\n");
599 pvt->is_close_pg = false;
602 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, ®);
603 if (IS_RDIMM_ENABLED(reg)) {
604 /* FIXME: Can also be LRDIMM */
605 debugf0("Memory is registered\n");
608 debugf0("Memory is unregistered\n");
612 /* On all supported DDR3 DIMM types, there are 8 banks available */
615 for (i = 0; i < NUM_CHANNELS; i++) {
618 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
619 pci_read_config_dword(pvt->pci_tad[i],
621 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
622 if (IS_DIMM_PRESENT(mtr)) {
623 pvt->channel[i].dimms++;
625 ranks = numrank(mtr);
629 /* DDR3 has 8 I/O banks */
630 size = (rows * cols * banks * ranks) >> (20 - 3);
631 npages = MiB_TO_PAGES(size);
633 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
634 pvt->sbridge_dev->mc, i, j,
636 banks, ranks, rows, cols);
637 csr = &mci->csrows[csrow];
639 csr->first_page = last_page;
640 csr->last_page = last_page + npages - 1;
641 csr->page_mask = 0UL; /* Unused */
642 csr->nr_pages = npages;
644 csr->csrow_idx = csrow;
645 csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
649 csr->edac_mode = mode;
650 csr->nr_channels = 1;
651 csr->channels[0].chan_idx = i;
652 csr->channels[0].ce_count = 0;
653 pvt->csrow_map[i][j] = csrow;
654 snprintf(csr->channels[0].label,
655 sizeof(csr->channels[0].label),
656 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
657 pvt->sbridge_dev->source_id, i, j);
667 static void get_memory_layout(const struct mem_ctl_info *mci)
669 struct sbridge_pvt *pvt = mci->pvt_info;
670 int i, j, k, n_sads, n_tads, sad_interl;
678 * Step 1) Get TOLM/TOHM ranges
681 /* Address range is 32:28 */
682 pci_read_config_dword(pvt->pci_sad1, TOLM,
684 pvt->tolm = GET_TOLM(reg);
685 tmp_mb = (1 + pvt->tolm) >> 20;
687 mb = div_u64_rem(tmp_mb, 1000, &kb);
688 debugf0("TOLM: %u.%03u GB (0x%016Lx)\n",
689 mb, kb, (u64)pvt->tolm);
691 /* Address range is already 45:25 */
692 pci_read_config_dword(pvt->pci_sad1, TOHM,
694 pvt->tohm = GET_TOHM(reg);
695 tmp_mb = (1 + pvt->tohm) >> 20;
697 mb = div_u64_rem(tmp_mb, 1000, &kb);
698 debugf0("TOHM: %u.%03u GB (0x%016Lx)",
699 mb, kb, (u64)pvt->tohm);
702 * Step 2) Get SAD range and SAD Interleave list
703 * TAD registers contain the interleave wayness. However, it
704 * seems simpler to just discover it indirectly, with the
708 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
709 /* SAD_LIMIT Address range is 45:26 */
710 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
712 limit = SAD_LIMIT(reg);
714 if (!DRAM_RULE_ENABLE(reg))
720 tmp_mb = (limit + 1) >> 20;
721 mb = div_u64_rem(tmp_mb, 1000, &kb);
722 debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n",
726 ((u64)tmp_mb) << 20L,
727 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
731 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
733 sad_interl = sad_pkg(reg, 0);
734 for (j = 0; j < 8; j++) {
735 if (j > 0 && sad_interl == sad_pkg(reg, j))
738 debugf0("SAD#%d, interleave #%d: %d\n",
739 n_sads, j, sad_pkg(reg, j));
744 * Step 3) Get TAD range
747 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
748 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
750 limit = TAD_LIMIT(reg);
753 tmp_mb = (limit + 1) >> 20;
755 mb = div_u64_rem(tmp_mb, 1000, &kb);
756 debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
758 ((u64)tmp_mb) << 20L,
770 * Step 4) Get TAD offsets, per each channel
772 for (i = 0; i < NUM_CHANNELS; i++) {
773 if (!pvt->channel[i].dimms)
775 for (j = 0; j < n_tads; j++) {
776 pci_read_config_dword(pvt->pci_tad[i],
777 tad_ch_nilv_offset[j],
779 tmp_mb = TAD_OFFSET(reg) >> 20;
780 mb = div_u64_rem(tmp_mb, 1000, &kb);
781 debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
784 ((u64)tmp_mb) << 20L,
790 * Step 6) Get RIR Wayness/Limit, per each channel
792 for (i = 0; i < NUM_CHANNELS; i++) {
793 if (!pvt->channel[i].dimms)
795 for (j = 0; j < MAX_RIR_RANGES; j++) {
796 pci_read_config_dword(pvt->pci_tad[i],
800 if (!IS_RIR_VALID(reg))
803 tmp_mb = RIR_LIMIT(reg) >> 20;
804 rir_way = 1 << RIR_WAY(reg);
805 mb = div_u64_rem(tmp_mb, 1000, &kb);
806 debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
809 ((u64)tmp_mb) << 20L,
813 for (k = 0; k < rir_way; k++) {
814 pci_read_config_dword(pvt->pci_tad[i],
817 tmp_mb = RIR_OFFSET(reg) << 6;
819 mb = div_u64_rem(tmp_mb, 1000, &kb);
820 debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
823 ((u64)tmp_mb) << 20L,
824 (u32)RIR_RNK_TGT(reg),
831 struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
833 struct sbridge_dev *sbridge_dev;
835 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
836 if (sbridge_dev->node_id == node_id)
837 return sbridge_dev->mci;
842 static int get_memory_error_data(struct mem_ctl_info *mci,
849 struct mem_ctl_info *new_mci;
850 struct sbridge_pvt *pvt = mci->pvt_info;
852 int n_rir, n_sads, n_tads, sad_way, sck_xch;
853 int sad_interl, idx, base_ch;
855 unsigned sad_interleave[MAX_INTERLEAVE];
861 u64 ch_addr, offset, limit, prv = 0;
865 * Step 0) Check if the address is at special memory ranges
866 * The check bellow is probably enough to fill all cases where
867 * the error is not inside a memory, except for the legacy
868 * range (e. g. VGA addresses). It is unlikely, however, that the
869 * memory controller would generate an error on that range.
871 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
872 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
873 edac_mc_handle_ce_no_info(mci, msg);
876 if (addr >= (u64)pvt->tohm) {
877 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
878 edac_mc_handle_ce_no_info(mci, msg);
885 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
886 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
889 if (!DRAM_RULE_ENABLE(reg))
892 limit = SAD_LIMIT(reg);
894 sprintf(msg, "Can't discover the memory socket");
895 edac_mc_handle_ce_no_info(mci, msg);
902 if (n_sads == MAX_SAD) {
903 sprintf(msg, "Can't discover the memory socket");
904 edac_mc_handle_ce_no_info(mci, msg);
907 area_type = get_dram_attr(reg);
908 interleave_mode = INTERLEAVE_MODE(reg);
910 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
912 sad_interl = sad_pkg(reg, 0);
913 for (sad_way = 0; sad_way < 8; sad_way++) {
914 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
916 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
917 debugf0("SAD interleave #%d: %d\n",
918 sad_way, sad_interleave[sad_way]);
920 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
921 pvt->sbridge_dev->mc,
926 INTERLEAVE_MODE(reg) ? "" : "XOR[18:16]");
928 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
930 idx = (addr >> 6) & 7;
944 sprintf(msg, "Can't discover socket interleave");
945 edac_mc_handle_ce_no_info(mci, msg);
948 *socket = sad_interleave[idx];
949 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n",
950 idx, sad_way, *socket);
953 * Move to the proper node structure, in order to access the
954 * right PCI registers
956 new_mci = get_mci_for_node_id(*socket);
958 sprintf(msg, "Struct for socket #%u wasn't initialized",
960 edac_mc_handle_ce_no_info(mci, msg);
967 * Step 2) Get memory channel
970 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
971 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
973 limit = TAD_LIMIT(reg);
975 sprintf(msg, "Can't discover the memory channel");
976 edac_mc_handle_ce_no_info(mci, msg);
983 ch_way = TAD_CH(reg) + 1;
984 sck_way = TAD_SOCK(reg) + 1;
986 * FIXME: Is it right to always use channel 0 for offsets?
988 pci_read_config_dword(pvt->pci_tad[0],
989 tad_ch_nilv_offset[n_tads],
995 idx = addr >> (6 + sck_way);
999 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1003 base_ch = TAD_TGT0(reg);
1006 base_ch = TAD_TGT1(reg);
1009 base_ch = TAD_TGT2(reg);
1012 base_ch = TAD_TGT3(reg);
1015 sprintf(msg, "Can't discover the TAD target");
1016 edac_mc_handle_ce_no_info(mci, msg);
1019 *channel_mask = 1 << base_ch;
1021 if (pvt->is_mirrored) {
1022 *channel_mask |= 1 << ((base_ch + 2) % 4);
1026 sck_xch = 1 << sck_way * (ch_way >> 1);
1029 sprintf(msg, "Invalid mirror set. Can't decode addr");
1030 edac_mc_handle_ce_no_info(mci, msg);
1034 sck_xch = (1 << sck_way) * ch_way;
1036 if (pvt->is_lockstep)
1037 *channel_mask |= 1 << ((base_ch + 1) % 4);
1039 offset = TAD_OFFSET(tad_offset);
1041 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1052 /* Calculate channel address */
1053 /* Remove the TAD offset */
1055 if (offset > addr) {
1056 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1058 edac_mc_handle_ce_no_info(mci, msg);
1062 /* Store the low bits [0:6] of the addr */
1063 ch_addr = addr & 0x7f;
1064 /* Remove socket wayness and remove 6 bits */
1066 addr = div_u64(addr, sck_xch);
1068 /* Divide by channel way */
1069 addr = addr / ch_way;
1071 /* Recover the last 6 bits */
1072 ch_addr |= addr << 6;
1075 * Step 3) Decode rank
1077 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1078 pci_read_config_dword(pvt->pci_tad[base_ch],
1079 rir_way_limit[n_rir],
1082 if (!IS_RIR_VALID(reg))
1085 limit = RIR_LIMIT(reg);
1086 mb = div_u64_rem(limit >> 20, 1000, &kb);
1087 debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1092 if (ch_addr <= limit)
1095 if (n_rir == MAX_RIR_RANGES) {
1096 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1098 edac_mc_handle_ce_no_info(mci, msg);
1101 rir_way = RIR_WAY(reg);
1102 if (pvt->is_close_pg)
1103 idx = (ch_addr >> 6);
1105 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1106 idx %= 1 << rir_way;
1108 pci_read_config_dword(pvt->pci_tad[base_ch],
1109 rir_offset[n_rir][idx],
1111 *rank = RIR_RNK_TGT(reg);
1113 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1123 /****************************************************************************
1124 Device initialization routines: put/get, init/exit
1125 ****************************************************************************/
1128 * sbridge_put_all_devices 'put' all the devices that we have
1129 * reserved via 'get'
1131 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1135 debugf0(__FILE__ ": %s()\n", __func__);
1136 for (i = 0; i < sbridge_dev->n_devs; i++) {
1137 struct pci_dev *pdev = sbridge_dev->pdev[i];
1140 debugf0("Removing dev %02x:%02x.%d\n",
1142 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1147 static void sbridge_put_all_devices(void)
1149 struct sbridge_dev *sbridge_dev, *tmp;
1151 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1152 sbridge_put_devices(sbridge_dev);
1153 free_sbridge_dev(sbridge_dev);
1158 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1159 * device/functions we want to reference for this driver
1161 * Need to 'get' device 16 func 1 and func 2
1163 static int sbridge_get_onedevice(struct pci_dev **prev,
1165 const struct pci_id_table *table,
1166 const unsigned devno)
1168 struct sbridge_dev *sbridge_dev;
1169 const struct pci_id_descr *dev_descr = &table->descr[devno];
1171 struct pci_dev *pdev = NULL;
1174 sbridge_printk(KERN_INFO,
1175 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1176 dev_descr->dev, dev_descr->func,
1177 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1179 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1180 dev_descr->dev_id, *prev);
1188 if (dev_descr->optional)
1194 sbridge_printk(KERN_INFO,
1195 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1196 dev_descr->dev, dev_descr->func,
1197 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1199 /* End of list, leave */
1202 bus = pdev->bus->number;
1204 sbridge_dev = get_sbridge_dev(bus);
1206 sbridge_dev = alloc_sbridge_dev(bus, table);
1214 if (sbridge_dev->pdev[devno]) {
1215 sbridge_printk(KERN_ERR,
1216 "Duplicated device for "
1217 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1218 bus, dev_descr->dev, dev_descr->func,
1219 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1224 sbridge_dev->pdev[devno] = pdev;
1227 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1228 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1229 sbridge_printk(KERN_ERR,
1230 "Device PCI ID %04x:%04x "
1231 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1232 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1233 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1234 bus, dev_descr->dev, dev_descr->func);
1238 /* Be sure that the device is enabled */
1239 if (unlikely(pci_enable_device(pdev) < 0)) {
1240 sbridge_printk(KERN_ERR,
1242 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1243 bus, dev_descr->dev, dev_descr->func,
1244 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1248 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1249 bus, dev_descr->dev,
1251 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1254 * As stated on drivers/pci/search.c, the reference count for
1255 * @from is always decremented if it is not %NULL. So, as we need
1256 * to get all devices up to null, we need to do a get for the device
1265 static int sbridge_get_all_devices(u8 *num_mc)
1268 struct pci_dev *pdev = NULL;
1269 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1271 while (table && table->descr) {
1272 for (i = 0; i < table->n_devs; i++) {
1275 rc = sbridge_get_onedevice(&pdev, num_mc,
1282 sbridge_put_all_devices();
1293 static int mci_bind_devs(struct mem_ctl_info *mci,
1294 struct sbridge_dev *sbridge_dev)
1296 struct sbridge_pvt *pvt = mci->pvt_info;
1297 struct pci_dev *pdev;
1300 for (i = 0; i < sbridge_dev->n_devs; i++) {
1301 pdev = sbridge_dev->pdev[i];
1304 slot = PCI_SLOT(pdev->devfn);
1305 func = PCI_FUNC(pdev->devfn);
1310 pvt->pci_sad0 = pdev;
1313 pvt->pci_sad1 = pdev;
1331 pvt->pci_ha0 = pdev;
1343 pvt->pci_ras = pdev;
1349 pvt->pci_tad[func - 2] = pdev;
1358 pvt->pci_ddrio = pdev;
1368 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n",
1370 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1374 /* Check if everything were registered */
1375 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1376 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1380 for (i = 0; i < NUM_CHANNELS; i++) {
1381 if (!pvt->pci_tad[i])
1387 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1391 sbridge_printk(KERN_ERR, "Device %d, function %d "
1392 "is out of the expected range\n",
1397 /****************************************************************************
1398 Error check routines
1399 ****************************************************************************/
1402 * While Sandy Bridge has error count registers, SMI BIOS read values from
1403 * and resets the counters. So, they are not reliable for the OS to read
1404 * from them. So, we have no option but to just trust on whatever MCE is
1405 * telling us about the errors.
1407 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1408 const struct mce *m)
1410 struct mem_ctl_info *new_mci;
1411 struct sbridge_pvt *pvt = mci->pvt_info;
1412 char *type, *optype, *msg, *recoverable_msg;
1413 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1414 bool overflow = GET_BITFIELD(m->status, 62, 62);
1415 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1416 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1417 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1418 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1419 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1420 u32 channel = GET_BITFIELD(m->status, 0, 3);
1421 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1422 long channel_mask, first_channel;
1424 int csrow, rc, dimm;
1425 char *area_type = "Unknown";
1433 * According with Table 15-9 of the Intel Archictecture spec vol 3A,
1434 * memory errors should fit in this mask:
1435 * 000f 0000 1mmm cccc (binary)
1437 * f = Correction Report Filtering Bit. If 1, subsequent errors
1441 * If the mask doesn't match, report an error to the parsing logic
1443 if (! ((errcode & 0xef80) == 0x80)) {
1444 optype = "Can't parse: it is not a mem";
1446 switch (optypenum) {
1448 optype = "generic undef request";
1451 optype = "memory read";
1454 optype = "memory write";
1457 optype = "addr/cmd";
1460 optype = "memory scrubbing";
1463 optype = "reserved";
1468 rc = get_memory_error_data(mci, m->addr, &socket,
1469 &channel_mask, &rank, area_type);
1472 new_mci = get_mci_for_node_id(socket);
1474 edac_mc_handle_ce_no_info(mci, "Error: socket got corrupted!");
1478 pvt = mci->pvt_info;
1480 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1489 csrow = pvt->csrow_map[first_channel][dimm];
1491 if (uncorrected_error && recoverable)
1492 recoverable_msg = " recoverable";
1494 recoverable_msg = "";
1497 * FIXME: What should we do with "channel" information on mcelog?
1498 * Probably, we can just discard it, as the channel information
1499 * comes from the get_memory_error_data() address decoding
1501 msg = kasprintf(GFP_ATOMIC,
1502 "%d %s error(s): %s on %s area %s%s: cpu=%d Err=%04x:%04x (ch=%d), "
1503 "addr = 0x%08llx => socket=%d, Channel=%ld(mask=%ld), rank=%d\n",
1509 overflow ? "OVERFLOW" : "",
1512 channel, /* 1111b means not specified */
1513 (long long) m->addr,
1515 first_channel, /* This is the real channel on SB */
1521 /* Call the helper to output message */
1522 if (uncorrected_error)
1523 edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg);
1525 edac_mc_handle_fbd_ce(mci, csrow, 0, msg);
1531 * sbridge_check_error Retrieve and process errors reported by the
1532 * hardware. Called by the Core module.
1534 static void sbridge_check_error(struct mem_ctl_info *mci)
1536 struct sbridge_pvt *pvt = mci->pvt_info;
1542 * MCE first step: Copy all mce errors into a temporary buffer
1543 * We use a double buffering here, to reduce the risk of
1547 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1552 m = pvt->mce_outentry;
1553 if (pvt->mce_in + count > MCE_LOG_LEN) {
1554 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1556 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1562 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1564 pvt->mce_in += count;
1567 if (pvt->mce_overrun) {
1568 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1571 pvt->mce_overrun = 0;
1575 * MCE second step: parse errors and display
1577 for (i = 0; i < count; i++)
1578 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1582 * sbridge_mce_check_error Replicates mcelog routine to get errors
1583 * This routine simply queues mcelog errors, and
1584 * return. The error itself should be handled later
1585 * by sbridge_check_error.
1586 * WARNING: As this routine should be called at NMI time, extra care should
1587 * be taken to avoid deadlocks, and to be as fast as possible.
1589 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1592 struct mce *mce = (struct mce *)data;
1593 struct mem_ctl_info *mci;
1594 struct sbridge_pvt *pvt;
1596 mci = get_mci_for_node_id(mce->socketid);
1599 pvt = mci->pvt_info;
1602 * Just let mcelog handle it if the error is
1603 * outside the memory controller. A memory error
1604 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1605 * bit 12 has an special meaning.
1607 if ((mce->status & 0xefff) >> 7 != 1)
1610 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1612 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1613 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1614 printk("TSC %llx ", mce->tsc);
1615 printk("ADDR %llx ", mce->addr);
1616 printk("MISC %llx ", mce->misc);
1618 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1619 mce->cpuvendor, mce->cpuid, mce->time,
1620 mce->socketid, mce->apicid);
1622 /* Only handle if it is the right mc controller */
1623 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
1627 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1633 /* Copy memory error at the ringbuffer */
1634 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1636 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1638 /* Handle fatal errors immediately */
1639 if (mce->mcgstatus & 1)
1640 sbridge_check_error(mci);
1642 /* Advice mcelog that the error were handled */
1646 static struct notifier_block sbridge_mce_dec = {
1647 .notifier_call = sbridge_mce_check_error,
1650 /****************************************************************************
1651 EDAC register/unregister logic
1652 ****************************************************************************/
1654 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1656 struct mem_ctl_info *mci = sbridge_dev->mci;
1657 struct sbridge_pvt *pvt;
1659 if (unlikely(!mci || !mci->pvt_info)) {
1660 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
1661 __func__, &sbridge_dev->pdev[0]->dev);
1663 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1667 pvt = mci->pvt_info;
1669 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1670 __func__, mci, &sbridge_dev->pdev[0]->dev);
1672 mce_unregister_decode_chain(&sbridge_mce_dec);
1674 /* Remove MC sysfs nodes */
1675 edac_mc_del_mc(mci->dev);
1677 debugf1("%s: free mci struct\n", mci->ctl_name);
1678 kfree(mci->ctl_name);
1680 sbridge_dev->mci = NULL;
1683 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1685 struct mem_ctl_info *mci;
1686 struct sbridge_pvt *pvt;
1687 int rc, channels, csrows;
1689 /* Check the number of active and not disabled channels */
1690 rc = sbridge_get_active_channels(sbridge_dev->bus, &channels, &csrows);
1691 if (unlikely(rc < 0))
1694 /* allocate a new MC control structure */
1695 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, sbridge_dev->mc);
1699 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1700 __func__, mci, &sbridge_dev->pdev[0]->dev);
1702 pvt = mci->pvt_info;
1703 memset(pvt, 0, sizeof(*pvt));
1705 /* Associate sbridge_dev and mci for future usage */
1706 pvt->sbridge_dev = sbridge_dev;
1707 sbridge_dev->mci = mci;
1709 mci->mtype_cap = MEM_FLAG_DDR3;
1710 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1711 mci->edac_cap = EDAC_FLAG_NONE;
1712 mci->mod_name = "sbridge_edac.c";
1713 mci->mod_ver = SBRIDGE_REVISION;
1714 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1715 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1716 mci->ctl_page_to_phys = NULL;
1718 /* Set the function pointer to an actual operation function */
1719 mci->edac_check = sbridge_check_error;
1721 /* Store pci devices at mci for faster access */
1722 rc = mci_bind_devs(mci, sbridge_dev);
1723 if (unlikely(rc < 0))
1726 /* Get dimm basic config and the memory layout */
1727 get_dimm_config(mci);
1728 get_memory_layout(mci);
1730 /* record ptr to the generic device */
1731 mci->dev = &sbridge_dev->pdev[0]->dev;
1733 /* add this new MC control structure to EDAC's list of MCs */
1734 if (unlikely(edac_mc_add_mc(mci))) {
1735 debugf0("MC: " __FILE__
1736 ": %s(): failed edac_mc_add_mc()\n", __func__);
1741 mce_register_decode_chain(&sbridge_mce_dec);
1745 kfree(mci->ctl_name);
1747 sbridge_dev->mci = NULL;
1752 * sbridge_probe Probe for ONE instance of device to see if it is
1755 * 0 for FOUND a device
1756 * < 0 for error code
1759 static int __devinit sbridge_probe(struct pci_dev *pdev,
1760 const struct pci_device_id *id)
1764 struct sbridge_dev *sbridge_dev;
1766 /* get the pci devices we want to reserve for our use */
1767 mutex_lock(&sbridge_edac_lock);
1770 * All memory controllers are allocated at the first pass.
1772 if (unlikely(probed >= 1)) {
1773 mutex_unlock(&sbridge_edac_lock);
1778 rc = sbridge_get_all_devices(&num_mc);
1779 if (unlikely(rc < 0))
1783 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1784 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc);
1785 sbridge_dev->mc = mc++;
1786 rc = sbridge_register_mci(sbridge_dev);
1787 if (unlikely(rc < 0))
1791 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1793 mutex_unlock(&sbridge_edac_lock);
1797 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1798 sbridge_unregister_mci(sbridge_dev);
1800 sbridge_put_all_devices();
1802 mutex_unlock(&sbridge_edac_lock);
1807 * sbridge_remove destructor for one instance of device
1810 static void __devexit sbridge_remove(struct pci_dev *pdev)
1812 struct sbridge_dev *sbridge_dev;
1814 debugf0(__FILE__ ": %s()\n", __func__);
1817 * we have a trouble here: pdev value for removal will be wrong, since
1818 * it will point to the X58 register used to detect that the machine
1819 * is a Nehalem or upper design. However, due to the way several PCI
1820 * devices are grouped together to provide MC functionality, we need
1821 * to use a different method for releasing the devices
1824 mutex_lock(&sbridge_edac_lock);
1826 if (unlikely(!probed)) {
1827 mutex_unlock(&sbridge_edac_lock);
1831 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1832 sbridge_unregister_mci(sbridge_dev);
1834 /* Release PCI resources */
1835 sbridge_put_all_devices();
1839 mutex_unlock(&sbridge_edac_lock);
1842 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1845 * sbridge_driver pci_driver structure for this module
1848 static struct pci_driver sbridge_driver = {
1849 .name = "sbridge_edac",
1850 .probe = sbridge_probe,
1851 .remove = __devexit_p(sbridge_remove),
1852 .id_table = sbridge_pci_tbl,
1856 * sbridge_init Module entry function
1857 * Try to initialize this module for its devices
1859 static int __init sbridge_init(void)
1863 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1865 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1868 pci_rc = pci_register_driver(&sbridge_driver);
1873 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1880 * sbridge_exit() Module exit function
1881 * Unregister the driver
1883 static void __exit sbridge_exit(void)
1885 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1886 pci_unregister_driver(&sbridge_driver);
1889 module_init(sbridge_init);
1890 module_exit(sbridge_exit);
1892 module_param(edac_op_state, int, 0444);
1893 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1895 MODULE_LICENSE("GPL");
1896 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1897 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1898 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "