drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <asm/processor.h>
  25 #include <asm/mce.h>
  26
  27 #include "edac_core.h"
  28
  29 /* Static vars */
  30 static LIST_HEAD(sbridge_edac_list);
  31 static DEFINE_MUTEX(sbridge_edac_lock);
  32 static int probed;
  33
  34 /*
  35  * Alter this version for the module when modifications are made
  36  */
  37 #define SBRIDGE_REVISION    " Ver: 1.1.1 "
  38 #define EDAC_MOD_STR      "sbridge_edac"
  39
  40 /*
  41  * Debug macros
  42  */
  43 #define sbridge_printk(level, fmt, arg...)                      \
  44         edac_printk(level, "sbridge", fmt, ##arg)
  45
  46 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  47         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  48
  49 /*
  50  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  51  */
  52 #define GET_BITFIELD(v, lo, hi) \
  53         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  54
  55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  56 static const u32 sbridge_dram_rule[] = {
  57         0x80, 0x88, 0x90, 0x98, 0xa0,
  58         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  59 };
  60
  61 static const u32 ibridge_dram_rule[] = {
  62         0x60, 0x68, 0x70, 0x78, 0x80,
  63         0x88, 0x90, 0x98, 0xa0, 0xa8,
  64         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  65         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  66 };
  67
  68 #define SAD_LIMIT(reg)          ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
  69 #define DRAM_ATTR(reg)          GET_BITFIELD(reg, 2,  3)
  70 #define INTERLEAVE_MODE(reg)    GET_BITFIELD(reg, 1,  1)
  71 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
  72 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
  73
  74 static char *get_dram_attr(u32 reg)
  75 {
  76         switch(DRAM_ATTR(reg)) {
  77                 case 0:
  78                         return "DRAM";
  79                 case 1:
  80                         return "MMCFG";
  81                 case 2:
  82                         return "NXM";
  83                 default:
  84                         return "unknown";
  85         }
  86 }
  87
  88 static const u32 sbridge_interleave_list[] = {
  89         0x84, 0x8c, 0x94, 0x9c, 0xa4,
  90         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
  91 };
  92
  93 static const u32 ibridge_interleave_list[] = {
  94         0x64, 0x6c, 0x74, 0x7c, 0x84,
  95         0x8c, 0x94, 0x9c, 0xa4, 0xac,
  96         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
  97         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
  98 };
  99
 100 struct interleave_pkg {
 101         unsigned char start;
 102         unsigned char end;
 103 };
 104
 105 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 106         { 0, 2 },
 107         { 3, 5 },
 108         { 8, 10 },
 109         { 11, 13 },
 110         { 16, 18 },
 111         { 19, 21 },
 112         { 24, 26 },
 113         { 27, 29 },
 114 };
 115
 116 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 117         { 0, 3 },
 118         { 4, 7 },
 119         { 8, 11 },
 120         { 12, 15 },
 121         { 16, 19 },
 122         { 20, 23 },
 123         { 24, 27 },
 124         { 28, 31 },
 125 };
 126
 127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 128                           int interleave)
 129 {
 130         return GET_BITFIELD(reg, table[interleave].start,
 131                             table[interleave].end);
 132 }
 133
 134 /* Devices 12 Function 7 */
 135
 136 #define TOLM            0x80
 137 #define TOHM            0x84
 138 #define HASWELL_TOLM    0xd0
 139 #define HASWELL_TOHM_0  0xd4
 140 #define HASWELL_TOHM_1  0xd8
 141
 142 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 143 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 144
 145 /* Device 13 Function 6 */
 146
 147 #define SAD_TARGET      0xf0
 148
 149 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 150
 151 #define SAD_CONTROL     0xf4
 152
 153 /* Device 14 function 0 */
 154
 155 static const u32 tad_dram_rule[] = {
 156         0x40, 0x44, 0x48, 0x4c,
 157         0x50, 0x54, 0x58, 0x5c,
 158         0x60, 0x64, 0x68, 0x6c,
 159 };
 160 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 161
 162 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 163 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 164 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 165 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 166 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 167 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 168 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 169
 170 /* Device 15, function 0 */
 171
 172 #define MCMTR                   0x7c
 173
 174 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 175 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 176 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 177
 178 /* Device 15, function 1 */
 179
 180 #define RASENABLES              0xac
 181 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 182
 183 /* Device 15, functions 2-5 */
 184
 185 static const int mtr_regs[] = {
 186         0x80, 0x84, 0x88,
 187 };
 188
 189 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 190 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 191 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 192 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 193 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 194
 195 static const u32 tad_ch_nilv_offset[] = {
 196         0x90, 0x94, 0x98, 0x9c,
 197         0xa0, 0xa4, 0xa8, 0xac,
 198         0xb0, 0xb4, 0xb8, 0xbc,
 199 };
 200 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 201 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 202
 203 static const u32 rir_way_limit[] = {
 204         0x108, 0x10c, 0x110, 0x114, 0x118,
 205 };
 206 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 207
 208 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 209 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 210
 211 #define MAX_RIR_WAY     8
 212
 213 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 214         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 215         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 216         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 217         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 218         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 219 };
 220
 221 #define RIR_RNK_TGT(reg)                GET_BITFIELD(reg, 16, 19)
 222 #define RIR_OFFSET(reg)         GET_BITFIELD(reg,  2, 14)
 223
 224 /* Device 16, functions 2-7 */
 225
 226 /*
 227  * FIXME: Implement the error count reads directly
 228  */
 229
 230 static const u32 correrrcnt[] = {
 231         0x104, 0x108, 0x10c, 0x110,
 232 };
 233
 234 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 235 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 236 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 237 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 238
 239 static const u32 correrrthrsld[] = {
 240         0x11c, 0x120, 0x124, 0x128,
 241 };
 242
 243 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 244 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 245
 246
 247 /* Device 17, function 0 */
 248
 249 #define SB_RANK_CFG_A           0x0328
 250
 251 #define IB_RANK_CFG_A           0x0320
 252
 253 /*
 254  * sbridge structs
 255  */
 256
 257 #define NUM_CHANNELS            8       /* 2MC per socket, four chan per MC */
 258 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 259 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 260
 261 enum type {
 262         SANDY_BRIDGE,
 263         IVY_BRIDGE,
 264         HASWELL,
 265         BROADWELL,
 266 };
 267
 268 struct sbridge_pvt;
 269 struct sbridge_info {
 270         enum type       type;
 271         u32             mcmtr;
 272         u32             rankcfgr;
 273         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 274         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 275         u64             (*rir_limit)(u32 reg);
 276         const u32       *dram_rule;
 277         const u32       *interleave_list;
 278         const struct interleave_pkg *interleave_pkg;
 279         u8              max_sad;
 280         u8              max_interleave;
 281         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 282         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 283         struct pci_dev  *pci_vtd;
 284 };
 285
 286 struct sbridge_channel {
 287         u32             ranks;
 288         u32             dimms;
 289 };
 290
 291 struct pci_id_descr {
 292         int                     dev_id;
 293         int                     optional;
 294 };
 295
 296 struct pci_id_table {
 297         const struct pci_id_descr       *descr;
 298         int                             n_devs;
 299 };
 300
 301 struct sbridge_dev {
 302         struct list_head        list;
 303         u8                      bus, mc;
 304         u8                      node_id, source_id;
 305         struct pci_dev          **pdev;
 306         int                     n_devs;
 307         struct mem_ctl_info     *mci;
 308 };
 309
 310 struct sbridge_pvt {
 311         struct pci_dev          *pci_ta, *pci_ddrio, *pci_ras;
 312         struct pci_dev          *pci_sad0, *pci_sad1;
 313         struct pci_dev          *pci_ha0, *pci_ha1;
 314         struct pci_dev          *pci_br0, *pci_br1;
 315         struct pci_dev          *pci_ha1_ta;
 316         struct pci_dev          *pci_tad[NUM_CHANNELS];
 317
 318         struct sbridge_dev      *sbridge_dev;
 319
 320         struct sbridge_info     info;
 321         struct sbridge_channel  channel[NUM_CHANNELS];
 322
 323         /* Memory type detection */
 324         bool                    is_mirrored, is_lockstep, is_close_pg;
 325
 326         /* Fifo double buffers */
 327         struct mce              mce_entry[MCE_LOG_LEN];
 328         struct mce              mce_outentry[MCE_LOG_LEN];
 329
 330         /* Fifo in/out counters */
 331         unsigned                mce_in, mce_out;
 332
 333         /* Count indicator to show errors not got */
 334         unsigned                mce_overrun;
 335
 336         /* Memory description */
 337         u64                     tolm, tohm;
 338 };
 339
 340 #define PCI_DESCR(device_id, opt)       \
 341         .dev_id = (device_id),          \
 342         .optional = opt
 343
 344 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 345                 /* Processor Home Agent */
 346         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0)     },
 347
 348                 /* Memory controller */
 349         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0)      },
 350         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0)     },
 351         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0)    },
 352         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0)    },
 353         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0)    },
 354         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0)    },
 355         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1)   },
 356
 357                 /* System Address Decoder */
 358         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0)        },
 359         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0)        },
 360
 361                 /* Broadcast Registers */
 362         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0)          },
 363 };
 364
 365 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
 366 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 367         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
 368         {0,}                    /* 0 terminated list. */
 369 };
 370
 371 /* This changes depending if 1HA or 2HA:
 372  * 1HA:
 373  *      0x0eb8 (17.0) is DDRIO0
 374  * 2HA:
 375  *      0x0ebc (17.4) is DDRIO0
 376  */
 377 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 378 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 379
 380 /* pci ids */
 381 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 382 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 383 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 384 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 385 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 386 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 387 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 388 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 389 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 390 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 391 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 392 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 393 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 394 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 395 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 396 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2        0x0e6c
 397 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3        0x0e6d
 398
 399 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 400                 /* Processor Home Agent */
 401         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0)             },
 402
 403                 /* Memory controller */
 404         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0)          },
 405         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0)         },
 406         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0)        },
 407         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0)        },
 408         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0)        },
 409         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0)        },
 410
 411                 /* System Address Decoder */
 412         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0)                 },
 413
 414                 /* Broadcast Registers */
 415         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1)                 },
 416         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0)                 },
 417
 418                 /* Optional, mode 2HA */
 419         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1)             },
 420 #if 0
 421         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1)  },
 422         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
 423 #endif
 424         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1)        },
 425         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1)        },
 426         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1)        },
 427         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1)        },
 428
 429         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1)      },
 430         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1)      },
 431 };
 432
 433 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 434         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
 435         {0,}                    /* 0 terminated list. */
 436 };
 437
 438 /* Haswell support */
 439 /* EN processor:
 440  *      - 1 IMC
 441  *      - 3 DDR3 channels, 2 DPC per channel
 442  * EP processor:
 443  *      - 1 or 2 IMC
 444  *      - 4 DDR4 channels, 3 DPC per channel
 445  * EP 4S processor:
 446  *      - 2 IMC
 447  *      - 4 DDR4 channels, 3 DPC per channel
 448  * EX processor:
 449  *      - 2 IMC
 450  *      - each IMC interfaces with a SMI 2 channel
 451  *      - each SMI channel interfaces with a scalable memory buffer
 452  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 453  */
 454 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
 455 #define HASWELL_HASYSDEFEATURE2 0x84
 456 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 457 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 458 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 459 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 460 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
 461 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 462 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
 463 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 464 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 465 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 466 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 467 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 468 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 469 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 470 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 471 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 472 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 473 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 474 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
 475 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
 476 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
 477 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 478         /* first item must be the HA */
 479         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0)             },
 480
 481         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0)        },
 482         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0)        },
 483
 484         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1)             },
 485
 486         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0)          },
 487         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0)     },
 488         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0)        },
 489         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0)        },
 490         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1)        },
 491         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1)        },
 492
 493         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1)          },
 494         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1)          },
 495         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1)          },
 496         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1)          },
 497
 498         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1)          },
 499         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1)     },
 500         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1)        },
 501         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1)        },
 502         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1)        },
 503         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1)        },
 504 };
 505
 506 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 507         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
 508         {0,}                    /* 0 terminated list. */
 509 };
 510
 511 /*
 512  * Broadwell support
 513  *
 514  * DE processor:
 515  *      - 1 IMC
 516  *      - 2 DDR3 channels, 2 DPC per channel
 517  * EP processor:
 518  *      - 1 or 2 IMC
 519  *      - 4 DDR4 channels, 3 DPC per channel
 520  * EP 4S processor:
 521  *      - 2 IMC
 522  *      - 4 DDR4 channels, 3 DPC per channel
 523  * EX processor:
 524  *      - 2 IMC
 525  *      - each IMC interfaces with a SMI 2 channel
 526  *      - each SMI channel interfaces with a scalable memory buffer
 527  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 528  */
 529 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
 530 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0   0x6fa0
 531 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1   0x6f60
 532 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA        0x6fa8
 533 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
 534 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA        0x6f68
 535 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
 536 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
 537 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
 538 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
 539 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
 540 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
 541 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
 542 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
 543 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
 544 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
 545 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
 546 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
 547
 548 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
 549         /* first item must be the HA */
 550         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0)           },
 551
 552         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0)      },
 553         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0)      },
 554
 555         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1)           },
 556
 557         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0)        },
 558         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0)   },
 559         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0)      },
 560         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0)      },
 561         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1)      },
 562         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1)      },
 563
 564         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1)        },
 565
 566         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1)        },
 567         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1)   },
 568         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1)      },
 569         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1)      },
 570         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1)      },
 571         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1)      },
 572 };
 573
 574 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
 575         PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
 576         {0,}                    /* 0 terminated list. */
 577 };
 578
 579 /*
 580  *      pci_device_id   table for which devices we are looking for
 581  */
 582 static const struct pci_device_id sbridge_pci_tbl[] = {
 583         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
 584         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
 585         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
 586         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
 587         {0,}                    /* 0 terminated list. */
 588 };
 589
 590
 591 /****************************************************************************
 592                         Ancillary status routines
 593  ****************************************************************************/
 594
 595 static inline int numrank(enum type type, u32 mtr)
 596 {
 597         int ranks = (1 << RANK_CNT_BITS(mtr));
 598         int max = 4;
 599
 600         if (type == HASWELL || type == BROADWELL)
 601                 max = 8;
 602
 603         if (ranks > max) {
 604                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 605                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 606                 return -EINVAL;
 607         }
 608
 609         return ranks;
 610 }
 611
 612 static inline int numrow(u32 mtr)
 613 {
 614         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 615
 616         if (rows < 13 || rows > 18) {
 617                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 618                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 619                 return -EINVAL;
 620         }
 621
 622         return 1 << rows;
 623 }
 624
 625 static inline int numcol(u32 mtr)
 626 {
 627         int cols = (COL_WIDTH_BITS(mtr) + 10);
 628
 629         if (cols > 12) {
 630                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 631                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 632                 return -EINVAL;
 633         }
 634
 635         return 1 << cols;
 636 }
 637
 638 static struct sbridge_dev *get_sbridge_dev(u8 bus)
 639 {
 640         struct sbridge_dev *sbridge_dev;
 641
 642         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
 643                 if (sbridge_dev->bus == bus)
 644                         return sbridge_dev;
 645         }
 646
 647         return NULL;
 648 }
 649
 650 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
 651                                            const struct pci_id_table *table)
 652 {
 653         struct sbridge_dev *sbridge_dev;
 654
 655         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 656         if (!sbridge_dev)
 657                 return NULL;
 658
 659         sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
 660                                    GFP_KERNEL);
 661         if (!sbridge_dev->pdev) {
 662                 kfree(sbridge_dev);
 663                 return NULL;
 664         }
 665
 666         sbridge_dev->bus = bus;
 667         sbridge_dev->n_devs = table->n_devs;
 668         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 669
 670         return sbridge_dev;
 671 }
 672
 673 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 674 {
 675         list_del(&sbridge_dev->list);
 676         kfree(sbridge_dev->pdev);
 677         kfree(sbridge_dev);
 678 }
 679
 680 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 681 {
 682         u32 reg;
 683
 684         /* Address range is 32:28 */
 685         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 686         return GET_TOLM(reg);
 687 }
 688
 689 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 690 {
 691         u32 reg;
 692
 693         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 694         return GET_TOHM(reg);
 695 }
 696
 697 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 698 {
 699         u32 reg;
 700
 701         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 702
 703         return GET_TOLM(reg);
 704 }
 705
 706 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 707 {
 708         u32 reg;
 709
 710         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 711
 712         return GET_TOHM(reg);
 713 }
 714
 715 static u64 rir_limit(u32 reg)
 716 {
 717         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 718 }
 719
 720 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 721 {
 722         u32 reg;
 723         enum mem_type mtype;
 724
 725         if (pvt->pci_ddrio) {
 726                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 727                                       &reg);
 728                 if (GET_BITFIELD(reg, 11, 11))
 729                         /* FIXME: Can also be LRDIMM */
 730                         mtype = MEM_RDDR3;
 731                 else
 732                         mtype = MEM_DDR3;
 733         } else
 734                 mtype = MEM_UNKNOWN;
 735
 736         return mtype;
 737 }
 738
 739 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 740 {
 741         u32 reg;
 742         bool registered = false;
 743         enum mem_type mtype = MEM_UNKNOWN;
 744
 745         if (!pvt->pci_ddrio)
 746                 goto out;
 747
 748         pci_read_config_dword(pvt->pci_ddrio,
 749                               HASWELL_DDRCRCLKCONTROLS, &reg);
 750         /* Is_Rdimm */
 751         if (GET_BITFIELD(reg, 16, 16))
 752                 registered = true;
 753
 754         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 755         if (GET_BITFIELD(reg, 14, 14)) {
 756                 if (registered)
 757                         mtype = MEM_RDDR4;
 758                 else
 759                         mtype = MEM_DDR4;
 760         } else {
 761                 if (registered)
 762                         mtype = MEM_RDDR3;
 763                 else
 764                         mtype = MEM_DDR3;
 765         }
 766
 767 out:
 768         return mtype;
 769 }
 770
 771 static u8 get_node_id(struct sbridge_pvt *pvt)
 772 {
 773         u32 reg;
 774         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 775         return GET_BITFIELD(reg, 0, 2);
 776 }
 777
 778 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 779 {
 780         u32 reg;
 781
 782         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 783         return GET_BITFIELD(reg, 0, 3);
 784 }
 785
 786 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
 787 {
 788         u32 reg;
 789
 790         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
 791         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
 792 }
 793
 794 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
 795 {
 796         u64 rc;
 797         u32 reg;
 798
 799         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
 800         rc = GET_BITFIELD(reg, 26, 31);
 801         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
 802         rc = ((reg << 6) | rc) << 26;
 803
 804         return rc | 0x1ffffff;
 805 }
 806
 807 static u64 haswell_rir_limit(u32 reg)
 808 {
 809         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
 810 }
 811
 812 static inline u8 sad_pkg_socket(u8 pkg)
 813 {
 814         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
 815         return ((pkg >> 3) << 2) | (pkg & 0x3);
 816 }
 817
 818 static inline u8 sad_pkg_ha(u8 pkg)
 819 {
 820         return (pkg >> 2) & 0x1;
 821 }
 822
 823 /****************************************************************************
 824                         Memory check routines
 825  ****************************************************************************/
 826 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
 827 {
 828         struct pci_dev *pdev = NULL;
 829
 830         do {
 831                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
 832                 if (pdev && pdev->bus->number == bus)
 833                         break;
 834         } while (pdev);
 835
 836         return pdev;
 837 }
 838
 839 /**
 840  * check_if_ecc_is_active() - Checks if ECC is active
 841  * @bus:        Device bus
 842  * @type:       Memory controller type
 843  * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
 844  *          disabled
 845  */
 846 static int check_if_ecc_is_active(const u8 bus, enum type type)
 847 {
 848         struct pci_dev *pdev = NULL;
 849         u32 mcmtr, id;
 850
 851         switch (type) {
 852         case IVY_BRIDGE:
 853                 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
 854                 break;
 855         case HASWELL:
 856                 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
 857                 break;
 858         case SANDY_BRIDGE:
 859                 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
 860                 break;
 861         case BROADWELL:
 862                 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
 863                 break;
 864         default:
 865                 return -ENODEV;
 866         }
 867
 868         pdev = get_pdev_same_bus(bus, id);
 869         if (!pdev) {
 870                 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
 871                                         "%04x:%04x! on bus %02d\n",
 872                                         PCI_VENDOR_ID_INTEL, id, bus);
 873                 return -ENODEV;
 874         }
 875
 876         pci_read_config_dword(pdev, MCMTR, &mcmtr);
 877         if (!IS_ECC_ENABLED(mcmtr)) {
 878                 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
 879                 return -ENODEV;
 880         }
 881         return 0;
 882 }
 883
 884 static int get_dimm_config(struct mem_ctl_info *mci)
 885 {
 886         struct sbridge_pvt *pvt = mci->pvt_info;
 887         struct dimm_info *dimm;
 888         unsigned i, j, banks, ranks, rows, cols, npages;
 889         u64 size;
 890         u32 reg;
 891         enum edac_type mode;
 892         enum mem_type mtype;
 893
 894         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
 895                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
 896         else
 897                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
 898
 899         pvt->sbridge_dev->source_id = SOURCE_ID(reg);
 900
 901         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
 902         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
 903                  pvt->sbridge_dev->mc,
 904                  pvt->sbridge_dev->node_id,
 905                  pvt->sbridge_dev->source_id);
 906
 907         pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
 908         if (IS_MIRROR_ENABLED(reg)) {
 909                 edac_dbg(0, "Memory mirror is enabled\n");
 910                 pvt->is_mirrored = true;
 911         } else {
 912                 edac_dbg(0, "Memory mirror is disabled\n");
 913                 pvt->is_mirrored = false;
 914         }
 915
 916         pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
 917         if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
 918                 edac_dbg(0, "Lockstep is enabled\n");
 919                 mode = EDAC_S8ECD8ED;
 920                 pvt->is_lockstep = true;
 921         } else {
 922                 edac_dbg(0, "Lockstep is disabled\n");
 923                 mode = EDAC_S4ECD4ED;
 924                 pvt->is_lockstep = false;
 925         }
 926         if (IS_CLOSE_PG(pvt->info.mcmtr)) {
 927                 edac_dbg(0, "address map is on closed page mode\n");
 928                 pvt->is_close_pg = true;
 929         } else {
 930                 edac_dbg(0, "address map is on open page mode\n");
 931                 pvt->is_close_pg = false;
 932         }
 933
 934         mtype = pvt->info.get_memory_type(pvt);
 935         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
 936                 edac_dbg(0, "Memory is registered\n");
 937         else if (mtype == MEM_UNKNOWN)
 938                 edac_dbg(0, "Cannot determine memory type\n");
 939         else
 940                 edac_dbg(0, "Memory is unregistered\n");
 941
 942         if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
 943                 banks = 16;
 944         else
 945                 banks = 8;
 946
 947         for (i = 0; i < NUM_CHANNELS; i++) {
 948                 u32 mtr;
 949
 950                 if (!pvt->pci_tad[i])
 951                         continue;
 952                 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
 953                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
 954                                        i, j, 0);
 955                         pci_read_config_dword(pvt->pci_tad[i],
 956                                               mtr_regs[j], &mtr);
 957                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
 958                         if (IS_DIMM_PRESENT(mtr)) {
 959                                 pvt->channel[i].dimms++;
 960
 961                                 ranks = numrank(pvt->info.type, mtr);
 962                                 rows = numrow(mtr);
 963                                 cols = numcol(mtr);
 964
 965                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
 966                                 npages = MiB_TO_PAGES(size);
 967
 968                                 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
 969                                          pvt->sbridge_dev->mc, i/4, i%4, j,
 970                                          size, npages,
 971                                          banks, ranks, rows, cols);
 972
 973                                 dimm->nr_pages = npages;
 974                                 dimm->grain = 32;
 975                                 switch (banks) {
 976                                 case 16:
 977                                         dimm->dtype = DEV_X16;
 978                                         break;
 979                                 case 8:
 980                                         dimm->dtype = DEV_X8;
 981                                         break;
 982                                 case 4:
 983                                         dimm->dtype = DEV_X4;
 984                                         break;
 985                                 }
 986                                 dimm->mtype = mtype;
 987                                 dimm->edac_mode = mode;
 988                                 snprintf(dimm->label, sizeof(dimm->label),
 989                                          "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
 990                                          pvt->sbridge_dev->source_id, i/4, i%4, j);
 991                         }
 992                 }
 993         }
 994
 995         return 0;
 996 }
 997
 998 static void get_memory_layout(const struct mem_ctl_info *mci)
 999 {
1000         struct sbridge_pvt *pvt = mci->pvt_info;
1001         int i, j, k, n_sads, n_tads, sad_interl;
1002         u32 reg;
1003         u64 limit, prv = 0;
1004         u64 tmp_mb;
1005         u32 gb, mb;
1006         u32 rir_way;
1007
1008         /*
1009          * Step 1) Get TOLM/TOHM ranges
1010          */
1011
1012         pvt->tolm = pvt->info.get_tolm(pvt);
1013         tmp_mb = (1 + pvt->tolm) >> 20;
1014
1015         gb = div_u64_rem(tmp_mb, 1024, &mb);
1016         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1017                 gb, (mb*1000)/1024, (u64)pvt->tolm);
1018
1019         /* Address range is already 45:25 */
1020         pvt->tohm = pvt->info.get_tohm(pvt);
1021         tmp_mb = (1 + pvt->tohm) >> 20;
1022
1023         gb = div_u64_rem(tmp_mb, 1024, &mb);
1024         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1025                 gb, (mb*1000)/1024, (u64)pvt->tohm);
1026
1027         /*
1028          * Step 2) Get SAD range and SAD Interleave list
1029          * TAD registers contain the interleave wayness. However, it
1030          * seems simpler to just discover it indirectly, with the
1031          * algorithm bellow.
1032          */
1033         prv = 0;
1034         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1035                 /* SAD_LIMIT Address range is 45:26 */
1036                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1037                                       &reg);
1038                 limit = SAD_LIMIT(reg);
1039
1040                 if (!DRAM_RULE_ENABLE(reg))
1041                         continue;
1042
1043                 if (limit <= prv)
1044                         break;
1045
1046                 tmp_mb = (limit + 1) >> 20;
1047                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1048                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1049                          n_sads,
1050                          get_dram_attr(reg),
1051                          gb, (mb*1000)/1024,
1052                          ((u64)tmp_mb) << 20L,
1053                          INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
1054                          reg);
1055                 prv = limit;
1056
1057                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1058                                       &reg);
1059                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1060                 for (j = 0; j < 8; j++) {
1061                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1062                         if (j > 0 && sad_interl == pkg)
1063                                 break;
1064
1065                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1066                                  n_sads, j, pkg);
1067                 }
1068         }
1069
1070         /*
1071          * Step 3) Get TAD range
1072          */
1073         prv = 0;
1074         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1075                 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1076                                       &reg);
1077                 limit = TAD_LIMIT(reg);
1078                 if (limit <= prv)
1079                         break;
1080                 tmp_mb = (limit + 1) >> 20;
1081
1082                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1083                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1084                          n_tads, gb, (mb*1000)/1024,
1085                          ((u64)tmp_mb) << 20L,
1086                          (u32)TAD_SOCK(reg),
1087                          (u32)TAD_CH(reg),
1088                          (u32)TAD_TGT0(reg),
1089                          (u32)TAD_TGT1(reg),
1090                          (u32)TAD_TGT2(reg),
1091                          (u32)TAD_TGT3(reg),
1092                          reg);
1093                 prv = limit;
1094         }
1095
1096         /*
1097          * Step 4) Get TAD offsets, per each channel
1098          */
1099         for (i = 0; i < NUM_CHANNELS; i++) {
1100                 if (!pvt->channel[i].dimms)
1101                         continue;
1102                 for (j = 0; j < n_tads; j++) {
1103                         pci_read_config_dword(pvt->pci_tad[i],
1104                                               tad_ch_nilv_offset[j],
1105                                               &reg);
1106                         tmp_mb = TAD_OFFSET(reg) >> 20;
1107                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1108                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1109                                  i, j,
1110                                  gb, (mb*1000)/1024,
1111                                  ((u64)tmp_mb) << 20L,
1112                                  reg);
1113                 }
1114         }
1115
1116         /*
1117          * Step 6) Get RIR Wayness/Limit, per each channel
1118          */
1119         for (i = 0; i < NUM_CHANNELS; i++) {
1120                 if (!pvt->channel[i].dimms)
1121                         continue;
1122                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1123                         pci_read_config_dword(pvt->pci_tad[i],
1124                                               rir_way_limit[j],
1125                                               &reg);
1126
1127                         if (!IS_RIR_VALID(reg))
1128                                 continue;
1129
1130                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1131                         rir_way = 1 << RIR_WAY(reg);
1132                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1133                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1134                                  i, j,
1135                                  gb, (mb*1000)/1024,
1136                                  ((u64)tmp_mb) << 20L,
1137                                  rir_way,
1138                                  reg);
1139
1140                         for (k = 0; k < rir_way; k++) {
1141                                 pci_read_config_dword(pvt->pci_tad[i],
1142                                                       rir_offset[j][k],
1143                                                       &reg);
1144                                 tmp_mb = RIR_OFFSET(reg) << 6;
1145
1146                                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1147                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1148                                          i, j, k,
1149                                          gb, (mb*1000)/1024,
1150                                          ((u64)tmp_mb) << 20L,
1151                                          (u32)RIR_RNK_TGT(reg),
1152                                          reg);
1153                         }
1154                 }
1155         }
1156 }
1157
1158 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1159 {
1160         struct sbridge_dev *sbridge_dev;
1161
1162         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1163                 if (sbridge_dev->node_id == node_id)
1164                         return sbridge_dev->mci;
1165         }
1166         return NULL;
1167 }
1168
1169 static int get_memory_error_data(struct mem_ctl_info *mci,
1170                                  u64 addr,
1171                                  u8 *socket, u8 *ha,
1172                                  long *channel_mask,
1173                                  u8 *rank,
1174                                  char **area_type, char *msg)
1175 {
1176         struct mem_ctl_info     *new_mci;
1177         struct sbridge_pvt *pvt = mci->pvt_info;
1178         struct pci_dev          *pci_ha;
1179         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1180         int                     sad_interl, idx, base_ch;
1181         int                     interleave_mode, shiftup = 0;
1182         unsigned                sad_interleave[pvt->info.max_interleave];
1183         u32                     reg, dram_rule;
1184         u8                      ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1185         u32                     tad_offset;
1186         u32                     rir_way;
1187         u32                     mb, gb;
1188         u64                     ch_addr, offset, limit = 0, prv = 0;
1189
1190
1191         /*
1192          * Step 0) Check if the address is at special memory ranges
1193          * The check bellow is probably enough to fill all cases where
1194          * the error is not inside a memory, except for the legacy
1195          * range (e. g. VGA addresses). It is unlikely, however, that the
1196          * memory controller would generate an error on that range.
1197          */
1198         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1199                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1200                 return -EINVAL;
1201         }
1202         if (addr >= (u64)pvt->tohm) {
1203                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1204                 return -EINVAL;
1205         }
1206
1207         /*
1208          * Step 1) Get socket
1209          */
1210         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1211                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1212                                       &reg);
1213
1214                 if (!DRAM_RULE_ENABLE(reg))
1215                         continue;
1216
1217                 limit = SAD_LIMIT(reg);
1218                 if (limit <= prv) {
1219                         sprintf(msg, "Can't discover the memory socket");
1220                         return -EINVAL;
1221                 }
1222                 if  (addr <= limit)
1223                         break;
1224                 prv = limit;
1225         }
1226         if (n_sads == pvt->info.max_sad) {
1227                 sprintf(msg, "Can't discover the memory socket");
1228                 return -EINVAL;
1229         }
1230         dram_rule = reg;
1231         *area_type = get_dram_attr(dram_rule);
1232         interleave_mode = INTERLEAVE_MODE(dram_rule);
1233
1234         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1235                               &reg);
1236
1237         if (pvt->info.type == SANDY_BRIDGE) {
1238                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1239                 for (sad_way = 0; sad_way < 8; sad_way++) {
1240                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1241                         if (sad_way > 0 && sad_interl == pkg)
1242                                 break;
1243                         sad_interleave[sad_way] = pkg;
1244                         edac_dbg(0, "SAD interleave #%d: %d\n",
1245                                  sad_way, sad_interleave[sad_way]);
1246                 }
1247                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1248                          pvt->sbridge_dev->mc,
1249                          n_sads,
1250                          addr,
1251                          limit,
1252                          sad_way + 7,
1253                          !interleave_mode ? "" : "XOR[18:16]");
1254                 if (interleave_mode)
1255                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1256                 else
1257                         idx = (addr >> 6) & 7;
1258                 switch (sad_way) {
1259                 case 1:
1260                         idx = 0;
1261                         break;
1262                 case 2:
1263                         idx = idx & 1;
1264                         break;
1265                 case 4:
1266                         idx = idx & 3;
1267                         break;
1268                 case 8:
1269                         break;
1270                 default:
1271                         sprintf(msg, "Can't discover socket interleave");
1272                         return -EINVAL;
1273                 }
1274                 *socket = sad_interleave[idx];
1275                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1276                          idx, sad_way, *socket);
1277         } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1278                 int bits, a7mode = A7MODE(dram_rule);
1279
1280                 if (a7mode) {
1281                         /* A7 mode swaps P9 with P6 */
1282                         bits = GET_BITFIELD(addr, 7, 8) << 1;
1283                         bits |= GET_BITFIELD(addr, 9, 9);
1284                 } else
1285                         bits = GET_BITFIELD(addr, 6, 8);
1286
1287                 if (interleave_mode == 0) {
1288                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
1289                         idx = GET_BITFIELD(addr, 16, 18);
1290                         idx ^= bits;
1291                 } else
1292                         idx = bits;
1293
1294                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1295                 *socket = sad_pkg_socket(pkg);
1296                 sad_ha = sad_pkg_ha(pkg);
1297                 if (sad_ha)
1298                         ch_add = 4;
1299
1300                 if (a7mode) {
1301                         /* MCChanShiftUpEnable */
1302                         pci_read_config_dword(pvt->pci_ha0,
1303                                               HASWELL_HASYSDEFEATURE2, &reg);
1304                         shiftup = GET_BITFIELD(reg, 22, 22);
1305                 }
1306
1307                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1308                          idx, *socket, sad_ha, shiftup);
1309         } else {
1310                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1311                 idx = (addr >> 6) & 7;
1312                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1313                 *socket = sad_pkg_socket(pkg);
1314                 sad_ha = sad_pkg_ha(pkg);
1315                 if (sad_ha)
1316                         ch_add = 4;
1317                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1318                          idx, *socket, sad_ha);
1319         }
1320
1321         *ha = sad_ha;
1322
1323         /*
1324          * Move to the proper node structure, in order to access the
1325          * right PCI registers
1326          */
1327         new_mci = get_mci_for_node_id(*socket);
1328         if (!new_mci) {
1329                 sprintf(msg, "Struct for socket #%u wasn't initialized",
1330                         *socket);
1331                 return -EINVAL;
1332         }
1333         mci = new_mci;
1334         pvt = mci->pvt_info;
1335
1336         /*
1337          * Step 2) Get memory channel
1338          */
1339         prv = 0;
1340         if (pvt->info.type == SANDY_BRIDGE)
1341                 pci_ha = pvt->pci_ha0;
1342         else {
1343                 if (sad_ha)
1344                         pci_ha = pvt->pci_ha1;
1345                 else
1346                         pci_ha = pvt->pci_ha0;
1347         }
1348         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1349                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
1350                 limit = TAD_LIMIT(reg);
1351                 if (limit <= prv) {
1352                         sprintf(msg, "Can't discover the memory channel");
1353                         return -EINVAL;
1354                 }
1355                 if  (addr <= limit)
1356                         break;
1357                 prv = limit;
1358         }
1359         if (n_tads == MAX_TAD) {
1360                 sprintf(msg, "Can't discover the memory channel");
1361                 return -EINVAL;
1362         }
1363
1364         ch_way = TAD_CH(reg) + 1;
1365         sck_way = TAD_SOCK(reg) + 1;
1366
1367         if (ch_way == 3)
1368                 idx = addr >> 6;
1369         else
1370                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1371         idx = idx % ch_way;
1372
1373         /*
1374          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1375          */
1376         switch (idx) {
1377         case 0:
1378                 base_ch = TAD_TGT0(reg);
1379                 break;
1380         case 1:
1381                 base_ch = TAD_TGT1(reg);
1382                 break;
1383         case 2:
1384                 base_ch = TAD_TGT2(reg);
1385                 break;
1386         case 3:
1387                 base_ch = TAD_TGT3(reg);
1388                 break;
1389         default:
1390                 sprintf(msg, "Can't discover the TAD target");
1391                 return -EINVAL;
1392         }
1393         *channel_mask = 1 << base_ch;
1394
1395         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1396                                 tad_ch_nilv_offset[n_tads],
1397                                 &tad_offset);
1398
1399         if (pvt->is_mirrored) {
1400                 *channel_mask |= 1 << ((base_ch + 2) % 4);
1401                 switch(ch_way) {
1402                 case 2:
1403                 case 4:
1404                         sck_xch = 1 << sck_way * (ch_way >> 1);
1405                         break;
1406                 default:
1407                         sprintf(msg, "Invalid mirror set. Can't decode addr");
1408                         return -EINVAL;
1409                 }
1410         } else
1411                 sck_xch = (1 << sck_way) * ch_way;
1412
1413         if (pvt->is_lockstep)
1414                 *channel_mask |= 1 << ((base_ch + 1) % 4);
1415
1416         offset = TAD_OFFSET(tad_offset);
1417
1418         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1419                  n_tads,
1420                  addr,
1421                  limit,
1422                  (u32)TAD_SOCK(reg),
1423                  ch_way,
1424                  offset,
1425                  idx,
1426                  base_ch,
1427                  *channel_mask);
1428
1429         /* Calculate channel address */
1430         /* Remove the TAD offset */
1431
1432         if (offset > addr) {
1433                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1434                         offset, addr);
1435                 return -EINVAL;
1436         }
1437         addr -= offset;
1438         /* Store the low bits [0:6] of the addr */
1439         ch_addr = addr & 0x7f;
1440         /* Remove socket wayness and remove 6 bits */
1441         addr >>= 6;
1442         addr = div_u64(addr, sck_xch);
1443 #if 0
1444         /* Divide by channel way */
1445         addr = addr / ch_way;
1446 #endif
1447         /* Recover the last 6 bits */
1448         ch_addr |= addr << 6;
1449
1450         /*
1451          * Step 3) Decode rank
1452          */
1453         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1454                 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1455                                       rir_way_limit[n_rir],
1456                                       &reg);
1457
1458                 if (!IS_RIR_VALID(reg))
1459                         continue;
1460
1461                 limit = pvt->info.rir_limit(reg);
1462                 gb = div_u64_rem(limit >> 20, 1024, &mb);
1463                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1464                          n_rir,
1465                          gb, (mb*1000)/1024,
1466                          limit,
1467                          1 << RIR_WAY(reg));
1468                 if  (ch_addr <= limit)
1469                         break;
1470         }
1471         if (n_rir == MAX_RIR_RANGES) {
1472                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1473                         ch_addr);
1474                 return -EINVAL;
1475         }
1476         rir_way = RIR_WAY(reg);
1477
1478         if (pvt->is_close_pg)
1479                 idx = (ch_addr >> 6);
1480         else
1481                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
1482         idx %= 1 << rir_way;
1483
1484         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1485                               rir_offset[n_rir][idx],
1486                               &reg);
1487         *rank = RIR_RNK_TGT(reg);
1488
1489         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1490                  n_rir,
1491                  ch_addr,
1492                  limit,
1493                  rir_way,
1494                  idx);
1495
1496         return 0;
1497 }
1498
1499 /****************************************************************************
1500         Device initialization routines: put/get, init/exit
1501  ****************************************************************************/
1502
1503 /*
1504  *      sbridge_put_all_devices 'put' all the devices that we have
1505  *                              reserved via 'get'
1506  */
1507 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1508 {
1509         int i;
1510
1511         edac_dbg(0, "\n");
1512         for (i = 0; i < sbridge_dev->n_devs; i++) {
1513                 struct pci_dev *pdev = sbridge_dev->pdev[i];
1514                 if (!pdev)
1515                         continue;
1516                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1517                          pdev->bus->number,
1518                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1519                 pci_dev_put(pdev);
1520         }
1521 }
1522
1523 static void sbridge_put_all_devices(void)
1524 {
1525         struct sbridge_dev *sbridge_dev, *tmp;
1526
1527         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1528                 sbridge_put_devices(sbridge_dev);
1529                 free_sbridge_dev(sbridge_dev);
1530         }
1531 }
1532
1533 static int sbridge_get_onedevice(struct pci_dev **prev,
1534                                  u8 *num_mc,
1535                                  const struct pci_id_table *table,
1536                                  const unsigned devno)
1537 {
1538         struct sbridge_dev *sbridge_dev;
1539         const struct pci_id_descr *dev_descr = &table->descr[devno];
1540         struct pci_dev *pdev = NULL;
1541         u8 bus = 0;
1542
1543         sbridge_printk(KERN_DEBUG,
1544                 "Seeking for: PCI ID %04x:%04x\n",
1545                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1546
1547         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1548                               dev_descr->dev_id, *prev);
1549
1550         if (!pdev) {
1551                 if (*prev) {
1552                         *prev = pdev;
1553                         return 0;
1554                 }
1555
1556                 if (dev_descr->optional)
1557                         return 0;
1558
1559                 /* if the HA wasn't found */
1560                 if (devno == 0)
1561                         return -ENODEV;
1562
1563                 sbridge_printk(KERN_INFO,
1564                         "Device not found: %04x:%04x\n",
1565                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1566
1567                 /* End of list, leave */
1568                 return -ENODEV;
1569         }
1570         bus = pdev->bus->number;
1571
1572         sbridge_dev = get_sbridge_dev(bus);
1573         if (!sbridge_dev) {
1574                 sbridge_dev = alloc_sbridge_dev(bus, table);
1575                 if (!sbridge_dev) {
1576                         pci_dev_put(pdev);
1577                         return -ENOMEM;
1578                 }
1579                 (*num_mc)++;
1580         }
1581
1582         if (sbridge_dev->pdev[devno]) {
1583                 sbridge_printk(KERN_ERR,
1584                         "Duplicated device for %04x:%04x\n",
1585                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1586                 pci_dev_put(pdev);
1587                 return -ENODEV;
1588         }
1589
1590         sbridge_dev->pdev[devno] = pdev;
1591
1592         /* Be sure that the device is enabled */
1593         if (unlikely(pci_enable_device(pdev) < 0)) {
1594                 sbridge_printk(KERN_ERR,
1595                         "Couldn't enable %04x:%04x\n",
1596                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1597                 return -ENODEV;
1598         }
1599
1600         edac_dbg(0, "Detected %04x:%04x\n",
1601                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1602
1603         /*
1604          * As stated on drivers/pci/search.c, the reference count for
1605          * @from is always decremented if it is not %NULL. So, as we need
1606          * to get all devices up to null, we need to do a get for the device
1607          */
1608         pci_dev_get(pdev);
1609
1610         *prev = pdev;
1611
1612         return 0;
1613 }
1614
1615 /*
1616  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1617  *                           devices we want to reference for this driver.
1618  * @num_mc: pointer to the memory controllers count, to be incremented in case
1619  *          of success.
1620  * @table: model specific table
1621  *
1622  * returns 0 in case of success or error code
1623  */
1624 static int sbridge_get_all_devices(u8 *num_mc,
1625                                    const struct pci_id_table *table)
1626 {
1627         int i, rc;
1628         struct pci_dev *pdev = NULL;
1629
1630         while (table && table->descr) {
1631                 for (i = 0; i < table->n_devs; i++) {
1632                         pdev = NULL;
1633                         do {
1634                                 rc = sbridge_get_onedevice(&pdev, num_mc,
1635                                                            table, i);
1636                                 if (rc < 0) {
1637                                         if (i == 0) {
1638                                                 i = table->n_devs;
1639                                                 break;
1640                                         }
1641                                         sbridge_put_all_devices();
1642                                         return -ENODEV;
1643                                 }
1644                         } while (pdev);
1645                 }
1646                 table++;
1647         }
1648
1649         return 0;
1650 }
1651
1652 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1653                                  struct sbridge_dev *sbridge_dev)
1654 {
1655         struct sbridge_pvt *pvt = mci->pvt_info;
1656         struct pci_dev *pdev;
1657         int i;
1658
1659         for (i = 0; i < sbridge_dev->n_devs; i++) {
1660                 pdev = sbridge_dev->pdev[i];
1661                 if (!pdev)
1662                         continue;
1663
1664                 switch (pdev->device) {
1665                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1666                         pvt->pci_sad0 = pdev;
1667                         break;
1668                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1669                         pvt->pci_sad1 = pdev;
1670                         break;
1671                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1672                         pvt->pci_br0 = pdev;
1673                         break;
1674                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1675                         pvt->pci_ha0 = pdev;
1676                         break;
1677                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1678                         pvt->pci_ta = pdev;
1679                         break;
1680                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1681                         pvt->pci_ras = pdev;
1682                         break;
1683                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1684                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1685                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1686                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1687                 {
1688                         int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1689                         pvt->pci_tad[id] = pdev;
1690                 }
1691                         break;
1692                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1693                         pvt->pci_ddrio = pdev;
1694                         break;
1695                 default:
1696                         goto error;
1697                 }
1698
1699                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1700                          pdev->vendor, pdev->device,
1701                          sbridge_dev->bus,
1702                          pdev);
1703         }
1704
1705         /* Check if everything were registered */
1706         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1707             !pvt-> pci_tad || !pvt->pci_ras  || !pvt->pci_ta)
1708                 goto enodev;
1709
1710         for (i = 0; i < NUM_CHANNELS; i++) {
1711                 if (!pvt->pci_tad[i])
1712                         goto enodev;
1713         }
1714         return 0;
1715
1716 enodev:
1717         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1718         return -ENODEV;
1719
1720 error:
1721         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1722                        PCI_VENDOR_ID_INTEL, pdev->device);
1723         return -EINVAL;
1724 }
1725
1726 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1727                                  struct sbridge_dev *sbridge_dev)
1728 {
1729         struct sbridge_pvt *pvt = mci->pvt_info;
1730         struct pci_dev *pdev;
1731         u8 saw_chan_mask = 0;
1732         int i;
1733
1734         for (i = 0; i < sbridge_dev->n_devs; i++) {
1735                 pdev = sbridge_dev->pdev[i];
1736                 if (!pdev)
1737                         continue;
1738
1739                 switch (pdev->device) {
1740                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1741                         pvt->pci_ha0 = pdev;
1742                         break;
1743                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1744                         pvt->pci_ta = pdev;
1745                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1746                         pvt->pci_ras = pdev;
1747                         break;
1748                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1749                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1750                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1751                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1752                 {
1753                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1754                         pvt->pci_tad[id] = pdev;
1755                         saw_chan_mask |= 1 << id;
1756                 }
1757                         break;
1758                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1759                         pvt->pci_ddrio = pdev;
1760                         break;
1761                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1762                         pvt->pci_ddrio = pdev;
1763                         break;
1764                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1765                         pvt->pci_sad0 = pdev;
1766                         break;
1767                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1768                         pvt->pci_br0 = pdev;
1769                         break;
1770                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1771                         pvt->pci_br1 = pdev;
1772                         break;
1773                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1774                         pvt->pci_ha1 = pdev;
1775                         break;
1776                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1777                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1778                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
1779                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
1780                 {
1781                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
1782                         pvt->pci_tad[id] = pdev;
1783                         saw_chan_mask |= 1 << id;
1784                 }
1785                         break;
1786                 default:
1787                         goto error;
1788                 }
1789
1790                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1791                          sbridge_dev->bus,
1792                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1793                          pdev);
1794         }
1795
1796         /* Check if everything were registered */
1797         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1798             !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras  ||
1799             !pvt->pci_ta)
1800                 goto enodev;
1801
1802         if (saw_chan_mask != 0x0f && /* -EN */
1803             saw_chan_mask != 0x33 && /* -EP */
1804             saw_chan_mask != 0xff)   /* -EX */
1805                 goto enodev;
1806         return 0;
1807
1808 enodev:
1809         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1810         return -ENODEV;
1811
1812 error:
1813         sbridge_printk(KERN_ERR,
1814                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1815                         pdev->device);
1816         return -EINVAL;
1817 }
1818
1819 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1820                                  struct sbridge_dev *sbridge_dev)
1821 {
1822         struct sbridge_pvt *pvt = mci->pvt_info;
1823         struct pci_dev *pdev;
1824         u8 saw_chan_mask = 0;
1825         int i;
1826
1827         /* there's only one device per system; not tied to any bus */
1828         if (pvt->info.pci_vtd == NULL)
1829                 /* result will be checked later */
1830                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1831                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1832                                                    NULL);
1833
1834         for (i = 0; i < sbridge_dev->n_devs; i++) {
1835                 pdev = sbridge_dev->pdev[i];
1836                 if (!pdev)
1837                         continue;
1838
1839                 switch (pdev->device) {
1840                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1841                         pvt->pci_sad0 = pdev;
1842                         break;
1843                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1844                         pvt->pci_sad1 = pdev;
1845                         break;
1846                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1847                         pvt->pci_ha0 = pdev;
1848                         break;
1849                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1850                         pvt->pci_ta = pdev;
1851                         break;
1852                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1853                         pvt->pci_ras = pdev;
1854                         break;
1855                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1856                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1857                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1858                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1859                 {
1860                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
1861
1862                         pvt->pci_tad[id] = pdev;
1863                         saw_chan_mask |= 1 << id;
1864                 }
1865                         break;
1866                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1867                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1868                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
1869                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
1870                 {
1871                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
1872
1873                         pvt->pci_tad[id] = pdev;
1874                         saw_chan_mask |= 1 << id;
1875                 }
1876                         break;
1877                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1878                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
1879                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
1880                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
1881                         if (!pvt->pci_ddrio)
1882                                 pvt->pci_ddrio = pdev;
1883                         break;
1884                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1885                         pvt->pci_ha1 = pdev;
1886                         break;
1887                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1888                         pvt->pci_ha1_ta = pdev;
1889                         break;
1890                 default:
1891                         break;
1892                 }
1893
1894                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1895                          sbridge_dev->bus,
1896                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1897                          pdev);
1898         }
1899
1900         /* Check if everything were registered */
1901         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1902             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
1903                 goto enodev;
1904
1905         if (saw_chan_mask != 0x0f && /* -EN */
1906             saw_chan_mask != 0x33 && /* -EP */
1907             saw_chan_mask != 0xff)   /* -EX */
1908                 goto enodev;
1909         return 0;
1910
1911 enodev:
1912         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1913         return -ENODEV;
1914 }
1915
1916 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
1917                                  struct sbridge_dev *sbridge_dev)
1918 {
1919         struct sbridge_pvt *pvt = mci->pvt_info;
1920         struct pci_dev *pdev;
1921         u8 saw_chan_mask = 0;
1922         int i;
1923
1924         /* there's only one device per system; not tied to any bus */
1925         if (pvt->info.pci_vtd == NULL)
1926                 /* result will be checked later */
1927                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1928                                                    PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
1929                                                    NULL);
1930
1931         for (i = 0; i < sbridge_dev->n_devs; i++) {
1932                 pdev = sbridge_dev->pdev[i];
1933                 if (!pdev)
1934                         continue;
1935
1936                 switch (pdev->device) {
1937                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
1938                         pvt->pci_sad0 = pdev;
1939                         break;
1940                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
1941                         pvt->pci_sad1 = pdev;
1942                         break;
1943                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
1944                         pvt->pci_ha0 = pdev;
1945                         break;
1946                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
1947                         pvt->pci_ta = pdev;
1948                         break;
1949                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
1950                         pvt->pci_ras = pdev;
1951                         break;
1952                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
1953                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
1954                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
1955                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
1956                 {
1957                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
1958                         pvt->pci_tad[id] = pdev;
1959                         saw_chan_mask |= 1 << id;
1960                 }
1961                         break;
1962                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
1963                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
1964                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
1965                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
1966                 {
1967                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
1968                         pvt->pci_tad[id] = pdev;
1969                         saw_chan_mask |= 1 << id;
1970                 }
1971                         break;
1972                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
1973                         pvt->pci_ddrio = pdev;
1974                         break;
1975                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
1976                         pvt->pci_ha1 = pdev;
1977                         break;
1978                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
1979                         pvt->pci_ha1_ta = pdev;
1980                         break;
1981                 default:
1982                         break;
1983                 }
1984
1985                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1986                          sbridge_dev->bus,
1987                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1988                          pdev);
1989         }
1990
1991         /* Check if everything were registered */
1992         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1993             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
1994                 goto enodev;
1995
1996         if (saw_chan_mask != 0x0f && /* -EN */
1997             saw_chan_mask != 0x33 && /* -EP */
1998             saw_chan_mask != 0xff)   /* -EX */
1999                 goto enodev;
2000         return 0;
2001
2002 enodev:
2003         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2004         return -ENODEV;
2005 }
2006
2007 /****************************************************************************
2008                         Error check routines
2009  ****************************************************************************/
2010
2011 /*
2012  * While Sandy Bridge has error count registers, SMI BIOS read values from
2013  * and resets the counters. So, they are not reliable for the OS to read
2014  * from them. So, we have no option but to just trust on whatever MCE is
2015  * telling us about the errors.
2016  */
2017 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2018                                     const struct mce *m)
2019 {
2020         struct mem_ctl_info *new_mci;
2021         struct sbridge_pvt *pvt = mci->pvt_info;
2022         enum hw_event_mc_err_type tp_event;
2023         char *type, *optype, msg[256];
2024         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2025         bool overflow = GET_BITFIELD(m->status, 62, 62);
2026         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2027         bool recoverable;
2028         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2029         u32 mscod = GET_BITFIELD(m->status, 16, 31);
2030         u32 errcode = GET_BITFIELD(m->status, 0, 15);
2031         u32 channel = GET_BITFIELD(m->status, 0, 3);
2032         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2033         long channel_mask, first_channel;
2034         u8  rank, socket, ha;
2035         int rc, dimm;
2036         char *area_type = NULL;
2037
2038         if (pvt->info.type != SANDY_BRIDGE)
2039                 recoverable = true;
2040         else
2041                 recoverable = GET_BITFIELD(m->status, 56, 56);
2042
2043         if (uncorrected_error) {
2044                 if (ripv) {
2045                         type = "FATAL";
2046                         tp_event = HW_EVENT_ERR_FATAL;
2047                 } else {
2048                         type = "NON_FATAL";
2049                         tp_event = HW_EVENT_ERR_UNCORRECTED;
2050                 }
2051         } else {
2052                 type = "CORRECTED";
2053                 tp_event = HW_EVENT_ERR_CORRECTED;
2054         }
2055
2056         /*
2057          * According with Table 15-9 of the Intel Architecture spec vol 3A,
2058          * memory errors should fit in this mask:
2059          *      000f 0000 1mmm cccc (binary)
2060          * where:
2061          *      f = Correction Report Filtering Bit. If 1, subsequent errors
2062          *          won't be shown
2063          *      mmm = error type
2064          *      cccc = channel
2065          * If the mask doesn't match, report an error to the parsing logic
2066          */
2067         if (! ((errcode & 0xef80) == 0x80)) {
2068                 optype = "Can't parse: it is not a mem";
2069         } else {
2070                 switch (optypenum) {
2071                 case 0:
2072                         optype = "generic undef request error";
2073                         break;
2074                 case 1:
2075                         optype = "memory read error";
2076                         break;
2077                 case 2:
2078                         optype = "memory write error";
2079                         break;
2080                 case 3:
2081                         optype = "addr/cmd error";
2082                         break;
2083                 case 4:
2084                         optype = "memory scrubbing error";
2085                         break;
2086                 default:
2087                         optype = "reserved";
2088                         break;
2089                 }
2090         }
2091
2092         /* Only decode errors with an valid address (ADDRV) */
2093         if (!GET_BITFIELD(m->status, 58, 58))
2094                 return;
2095
2096         rc = get_memory_error_data(mci, m->addr, &socket, &ha,
2097                                    &channel_mask, &rank, &area_type, msg);
2098         if (rc < 0)
2099                 goto err_parsing;
2100         new_mci = get_mci_for_node_id(socket);
2101         if (!new_mci) {
2102                 strcpy(msg, "Error: socket got corrupted!");
2103                 goto err_parsing;
2104         }
2105         mci = new_mci;
2106         pvt = mci->pvt_info;
2107
2108         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2109
2110         if (rank < 4)
2111                 dimm = 0;
2112         else if (rank < 8)
2113                 dimm = 1;
2114         else
2115                 dimm = 2;
2116
2117
2118         /*
2119          * FIXME: On some memory configurations (mirror, lockstep), the
2120          * Memory Controller can't point the error to a single DIMM. The
2121          * EDAC core should be handling the channel mask, in order to point
2122          * to the group of dimm's where the error may be happening.
2123          */
2124         if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
2125                 channel = first_channel;
2126
2127         snprintf(msg, sizeof(msg),
2128                  "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
2129                  overflow ? " OVERFLOW" : "",
2130                  (uncorrected_error && recoverable) ? " recoverable" : "",
2131                  area_type,
2132                  mscod, errcode,
2133                  socket, ha,
2134                  channel_mask,
2135                  rank);
2136
2137         edac_dbg(0, "%s\n", msg);
2138
2139         /* FIXME: need support for channel mask */
2140
2141         if (channel == CHANNEL_UNSPECIFIED)
2142                 channel = -1;
2143
2144         /* Call the helper to output message */
2145         edac_mc_handle_error(tp_event, mci, core_err_cnt,
2146                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2147                              4*ha+channel, dimm, -1,
2148                              optype, msg);
2149         return;
2150 err_parsing:
2151         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
2152                              -1, -1, -1,
2153                              msg, "");
2154
2155 }
2156
2157 /*
2158  *      sbridge_check_error     Retrieve and process errors reported by the
2159  *                              hardware. Called by the Core module.
2160  */
2161 static void sbridge_check_error(struct mem_ctl_info *mci)
2162 {
2163         struct sbridge_pvt *pvt = mci->pvt_info;
2164         int i;
2165         unsigned count = 0;
2166         struct mce *m;
2167
2168         /*
2169          * MCE first step: Copy all mce errors into a temporary buffer
2170          * We use a double buffering here, to reduce the risk of
2171          * loosing an error.
2172          */
2173         smp_rmb();
2174         count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2175                 % MCE_LOG_LEN;
2176         if (!count)
2177                 return;
2178
2179         m = pvt->mce_outentry;
2180         if (pvt->mce_in + count > MCE_LOG_LEN) {
2181                 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2182
2183                 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2184                 smp_wmb();
2185                 pvt->mce_in = 0;
2186                 count -= l;
2187                 m += l;
2188         }
2189         memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2190         smp_wmb();
2191         pvt->mce_in += count;
2192
2193         smp_rmb();
2194         if (pvt->mce_overrun) {
2195                 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2196                               pvt->mce_overrun);
2197                 smp_wmb();
2198                 pvt->mce_overrun = 0;
2199         }
2200
2201         /*
2202          * MCE second step: parse errors and display
2203          */
2204         for (i = 0; i < count; i++)
2205                 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2206 }
2207
2208 /*
2209  * sbridge_mce_check_error      Replicates mcelog routine to get errors
2210  *                              This routine simply queues mcelog errors, and
2211  *                              return. The error itself should be handled later
2212  *                              by sbridge_check_error.
2213  * WARNING: As this routine should be called at NMI time, extra care should
2214  * be taken to avoid deadlocks, and to be as fast as possible.
2215  */
2216 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2217                                    void *data)
2218 {
2219         struct mce *mce = (struct mce *)data;
2220         struct mem_ctl_info *mci;
2221         struct sbridge_pvt *pvt;
2222         char *type;
2223
2224         if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2225                 return NOTIFY_DONE;
2226
2227         mci = get_mci_for_node_id(mce->socketid);
2228         if (!mci)
2229                 return NOTIFY_BAD;
2230         pvt = mci->pvt_info;
2231
2232         /*
2233          * Just let mcelog handle it if the error is
2234          * outside the memory controller. A memory error
2235          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2236          * bit 12 has an special meaning.
2237          */
2238         if ((mce->status & 0xefff) >> 7 != 1)
2239                 return NOTIFY_DONE;
2240
2241         if (mce->mcgstatus & MCG_STATUS_MCIP)
2242                 type = "Exception";
2243         else
2244                 type = "Event";
2245
2246         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2247
2248         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2249                           "Bank %d: %016Lx\n", mce->extcpu, type,
2250                           mce->mcgstatus, mce->bank, mce->status);
2251         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2252         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2253         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2254
2255         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2256                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2257                           mce->time, mce->socketid, mce->apicid);
2258
2259         smp_rmb();
2260         if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2261                 smp_wmb();
2262                 pvt->mce_overrun++;
2263                 return NOTIFY_DONE;
2264         }
2265
2266         /* Copy memory error at the ringbuffer */
2267         memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2268         smp_wmb();
2269         pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2270
2271         /* Handle fatal errors immediately */
2272         if (mce->mcgstatus & 1)
2273                 sbridge_check_error(mci);
2274
2275         /* Advice mcelog that the error were handled */
2276         return NOTIFY_STOP;
2277 }
2278
2279 static struct notifier_block sbridge_mce_dec = {
2280         .notifier_call      = sbridge_mce_check_error,
2281 };
2282
2283 /****************************************************************************
2284                         EDAC register/unregister logic
2285  ****************************************************************************/
2286
2287 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2288 {
2289         struct mem_ctl_info *mci = sbridge_dev->mci;
2290         struct sbridge_pvt *pvt;
2291
2292         if (unlikely(!mci || !mci->pvt_info)) {
2293                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2294
2295                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2296                 return;
2297         }
2298
2299         pvt = mci->pvt_info;
2300
2301         edac_dbg(0, "MC: mci = %p, dev = %p\n",
2302                  mci, &sbridge_dev->pdev[0]->dev);
2303
2304         /* Remove MC sysfs nodes */
2305         edac_mc_del_mc(mci->pdev);
2306
2307         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2308         kfree(mci->ctl_name);
2309         edac_mc_free(mci);
2310         sbridge_dev->mci = NULL;
2311 }
2312
2313 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2314 {
2315         struct mem_ctl_info *mci;
2316         struct edac_mc_layer layers[2];
2317         struct sbridge_pvt *pvt;
2318         struct pci_dev *pdev = sbridge_dev->pdev[0];
2319         int rc;
2320
2321         /* Check the number of active and not disabled channels */
2322         rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2323         if (unlikely(rc < 0))
2324                 return rc;
2325
2326         /* allocate a new MC control structure */
2327         layers[0].type = EDAC_MC_LAYER_CHANNEL;
2328         layers[0].size = NUM_CHANNELS;
2329         layers[0].is_virt_csrow = false;
2330         layers[1].type = EDAC_MC_LAYER_SLOT;
2331         layers[1].size = MAX_DIMMS;
2332         layers[1].is_virt_csrow = true;
2333         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2334                             sizeof(*pvt));
2335
2336         if (unlikely(!mci))
2337                 return -ENOMEM;
2338
2339         edac_dbg(0, "MC: mci = %p, dev = %p\n",
2340                  mci, &pdev->dev);
2341
2342         pvt = mci->pvt_info;
2343         memset(pvt, 0, sizeof(*pvt));
2344
2345         /* Associate sbridge_dev and mci for future usage */
2346         pvt->sbridge_dev = sbridge_dev;
2347         sbridge_dev->mci = mci;
2348
2349         mci->mtype_cap = MEM_FLAG_DDR3;
2350         mci->edac_ctl_cap = EDAC_FLAG_NONE;
2351         mci->edac_cap = EDAC_FLAG_NONE;
2352         mci->mod_name = "sbridge_edac.c";
2353         mci->mod_ver = SBRIDGE_REVISION;
2354         mci->dev_name = pci_name(pdev);
2355         mci->ctl_page_to_phys = NULL;
2356
2357         /* Set the function pointer to an actual operation function */
2358         mci->edac_check = sbridge_check_error;
2359
2360         pvt->info.type = type;
2361         switch (type) {
2362         case IVY_BRIDGE:
2363                 pvt->info.rankcfgr = IB_RANK_CFG_A;
2364                 pvt->info.get_tolm = ibridge_get_tolm;
2365                 pvt->info.get_tohm = ibridge_get_tohm;
2366                 pvt->info.dram_rule = ibridge_dram_rule;
2367                 pvt->info.get_memory_type = get_memory_type;
2368                 pvt->info.get_node_id = get_node_id;
2369                 pvt->info.rir_limit = rir_limit;
2370                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2371                 pvt->info.interleave_list = ibridge_interleave_list;
2372                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2373                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2374                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2375
2376                 /* Store pci devices at mci for faster access */
2377                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2378                 if (unlikely(rc < 0))
2379                         goto fail0;
2380                 break;
2381         case SANDY_BRIDGE:
2382                 pvt->info.rankcfgr = SB_RANK_CFG_A;
2383                 pvt->info.get_tolm = sbridge_get_tolm;
2384                 pvt->info.get_tohm = sbridge_get_tohm;
2385                 pvt->info.dram_rule = sbridge_dram_rule;
2386                 pvt->info.get_memory_type = get_memory_type;
2387                 pvt->info.get_node_id = get_node_id;
2388                 pvt->info.rir_limit = rir_limit;
2389                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2390                 pvt->info.interleave_list = sbridge_interleave_list;
2391                 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2392                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2393                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2394
2395                 /* Store pci devices at mci for faster access */
2396                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2397                 if (unlikely(rc < 0))
2398                         goto fail0;
2399                 break;
2400         case HASWELL:
2401                 /* rankcfgr isn't used */
2402                 pvt->info.get_tolm = haswell_get_tolm;
2403                 pvt->info.get_tohm = haswell_get_tohm;
2404                 pvt->info.dram_rule = ibridge_dram_rule;
2405                 pvt->info.get_memory_type = haswell_get_memory_type;
2406                 pvt->info.get_node_id = haswell_get_node_id;
2407                 pvt->info.rir_limit = haswell_rir_limit;
2408                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2409                 pvt->info.interleave_list = ibridge_interleave_list;
2410                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2411                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2412                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2413
2414                 /* Store pci devices at mci for faster access */
2415                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2416                 if (unlikely(rc < 0))
2417                         goto fail0;
2418                 break;
2419         case BROADWELL:
2420                 /* rankcfgr isn't used */
2421                 pvt->info.get_tolm = haswell_get_tolm;
2422                 pvt->info.get_tohm = haswell_get_tohm;
2423                 pvt->info.dram_rule = ibridge_dram_rule;
2424                 pvt->info.get_memory_type = haswell_get_memory_type;
2425                 pvt->info.get_node_id = haswell_get_node_id;
2426                 pvt->info.rir_limit = haswell_rir_limit;
2427                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2428                 pvt->info.interleave_list = ibridge_interleave_list;
2429                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2430                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2431                 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
2432
2433                 /* Store pci devices at mci for faster access */
2434                 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
2435                 if (unlikely(rc < 0))
2436                         goto fail0;
2437                 break;
2438         }
2439
2440         /* Get dimm basic config and the memory layout */
2441         get_dimm_config(mci);
2442         get_memory_layout(mci);
2443
2444         /* record ptr to the generic device */
2445         mci->pdev = &pdev->dev;
2446
2447         /* add this new MC control structure to EDAC's list of MCs */
2448         if (unlikely(edac_mc_add_mc(mci))) {
2449                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2450                 rc = -EINVAL;
2451                 goto fail0;
2452         }
2453
2454         return 0;
2455
2456 fail0:
2457         kfree(mci->ctl_name);
2458         edac_mc_free(mci);
2459         sbridge_dev->mci = NULL;
2460         return rc;
2461 }
2462
2463 /*
2464  *      sbridge_probe   Probe for ONE instance of device to see if it is
2465  *                      present.
2466  *      return:
2467  *              0 for FOUND a device
2468  *              < 0 for error code
2469  */
2470
2471 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2472 {
2473         int rc = -ENODEV;
2474         u8 mc, num_mc = 0;
2475         struct sbridge_dev *sbridge_dev;
2476         enum type type = SANDY_BRIDGE;
2477
2478         /* get the pci devices we want to reserve for our use */
2479         mutex_lock(&sbridge_edac_lock);
2480
2481         /*
2482          * All memory controllers are allocated at the first pass.
2483          */
2484         if (unlikely(probed >= 1)) {
2485                 mutex_unlock(&sbridge_edac_lock);
2486                 return -ENODEV;
2487         }
2488         probed++;
2489
2490         switch (pdev->device) {
2491         case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2492                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2493                 type = IVY_BRIDGE;
2494                 break;
2495         case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2496                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2497                 type = SANDY_BRIDGE;
2498                 break;
2499         case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2500                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2501                 type = HASWELL;
2502                 break;
2503         case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2504                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
2505                 type = BROADWELL;
2506                 break;
2507         }
2508         if (unlikely(rc < 0)) {
2509                 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
2510                 goto fail0;
2511         }
2512
2513         mc = 0;
2514
2515         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2516                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2517                          mc, mc + 1, num_mc);
2518
2519                 sbridge_dev->mc = mc++;
2520                 rc = sbridge_register_mci(sbridge_dev, type);
2521                 if (unlikely(rc < 0))
2522                         goto fail1;
2523         }
2524
2525         sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
2526
2527         mutex_unlock(&sbridge_edac_lock);
2528         return 0;
2529
2530 fail1:
2531         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2532                 sbridge_unregister_mci(sbridge_dev);
2533
2534         sbridge_put_all_devices();
2535 fail0:
2536         mutex_unlock(&sbridge_edac_lock);
2537         return rc;
2538 }
2539
2540 /*
2541  *      sbridge_remove  destructor for one instance of device
2542  *
2543  */
2544 static void sbridge_remove(struct pci_dev *pdev)
2545 {
2546         struct sbridge_dev *sbridge_dev;
2547
2548         edac_dbg(0, "\n");
2549
2550         /*
2551          * we have a trouble here: pdev value for removal will be wrong, since
2552          * it will point to the X58 register used to detect that the machine
2553          * is a Nehalem or upper design. However, due to the way several PCI
2554          * devices are grouped together to provide MC functionality, we need
2555          * to use a different method for releasing the devices
2556          */
2557
2558         mutex_lock(&sbridge_edac_lock);
2559
2560         if (unlikely(!probed)) {
2561                 mutex_unlock(&sbridge_edac_lock);
2562                 return;
2563         }
2564
2565         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2566                 sbridge_unregister_mci(sbridge_dev);
2567
2568         /* Release PCI resources */
2569         sbridge_put_all_devices();
2570
2571         probed--;
2572
2573         mutex_unlock(&sbridge_edac_lock);
2574 }
2575
2576 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2577
2578 /*
2579  *      sbridge_driver  pci_driver structure for this module
2580  *
2581  */
2582 static struct pci_driver sbridge_driver = {
2583         .name     = "sbridge_edac",
2584         .probe    = sbridge_probe,
2585         .remove   = sbridge_remove,
2586         .id_table = sbridge_pci_tbl,
2587 };
2588
2589 /*
2590  *      sbridge_init            Module entry function
2591  *                      Try to initialize this module for its devices
2592  */
2593 static int __init sbridge_init(void)
2594 {
2595         int pci_rc;
2596
2597         edac_dbg(2, "\n");
2598
2599         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2600         opstate_init();
2601
2602         pci_rc = pci_register_driver(&sbridge_driver);
2603         if (pci_rc >= 0) {
2604                 mce_register_decode_chain(&sbridge_mce_dec);
2605                 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2606                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2607                 return 0;
2608         }
2609
2610         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2611                       pci_rc);
2612
2613         return pci_rc;
2614 }
2615
2616 /*
2617  *      sbridge_exit()  Module exit function
2618  *                      Unregister the driver
2619  */
2620 static void __exit sbridge_exit(void)
2621 {
2622         edac_dbg(2, "\n");
2623         pci_unregister_driver(&sbridge_driver);
2624         mce_unregister_decode_chain(&sbridge_mce_dec);
2625 }
2626
2627 module_init(sbridge_init);
2628 module_exit(sbridge_exit);
2629
2630 module_param(edac_op_state, int, 0444);
2631 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2632
2633 MODULE_LICENSE("GPL");
2634 MODULE_AUTHOR("Mauro Carvalho Chehab");
2635 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2636 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
2637                    SBRIDGE_REVISION);