drivers/firewire/fw-ohci.c

   1 /*                                              -*- c-basic-offset: 8 -*-
   2  *
   3  * fw-ohci.c - Driver for OHCI 1394 boards
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/pci.h>
  26 #include <linux/delay.h>
  27 #include <linux/poll.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <asm/uaccess.h>
  31 #include <asm/semaphore.h>
  32
  33 #include "fw-transaction.h"
  34 #include "fw-ohci.h"
  35
  36 #define descriptor_output_more          0
  37 #define descriptor_output_last          (1 << 12)
  38 #define descriptor_input_more           (2 << 12)
  39 #define descriptor_input_last           (3 << 12)
  40 #define descriptor_status               (1 << 11)
  41 #define descriptor_key_immediate        (2 << 8)
  42 #define descriptor_ping                 (1 << 7)
  43 #define descriptor_yy                   (1 << 6)
  44 #define descriptor_no_irq               (0 << 4)
  45 #define descriptor_irq_error            (1 << 4)
  46 #define descriptor_irq_always           (3 << 4)
  47 #define descriptor_branch_always        (3 << 2)
  48
  49 struct descriptor {
  50         __le16 req_count;
  51         __le16 control;
  52         __le32 data_address;
  53         __le32 branch_address;
  54         __le16 res_count;
  55         __le16 transfer_status;
  56 } __attribute__((aligned(16)));
  57
  58 struct ar_context {
  59         struct fw_ohci *ohci;
  60         struct descriptor descriptor;
  61         __le32 buffer[512];
  62         dma_addr_t descriptor_bus;
  63         dma_addr_t buffer_bus;
  64
  65         u32 command_ptr;
  66         u32 control_set;
  67         u32 control_clear;
  68
  69         struct tasklet_struct tasklet;
  70 };
  71
  72 struct at_context {
  73         struct fw_ohci *ohci;
  74         dma_addr_t descriptor_bus;
  75         dma_addr_t buffer_bus;
  76
  77         struct list_head list;
  78
  79         struct {
  80                 struct descriptor more;
  81                 __le32 header[4];
  82                 struct descriptor last;
  83         } d;
  84
  85         u32 command_ptr;
  86         u32 control_set;
  87         u32 control_clear;
  88
  89         struct tasklet_struct tasklet;
  90 };
  91
  92 #define it_header_sy(v)          ((v) <<  0)
  93 #define it_header_tcode(v)       ((v) <<  4)
  94 #define it_header_channel(v)     ((v) <<  8)
  95 #define it_header_tag(v)         ((v) << 14)
  96 #define it_header_speed(v)       ((v) << 16)
  97 #define it_header_data_length(v) ((v) << 16)
  98
  99 struct iso_context {
 100         struct fw_iso_context base;
 101         struct tasklet_struct tasklet;
 102         u32 control_set;
 103         u32 control_clear;
 104         u32 command_ptr;
 105         u32 context_match;
 106
 107         struct descriptor *buffer;
 108         dma_addr_t buffer_bus;
 109         struct descriptor *head_descriptor;
 110         struct descriptor *tail_descriptor;
 111         struct descriptor *tail_descriptor_last;
 112         struct descriptor *prev_descriptor;
 113 };
 114
 115 #define CONFIG_ROM_SIZE 1024
 116
 117 struct fw_ohci {
 118         struct fw_card card;
 119
 120         __iomem char *registers;
 121         dma_addr_t self_id_bus;
 122         __le32 *self_id_cpu;
 123         struct tasklet_struct bus_reset_tasklet;
 124         int generation;
 125         int request_generation;
 126
 127         /* Spinlock for accessing fw_ohci data.  Never call out of
 128          * this driver with this lock held. */
 129         spinlock_t lock;
 130         u32 self_id_buffer[512];
 131
 132         /* Config rom buffers */
 133         __be32 *config_rom;
 134         dma_addr_t config_rom_bus;
 135         __be32 *next_config_rom;
 136         dma_addr_t next_config_rom_bus;
 137         u32 next_header;
 138
 139         struct ar_context ar_request_ctx;
 140         struct ar_context ar_response_ctx;
 141         struct at_context at_request_ctx;
 142         struct at_context at_response_ctx;
 143
 144         u32 it_context_mask;
 145         struct iso_context *it_context_list;
 146         u32 ir_context_mask;
 147         struct iso_context *ir_context_list;
 148 };
 149
 150 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 151 {
 152         return container_of(card, struct fw_ohci, card);
 153 }
 154
 155 #define CONTEXT_CYCLE_MATCH_ENABLE      0x80000000
 156
 157 #define CONTEXT_RUN     0x8000
 158 #define CONTEXT_WAKE    0x1000
 159 #define CONTEXT_DEAD    0x0800
 160 #define CONTEXT_ACTIVE  0x0400
 161
 162 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 163 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 164 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 165
 166 #define FW_OHCI_MAJOR                   240
 167 #define OHCI1394_REGISTER_SIZE          0x800
 168 #define OHCI_LOOP_COUNT                 500
 169 #define OHCI1394_PCI_HCI_Control        0x40
 170 #define SELF_ID_BUF_SIZE                0x800
 171
 172 /* FIXME: Move this to linux/pci_ids.h */
 173 #define PCI_CLASS_SERIAL_FIREWIRE_OHCI  0x0c0010
 174
 175 static char ohci_driver_name[] = KBUILD_MODNAME;
 176
 177 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 178 {
 179         writel(data, ohci->registers + offset);
 180 }
 181
 182 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 183 {
 184         return readl(ohci->registers + offset);
 185 }
 186
 187 static inline void flush_writes(const struct fw_ohci *ohci)
 188 {
 189         /* Do a dummy read to flush writes. */
 190         reg_read(ohci, OHCI1394_Version);
 191 }
 192
 193 static int
 194 ohci_update_phy_reg(struct fw_card *card, int addr,
 195                     int clear_bits, int set_bits)
 196 {
 197         struct fw_ohci *ohci = fw_ohci(card);
 198         u32 val, old;
 199
 200         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 201         msleep(2);
 202         val = reg_read(ohci, OHCI1394_PhyControl);
 203         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 204                 fw_error("failed to set phy reg bits.\n");
 205                 return -EBUSY;
 206         }
 207
 208         old = OHCI1394_PhyControl_ReadData(val);
 209         old = (old & ~clear_bits) | set_bits;
 210         reg_write(ohci, OHCI1394_PhyControl,
 211                   OHCI1394_PhyControl_Write(addr, old));
 212
 213         return 0;
 214 }
 215
 216 static void ar_context_run(struct ar_context *ctx)
 217 {
 218         reg_write(ctx->ohci, ctx->command_ptr, ctx->descriptor_bus | 1);
 219         reg_write(ctx->ohci, ctx->control_set, CONTEXT_RUN);
 220         flush_writes(ctx->ohci);
 221 }
 222
 223 static void ar_context_tasklet(unsigned long data)
 224 {
 225         struct ar_context *ctx = (struct ar_context *)data;
 226         struct fw_ohci *ohci = ctx->ohci;
 227         u32 status;
 228         int length, speed, ack, timestamp, tcode;
 229
 230         /* FIXME: What to do about evt_* errors? */
 231         length    = le16_to_cpu(ctx->descriptor.req_count) -
 232                 le16_to_cpu(ctx->descriptor.res_count) - 4;
 233         status    = le32_to_cpu(ctx->buffer[length / 4]);
 234         ack       = ((status >> 16) & 0x1f) - 16;
 235         speed     = (status >> 21) & 0x7;
 236         timestamp = status & 0xffff;
 237
 238         ctx->buffer[0] = le32_to_cpu(ctx->buffer[0]);
 239         ctx->buffer[1] = le32_to_cpu(ctx->buffer[1]);
 240         ctx->buffer[2] = le32_to_cpu(ctx->buffer[2]);
 241
 242         tcode = (ctx->buffer[0] >> 4) & 0x0f;
 243         if (TCODE_IS_BLOCK_PACKET(tcode))
 244                 ctx->buffer[3] = le32_to_cpu(ctx->buffer[3]);
 245
 246         /* The OHCI bus reset handler synthesizes a phy packet with
 247          * the new generation number when a bus reset happens (see
 248          * section 8.4.2.3).  This helps us determine when a request
 249          * was received and make sure we send the response in the same
 250          * generation.  We only need this for requests; for responses
 251          * we use the unique tlabel for finding the matching
 252          * request. */
 253
 254         if (ack + 16 == 0x09)
 255                 ohci->request_generation = (ctx->buffer[2] >> 16) & 0xff;
 256         else if (ctx == &ohci->ar_request_ctx)
 257                 fw_core_handle_request(&ohci->card, speed, ack, timestamp,
 258                                        ohci->request_generation,
 259                                        length, ctx->buffer);
 260         else
 261                 fw_core_handle_response(&ohci->card, speed, ack, timestamp,
 262                                         length, ctx->buffer);
 263
 264         ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus);
 265         ctx->descriptor.req_count    = cpu_to_le16(sizeof ctx->buffer);
 266         ctx->descriptor.res_count    = cpu_to_le16(sizeof ctx->buffer);
 267
 268         dma_sync_single_for_device(ohci->card.device, ctx->descriptor_bus,
 269                                    sizeof ctx->descriptor_bus, DMA_TO_DEVICE);
 270
 271         /* FIXME: We stop and restart the ar context here, what if we
 272          * stop while a receive is in progress? Maybe we could just
 273          * loop the context back to itself and use it in buffer fill
 274          * mode as intended... */
 275
 276         reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN);
 277         ar_context_run(ctx);
 278 }
 279
 280 static int
 281 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 control_set)
 282 {
 283         ctx->descriptor_bus =
 284                 dma_map_single(ohci->card.device, &ctx->descriptor,
 285                                sizeof ctx->descriptor, DMA_TO_DEVICE);
 286         if (ctx->descriptor_bus == 0)
 287                 return -ENOMEM;
 288
 289         if (ctx->descriptor_bus & 0xf)
 290                 fw_notify("descriptor not 16-byte aligned: 0x%08lx\n",
 291                           (unsigned long)ctx->descriptor_bus);
 292
 293         ctx->buffer_bus =
 294                 dma_map_single(ohci->card.device, ctx->buffer,
 295                                sizeof ctx->buffer, DMA_FROM_DEVICE);
 296
 297         if (ctx->buffer_bus == 0) {
 298                 dma_unmap_single(ohci->card.device, ctx->descriptor_bus,
 299                                  sizeof ctx->descriptor, DMA_TO_DEVICE);
 300                 return -ENOMEM;
 301         }
 302
 303         memset(&ctx->descriptor, 0, sizeof ctx->descriptor);
 304         ctx->descriptor.control      = cpu_to_le16(descriptor_input_more |
 305                                                    descriptor_status |
 306                                                    descriptor_branch_always);
 307         ctx->descriptor.req_count    = cpu_to_le16(sizeof ctx->buffer);
 308         ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus);
 309         ctx->descriptor.res_count    = cpu_to_le16(sizeof ctx->buffer);
 310
 311         ctx->control_set   = control_set;
 312         ctx->control_clear = control_set + 4;
 313         ctx->command_ptr   = control_set + 12;
 314         ctx->ohci          = ohci;
 315
 316         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 317
 318         ar_context_run(ctx);
 319
 320         return 0;
 321 }
 322
 323 static void
 324 do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
 325 {
 326         struct fw_packet *p, *next;
 327
 328         list_for_each_entry_safe(p, next, list, link)
 329                 p->callback(p, &ohci->card, p->status);
 330 }
 331
 332 static void
 333 complete_transmission(struct fw_packet *packet,
 334                       int status, struct list_head *list)
 335 {
 336         list_move_tail(&packet->link, list);
 337         packet->status = status;
 338 }
 339
 340 /* This function prepares the first packet in the context queue for
 341  * transmission.  Must always be called with the ochi->lock held to
 342  * ensure proper generation handling and locking around packet queue
 343  * manipulation. */
 344 static void
 345 at_context_setup_packet(struct at_context *ctx, struct list_head *list)
 346 {
 347         struct fw_packet *packet;
 348         struct fw_ohci *ohci = ctx->ohci;
 349         int z, tcode;
 350
 351         packet = fw_packet(ctx->list.next);
 352
 353         memset(&ctx->d, 0, sizeof ctx->d);
 354         if (packet->payload_length > 0) {
 355                 packet->payload_bus = dma_map_single(ohci->card.device,
 356                                                      packet->payload,
 357                                                      packet->payload_length,
 358                                                      DMA_TO_DEVICE);
 359                 if (packet->payload_bus == 0) {
 360                         complete_transmission(packet, -ENOMEM, list);
 361                         return;
 362                 }
 363
 364                 ctx->d.more.control      =
 365                         cpu_to_le16(descriptor_output_more |
 366                                     descriptor_key_immediate);
 367                 ctx->d.more.req_count    = cpu_to_le16(packet->header_length);
 368                 ctx->d.more.res_count    = cpu_to_le16(packet->timestamp);
 369                 ctx->d.last.control      =
 370                         cpu_to_le16(descriptor_output_last |
 371                                     descriptor_irq_always |
 372                                     descriptor_branch_always);
 373                 ctx->d.last.req_count    = cpu_to_le16(packet->payload_length);
 374                 ctx->d.last.data_address = cpu_to_le32(packet->payload_bus);
 375                 z = 3;
 376         } else {
 377                 ctx->d.more.control   =
 378                         cpu_to_le16(descriptor_output_last |
 379                                     descriptor_key_immediate |
 380                                     descriptor_irq_always |
 381                                     descriptor_branch_always);
 382                 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
 383                 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
 384                 z = 2;
 385         }
 386
 387         /* The DMA format for asyncronous link packets is different
 388          * from the IEEE1394 layout, so shift the fields around
 389          * accordingly.  If header_length is 8, it's a PHY packet, to
 390          * which we need to prepend an extra quadlet. */
 391         if (packet->header_length > 8) {
 392                 ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 393                                                (packet->speed << 16));
 394                 ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 395                                                (packet->header[0] & 0xffff0000));
 396                 ctx->d.header[2] = cpu_to_le32(packet->header[2]);
 397
 398                 tcode = (packet->header[0] >> 4) & 0x0f;
 399                 if (TCODE_IS_BLOCK_PACKET(tcode))
 400                         ctx->d.header[3] = cpu_to_le32(packet->header[3]);
 401                 else
 402                         ctx->d.header[3] = packet->header[3];
 403         } else {
 404                 ctx->d.header[0] =
 405                         cpu_to_le32((OHCI1394_phy_tcode << 4) |
 406                                     (packet->speed << 16));
 407                 ctx->d.header[1] = cpu_to_le32(packet->header[0]);
 408                 ctx->d.header[2] = cpu_to_le32(packet->header[1]);
 409                 ctx->d.more.req_count = cpu_to_le16(12);
 410         }
 411
 412         /* FIXME: Document how the locking works. */
 413         if (ohci->generation == packet->generation) {
 414                 reg_write(ctx->ohci, ctx->command_ptr,
 415                           ctx->descriptor_bus | z);
 416                 reg_write(ctx->ohci, ctx->control_set,
 417                           CONTEXT_RUN | CONTEXT_WAKE);
 418         } else {
 419                 /* We dont return error codes from this function; all
 420                  * transmission errors are reported through the
 421                  * callback. */
 422                 complete_transmission(packet, -ESTALE, list);
 423         }
 424 }
 425
 426 static void at_context_stop(struct at_context *ctx)
 427 {
 428         u32 reg;
 429
 430         reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN);
 431
 432         reg = reg_read(ctx->ohci, ctx->control_set);
 433         if (reg & CONTEXT_ACTIVE)
 434                 fw_notify("Tried to stop context, but it is still active "
 435                           "(0x%08x).\n", reg);
 436 }
 437
 438 static void at_context_tasklet(unsigned long data)
 439 {
 440         struct at_context *ctx = (struct at_context *)data;
 441         struct fw_ohci *ohci = ctx->ohci;
 442         struct fw_packet *packet;
 443         LIST_HEAD(list);
 444         unsigned long flags;
 445         int evt;
 446
 447         spin_lock_irqsave(&ohci->lock, flags);
 448
 449         packet = fw_packet(ctx->list.next);
 450
 451         at_context_stop(ctx);
 452
 453         if (packet->payload_length > 0) {
 454                 dma_unmap_single(ohci->card.device, packet->payload_bus,
 455                                  packet->payload_length, DMA_TO_DEVICE);
 456                 evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f;
 457                 packet->timestamp = le16_to_cpu(ctx->d.last.res_count);
 458         }
 459         else {
 460                 evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f;
 461                 packet->timestamp = le16_to_cpu(ctx->d.more.res_count);
 462         }
 463
 464         if (evt < 16) {
 465                 switch (evt) {
 466                 case OHCI1394_evt_timeout:
 467                         /* Async response transmit timed out. */
 468                         complete_transmission(packet, -ETIMEDOUT, &list);
 469                         break;
 470
 471                 case OHCI1394_evt_flushed:
 472                         /* The packet was flushed should give same
 473                          * error as when we try to use a stale
 474                          * generation count. */
 475                         complete_transmission(packet, -ESTALE, &list);
 476                         break;
 477
 478                 case OHCI1394_evt_missing_ack:
 479                         /* This would be a higher level software
 480                          * error, it is using a valid (current)
 481                          * generation count, but the node is not on
 482                          * the bus. */
 483                         complete_transmission(packet, -ENODEV, &list);
 484                         break;
 485
 486                 default:
 487                         complete_transmission(packet, -EIO, &list);
 488                         break;
 489                 }
 490         } else
 491                 complete_transmission(packet, evt - 16, &list);
 492
 493         /* If more packets are queued, set up the next one. */
 494         if (!list_empty(&ctx->list))
 495                 at_context_setup_packet(ctx, &list);
 496
 497         spin_unlock_irqrestore(&ohci->lock, flags);
 498
 499         do_packet_callbacks(ohci, &list);
 500 }
 501
 502 static int
 503 at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 control_set)
 504 {
 505         INIT_LIST_HEAD(&ctx->list);
 506
 507         ctx->descriptor_bus =
 508                 dma_map_single(ohci->card.device, &ctx->d,
 509                                sizeof ctx->d, DMA_TO_DEVICE);
 510         if (ctx->descriptor_bus == 0)
 511                 return -ENOMEM;
 512
 513         ctx->control_set   = control_set;
 514         ctx->control_clear = control_set + 4;
 515         ctx->command_ptr   = control_set + 12;
 516         ctx->ohci          = ohci;
 517
 518         tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx);
 519
 520         return 0;
 521 }
 522
 523 static void
 524 at_context_transmit(struct at_context *ctx, struct fw_packet *packet)
 525 {
 526         LIST_HEAD(list);
 527         unsigned long flags;
 528         int was_empty;
 529
 530         spin_lock_irqsave(&ctx->ohci->lock, flags);
 531
 532         was_empty = list_empty(&ctx->list);
 533         list_add_tail(&packet->link, &ctx->list);
 534         if (was_empty)
 535                 at_context_setup_packet(ctx, &list);
 536
 537         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 538
 539         do_packet_callbacks(ctx->ohci, &list);
 540 }
 541
 542 static void bus_reset_tasklet(unsigned long data)
 543 {
 544         struct fw_ohci *ohci = (struct fw_ohci *)data;
 545         int self_id_count, i, j, reg, node_id;
 546         int generation, new_generation;
 547         unsigned long flags;
 548
 549         reg = reg_read(ohci, OHCI1394_NodeID);
 550         if (!(reg & OHCI1394_NodeID_idValid)) {
 551                 fw_error("node ID not valid, new bus reset in progress\n");
 552                 return;
 553         }
 554         node_id = reg & 0xffff;
 555
 556         /* The count in the SelfIDCount register is the number of
 557          * bytes in the self ID receive buffer.  Since we also receive
 558          * the inverted quadlets and a header quadlet, we shift one
 559          * bit extra to get the actual number of self IDs. */
 560
 561         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
 562         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 563
 564         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 565                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
 566                         fw_error("inconsistent self IDs\n");
 567                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
 568         }
 569
 570         /* Check the consistency of the self IDs we just read.  The
 571          * problem we face is that a new bus reset can start while we
 572          * read out the self IDs from the DMA buffer. If this happens,
 573          * the DMA buffer will be overwritten with new self IDs and we
 574          * will read out inconsistent data.  The OHCI specification
 575          * (section 11.2) recommends a technique similar to
 576          * linux/seqlock.h, where we remember the generation of the
 577          * self IDs in the buffer before reading them out and compare
 578          * it to the current generation after reading them out.  If
 579          * the two generations match we know we have a consistent set
 580          * of self IDs. */
 581
 582         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 583         if (new_generation != generation) {
 584                 fw_notify("recursive bus reset detected, "
 585                           "discarding self ids\n");
 586                 return;
 587         }
 588
 589         /* FIXME: Document how the locking works. */
 590         spin_lock_irqsave(&ohci->lock, flags);
 591
 592         ohci->generation = generation;
 593         at_context_stop(&ohci->at_request_ctx);
 594         at_context_stop(&ohci->at_response_ctx);
 595         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 596
 597         /* This next bit is unrelated to the AT context stuff but we
 598          * have to do it under the spinlock also.  If a new config rom
 599          * was set up before this reset, the old one is now no longer
 600          * in use and we can free it. Update the config rom pointers
 601          * to point to the current config rom and clear the
 602          * next_config_rom pointer so a new udpate can take place. */
 603
 604         if (ohci->next_config_rom != NULL) {
 605                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 606                                   ohci->config_rom, ohci->config_rom_bus);
 607                 ohci->config_rom      = ohci->next_config_rom;
 608                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
 609                 ohci->next_config_rom = NULL;
 610
 611                 /* Restore config_rom image and manually update
 612                  * config_rom registers.  Writing the header quadlet
 613                  * will indicate that the config rom is ready, so we
 614                  * do that last. */
 615                 reg_write(ohci, OHCI1394_BusOptions,
 616                           be32_to_cpu(ohci->config_rom[2]));
 617                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
 618                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
 619         }
 620
 621         spin_unlock_irqrestore(&ohci->lock, flags);
 622
 623         fw_core_handle_bus_reset(&ohci->card, node_id, generation,
 624                                  self_id_count, ohci->self_id_buffer);
 625 }
 626
 627 static irqreturn_t irq_handler(int irq, void *data)
 628 {
 629         struct fw_ohci *ohci = data;
 630         u32 event, iso_event;
 631         int i;
 632
 633         event = reg_read(ohci, OHCI1394_IntEventClear);
 634
 635         if (!event)
 636                 return IRQ_NONE;
 637
 638         reg_write(ohci, OHCI1394_IntEventClear, event);
 639
 640         if (event & OHCI1394_selfIDComplete)
 641                 tasklet_schedule(&ohci->bus_reset_tasklet);
 642
 643         if (event & OHCI1394_RQPkt)
 644                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
 645
 646         if (event & OHCI1394_RSPkt)
 647                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
 648
 649         if (event & OHCI1394_reqTxComplete)
 650                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
 651
 652         if (event & OHCI1394_respTxComplete)
 653                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
 654
 655         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
 656         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
 657
 658         while (iso_event) {
 659                 i = ffs(iso_event) - 1;
 660                 tasklet_schedule(&ohci->ir_context_list[i].tasklet);
 661                 iso_event &= ~(1 << i);
 662         }
 663
 664         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
 665         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
 666
 667         while (iso_event) {
 668                 i = ffs(iso_event) - 1;
 669                 tasklet_schedule(&ohci->it_context_list[i].tasklet);
 670                 iso_event &= ~(1 << i);
 671         }
 672
 673         return IRQ_HANDLED;
 674 }
 675
 676 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
 677 {
 678         struct fw_ohci *ohci = fw_ohci(card);
 679         struct pci_dev *dev = to_pci_dev(card->device);
 680
 681         /* When the link is not yet enabled, the atomic config rom
 682          * update mechanism described below in ohci_set_config_rom()
 683          * is not active.  We have to update ConfigRomHeader and
 684          * BusOptions manually, and the write to ConfigROMmap takes
 685          * effect immediately.  We tie this to the enabling of the
 686          * link, so we have a valid config rom before enabling - the
 687          * OHCI requires that ConfigROMhdr and BusOptions have valid
 688          * values before enabling.
 689          *
 690          * However, when the ConfigROMmap is written, some controllers
 691          * always read back quadlets 0 and 2 from the config rom to
 692          * the ConfigRomHeader and BusOptions registers on bus reset.
 693          * They shouldn't do that in this initial case where the link
 694          * isn't enabled.  This means we have to use the same
 695          * workaround here, setting the bus header to 0 and then write
 696          * the right values in the bus reset tasklet.
 697          */
 698
 699         ohci->next_config_rom =
 700                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 701                                    &ohci->next_config_rom_bus, GFP_KERNEL);
 702         if (ohci->next_config_rom == NULL)
 703                 return -ENOMEM;
 704
 705         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
 706         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
 707
 708         ohci->next_header = config_rom[0];
 709         ohci->next_config_rom[0] = 0;
 710         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
 711         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
 712         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
 713
 714         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
 715
 716         if (request_irq(dev->irq, irq_handler,
 717                         SA_SHIRQ, ohci_driver_name, ohci)) {
 718                 fw_error("Failed to allocate shared interrupt %d.\n",
 719                          dev->irq);
 720                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 721                                   ohci->config_rom, ohci->config_rom_bus);
 722                 return -EIO;
 723         }
 724
 725         reg_write(ohci, OHCI1394_HCControlSet,
 726                   OHCI1394_HCControl_linkEnable |
 727                   OHCI1394_HCControl_BIBimageValid);
 728         flush_writes(ohci);
 729
 730         /* We are ready to go, initiate bus reset to finish the
 731          * initialization. */
 732
 733         fw_core_initiate_bus_reset(&ohci->card, 1);
 734
 735         return 0;
 736 }
 737
 738 static int
 739 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
 740 {
 741         struct fw_ohci *ohci;
 742         unsigned long flags;
 743         int retval = 0;
 744         __be32 *next_config_rom;
 745         dma_addr_t next_config_rom_bus;
 746
 747         ohci = fw_ohci(card);
 748
 749         /* When the OHCI controller is enabled, the config rom update
 750          * mechanism is a bit tricky, but easy enough to use.  See
 751          * section 5.5.6 in the OHCI specification.
 752          *
 753          * The OHCI controller caches the new config rom address in a
 754          * shadow register (ConfigROMmapNext) and needs a bus reset
 755          * for the changes to take place.  When the bus reset is
 756          * detected, the controller loads the new values for the
 757          * ConfigRomHeader and BusOptions registers from the specified
 758          * config rom and loads ConfigROMmap from the ConfigROMmapNext
 759          * shadow register. All automatically and atomically.
 760          *
 761          * Now, there's a twist to this story.  The automatic load of
 762          * ConfigRomHeader and BusOptions doesn't honor the
 763          * noByteSwapData bit, so with a be32 config rom, the
 764          * controller will load be32 values in to these registers
 765          * during the atomic update, even on litte endian
 766          * architectures.  The workaround we use is to put a 0 in the
 767          * header quadlet; 0 is endian agnostic and means that the
 768          * config rom isn't ready yet.  In the bus reset tasklet we
 769          * then set up the real values for the two registers.
 770          *
 771          * We use ohci->lock to avoid racing with the code that sets
 772          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
 773          */
 774
 775         next_config_rom =
 776                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 777                                    &next_config_rom_bus, GFP_KERNEL);
 778         if (next_config_rom == NULL)
 779                 return -ENOMEM;
 780
 781         spin_lock_irqsave(&ohci->lock, flags);
 782
 783         if (ohci->next_config_rom == NULL) {
 784                 ohci->next_config_rom = next_config_rom;
 785                 ohci->next_config_rom_bus = next_config_rom_bus;
 786
 787                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
 788                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
 789                                   length * 4);
 790
 791                 ohci->next_header = config_rom[0];
 792                 ohci->next_config_rom[0] = 0;
 793
 794                 reg_write(ohci, OHCI1394_ConfigROMmap,
 795                           ohci->next_config_rom_bus);
 796         } else {
 797                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 798                                   next_config_rom, next_config_rom_bus);
 799                 retval = -EBUSY;
 800         }
 801
 802         spin_unlock_irqrestore(&ohci->lock, flags);
 803
 804         /* Now initiate a bus reset to have the changes take
 805          * effect. We clean up the old config rom memory and DMA
 806          * mappings in the bus reset tasklet, since the OHCI
 807          * controller could need to access it before the bus reset
 808          * takes effect. */
 809         if (retval == 0)
 810                 fw_core_initiate_bus_reset(&ohci->card, 1);
 811
 812         return retval;
 813 }
 814
 815 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
 816 {
 817         struct fw_ohci *ohci = fw_ohci(card);
 818
 819         at_context_transmit(&ohci->at_request_ctx, packet);
 820 }
 821
 822 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
 823 {
 824         struct fw_ohci *ohci = fw_ohci(card);
 825
 826         at_context_transmit(&ohci->at_response_ctx, packet);
 827 }
 828
 829 static int
 830 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
 831 {
 832         struct fw_ohci *ohci = fw_ohci(card);
 833         unsigned long flags;
 834         int retval = 0;
 835
 836         /* FIXME: make sure this bitmask is cleared when we clear the
 837          * busReset interrupt bit. */
 838
 839         spin_lock_irqsave(&ohci->lock, flags);
 840
 841         if (ohci->generation != generation) {
 842                 retval = -ESTALE;
 843                 goto out;
 844         }
 845
 846         if (node_id < 32) {
 847                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << node_id);
 848         } else {
 849                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
 850                           1 << (node_id - 32));
 851         }
 852         flush_writes(ohci);
 853  out:
 854         spin_unlock_irqrestore(&ohci->lock, flags);
 855         return retval;
 856 }
 857
 858 static void ir_context_tasklet(unsigned long data)
 859 {
 860         struct iso_context *ctx = (struct iso_context *)data;
 861
 862         (void)ctx;
 863 }
 864
 865 #define ISO_BUFFER_SIZE (64 * 1024)
 866
 867 static void flush_iso_context(struct iso_context *ctx)
 868 {
 869         struct fw_ohci *ohci = fw_ohci(ctx->base.card);
 870         struct descriptor *d, *last;
 871         u32 address;
 872         int z;
 873
 874         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
 875                                 ISO_BUFFER_SIZE, DMA_TO_DEVICE);
 876
 877         d    = ctx->tail_descriptor;
 878         last = ctx->tail_descriptor_last;
 879
 880         while (last->branch_address != 0 && last->transfer_status != 0) {
 881                 address = le32_to_cpu(last->branch_address);
 882                 z = address & 0xf;
 883                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
 884
 885                 if (z == 2)
 886                         last = d;
 887                 else
 888                         last = d + z - 1;
 889
 890                 if (le16_to_cpu(last->control) & descriptor_irq_always)
 891                         ctx->base.callback(&ctx->base,
 892                                            0, le16_to_cpu(last->res_count),
 893                                            ctx->base.callback_data);
 894         }
 895
 896         ctx->tail_descriptor      = d;
 897         ctx->tail_descriptor_last = last;
 898 }
 899
 900 static void it_context_tasklet(unsigned long data)
 901 {
 902         struct iso_context *ctx = (struct iso_context *)data;
 903
 904         flush_iso_context(ctx);
 905 }
 906
 907 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
 908                                                         int type)
 909 {
 910         struct fw_ohci *ohci = fw_ohci(card);
 911         struct iso_context *ctx, *list;
 912         void (*tasklet) (unsigned long data);
 913         u32 *mask;
 914         unsigned long flags;
 915         int index;
 916
 917         if (type == FW_ISO_CONTEXT_TRANSMIT) {
 918                 mask = &ohci->it_context_mask;
 919                 list = ohci->it_context_list;
 920                 tasklet = it_context_tasklet;
 921         } else {
 922                 mask = &ohci->ir_context_mask;
 923                 list = ohci->ir_context_list;
 924                 tasklet = ir_context_tasklet;
 925         }
 926
 927         spin_lock_irqsave(&ohci->lock, flags);
 928         index = ffs(*mask) - 1;
 929         if (index >= 0)
 930                 *mask &= ~(1 << index);
 931         spin_unlock_irqrestore(&ohci->lock, flags);
 932
 933         if (index < 0)
 934                 return ERR_PTR(-EBUSY);
 935
 936         ctx = &list[index];
 937         memset(ctx, 0, sizeof *ctx);
 938         tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx);
 939
 940         ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL);
 941         if (ctx->buffer == NULL) {
 942                 spin_lock_irqsave(&ohci->lock, flags);
 943                 *mask |= 1 << index;
 944                 spin_unlock_irqrestore(&ohci->lock, flags);
 945                 return ERR_PTR(-ENOMEM);
 946         }
 947
 948         ctx->buffer_bus =
 949             dma_map_single(card->device, ctx->buffer,
 950                            ISO_BUFFER_SIZE, DMA_TO_DEVICE);
 951
 952         ctx->head_descriptor      = ctx->buffer;
 953         ctx->prev_descriptor      = ctx->buffer;
 954         ctx->tail_descriptor      = ctx->buffer;
 955         ctx->tail_descriptor_last = ctx->buffer;
 956
 957         /* We put a dummy descriptor in the buffer that has a NULL
 958          * branch address and looks like it's been sent.  That way we
 959          * have a descriptor to append DMA programs to.  Also, the
 960          * ring buffer invariant is that it always has at least one
 961          * element so that head == tail means buffer full. */
 962
 963         memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
 964         ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
 965         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
 966         ctx->head_descriptor++;
 967
 968         return &ctx->base;
 969 }
 970
 971 static int ohci_send_iso(struct fw_iso_context *base, s32 cycle)
 972 {
 973         struct iso_context *ctx = (struct iso_context *)base;
 974         struct fw_ohci *ohci = fw_ohci(ctx->base.card);
 975         u32 cycle_match = 0;
 976         int index;
 977
 978         index = ctx - ohci->it_context_list;
 979         if (cycle > 0)
 980                 cycle_match = CONTEXT_CYCLE_MATCH_ENABLE |
 981                         (cycle & 0x7fff) << 16;
 982
 983         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
 984         reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index),
 985                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
 986         reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
 987         reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index),
 988                   CONTEXT_RUN | cycle_match);
 989         flush_writes(ohci);
 990
 991         return 0;
 992 }
 993
 994 static void ohci_free_iso_context(struct fw_iso_context *base)
 995 {
 996         struct fw_ohci *ohci = fw_ohci(base->card);
 997         struct iso_context *ctx = (struct iso_context *)base;
 998         unsigned long flags;
 999         int index;
1000
1001         flush_iso_context(ctx);
1002
1003         spin_lock_irqsave(&ohci->lock, flags);
1004
1005         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1006                 index = ctx - ohci->it_context_list;
1007                 reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
1008                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1009                 ohci->it_context_mask |= 1 << index;
1010         } else {
1011                 index = ctx - ohci->ir_context_list;
1012                 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0);
1013                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1014                 ohci->ir_context_mask |= 1 << index;
1015         }
1016         flush_writes(ohci);
1017
1018         dma_unmap_single(ohci->card.device, ctx->buffer_bus,
1019                          ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1020
1021         spin_unlock_irqrestore(&ohci->lock, flags);
1022 }
1023
1024 static int
1025 ohci_queue_iso(struct fw_iso_context *base,
1026                struct fw_iso_packet *packet, void *payload)
1027 {
1028         struct iso_context *ctx = (struct iso_context *)base;
1029         struct fw_ohci *ohci = fw_ohci(ctx->base.card);
1030         struct descriptor *d, *end, *last, *tail, *pd;
1031         struct fw_iso_packet *p;
1032         __le32 *header;
1033         dma_addr_t d_bus;
1034         u32 z, header_z, payload_z, irq;
1035         u32 payload_index, payload_end_index, next_page_index;
1036         int index, page, end_page, i, length, offset;
1037
1038         /* FIXME: Cycle lost behavior should be configurable: lose
1039          * packet, retransmit or terminate.. */
1040
1041         p = packet;
1042         payload_index = payload - ctx->base.buffer;
1043         d = ctx->head_descriptor;
1044         tail = ctx->tail_descriptor;
1045         end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor);
1046
1047         if (p->skip)
1048                 z = 1;
1049         else
1050                 z = 2;
1051         if (p->header_length > 0)
1052                 z++;
1053
1054         /* Determine the first page the payload isn't contained in. */
1055         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1056         if (p->payload_length > 0)
1057                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1058         else
1059                 payload_z = 0;
1060
1061         z += payload_z;
1062
1063         /* Get header size in number of descriptors. */
1064         header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1065
1066         if (d + z + header_z <= tail) {
1067                 goto has_space;
1068         } else if (d > tail && d + z + header_z <= end) {
1069                 goto has_space;
1070         } else if (d > tail && ctx->buffer + z + header_z <= tail) {
1071                 d = ctx->buffer;
1072                 goto has_space;
1073         }
1074
1075         /* No space in buffer */
1076         return -1;
1077
1078  has_space:
1079         memset(d, 0, (z + header_z) * sizeof *d);
1080         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
1081
1082         if (!p->skip) {
1083                 d[0].control   = cpu_to_le16(descriptor_key_immediate);
1084                 d[0].req_count = cpu_to_le16(8);
1085
1086                 header = (__le32 *) &d[1];
1087                 header[0] = cpu_to_le32(it_header_sy(p->sy) |
1088                                         it_header_tag(p->tag) |
1089                                         it_header_tcode(TCODE_STREAM_DATA) |
1090                                         it_header_channel(ctx->base.channel) |
1091                                         it_header_speed(ctx->base.speed));
1092                 header[1] =
1093                         cpu_to_le32(it_header_data_length(p->header_length +
1094                                                           p->payload_length));
1095         }
1096
1097         if (p->header_length > 0) {
1098                 d[2].req_count    = cpu_to_le16(p->header_length);
1099                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
1100                 memcpy(&d[z], p->header, p->header_length);
1101         }
1102
1103         pd = d + z - payload_z;
1104         payload_end_index = payload_index + p->payload_length;
1105         for (i = 0; i < payload_z; i++) {
1106                 page               = payload_index >> PAGE_SHIFT;
1107                 offset             = payload_index & ~PAGE_MASK;
1108                 next_page_index    = (page + 1) << PAGE_SHIFT;
1109                 length             =
1110                         min(next_page_index, payload_end_index) - payload_index;
1111                 pd[i].req_count    = cpu_to_le16(length);
1112                 pd[i].data_address = cpu_to_le32(ctx->base.pages[page] + offset);
1113
1114                 payload_index += length;
1115         }
1116
1117         if (z == 2)
1118                 last = d;
1119         else
1120                 last = d + z - 1;
1121
1122         if (p->interrupt)
1123                 irq = descriptor_irq_always;
1124         else
1125                 irq = descriptor_no_irq;
1126
1127         last->control = cpu_to_le16(descriptor_output_last |
1128                                     descriptor_status |
1129                                     descriptor_branch_always |
1130                                     irq);
1131
1132         dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus,
1133                                    ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1134
1135         ctx->head_descriptor = d + z + header_z;
1136         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
1137         ctx->prev_descriptor = last;
1138
1139         index = ctx - ohci->it_context_list;
1140         reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE);
1141         flush_writes(ohci);
1142
1143         return 0;
1144 }
1145
1146 static const struct fw_card_driver ohci_driver = {
1147         .name                   = ohci_driver_name,
1148         .enable                 = ohci_enable,
1149         .update_phy_reg         = ohci_update_phy_reg,
1150         .set_config_rom         = ohci_set_config_rom,
1151         .send_request           = ohci_send_request,
1152         .send_response          = ohci_send_response,
1153         .enable_phys_dma        = ohci_enable_phys_dma,
1154
1155         .allocate_iso_context   = ohci_allocate_iso_context,
1156         .free_iso_context       = ohci_free_iso_context,
1157         .queue_iso              = ohci_queue_iso,
1158         .send_iso               = ohci_send_iso,
1159 };
1160
1161 static int software_reset(struct fw_ohci *ohci)
1162 {
1163         int i;
1164
1165         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1166
1167         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1168                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1169                      OHCI1394_HCControl_softReset) == 0)
1170                         return 0;
1171                 msleep(1);
1172         }
1173
1174         return -EBUSY;
1175 }
1176
1177 /* ---------- pci subsystem interface ---------- */
1178
1179 enum {
1180         CLEANUP_SELF_ID,
1181         CLEANUP_REGISTERS,
1182         CLEANUP_IOMEM,
1183         CLEANUP_DISABLE,
1184         CLEANUP_PUT_CARD,
1185 };
1186
1187 static int cleanup(struct fw_ohci *ohci, int stage, int code)
1188 {
1189         struct pci_dev *dev = to_pci_dev(ohci->card.device);
1190
1191         switch (stage) {
1192         case CLEANUP_SELF_ID:
1193                 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1194                                   ohci->self_id_cpu, ohci->self_id_bus);
1195         case CLEANUP_REGISTERS:
1196                 kfree(ohci->it_context_list);
1197                 kfree(ohci->ir_context_list);
1198                 pci_iounmap(dev, ohci->registers);
1199         case CLEANUP_IOMEM:
1200                 pci_release_region(dev, 0);
1201         case CLEANUP_DISABLE:
1202                 pci_disable_device(dev);
1203         case CLEANUP_PUT_CARD:
1204                 fw_card_put(&ohci->card);
1205         }
1206
1207         return code;
1208 }
1209
1210 static int __devinit
1211 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1212 {
1213         struct fw_ohci *ohci;
1214         u32 bus_options, max_receive, link_speed;
1215         u64 guid;
1216         int error_code;
1217         size_t size;
1218
1219         ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
1220         if (ohci == NULL) {
1221                 fw_error("Could not malloc fw_ohci data.\n");
1222                 return -ENOMEM;
1223         }
1224
1225         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1226
1227         if (pci_enable_device(dev)) {
1228                 fw_error("Failed to enable OHCI hardware.\n");
1229                 return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
1230         }
1231
1232         pci_set_master(dev);
1233         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1234         pci_set_drvdata(dev, ohci);
1235
1236         spin_lock_init(&ohci->lock);
1237
1238         tasklet_init(&ohci->bus_reset_tasklet,
1239                      bus_reset_tasklet, (unsigned long)ohci);
1240
1241         if (pci_request_region(dev, 0, ohci_driver_name)) {
1242                 fw_error("MMIO resource unavailable\n");
1243                 return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
1244         }
1245
1246         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1247         if (ohci->registers == NULL) {
1248                 fw_error("Failed to remap registers\n");
1249                 return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
1250         }
1251
1252         if (software_reset(ohci)) {
1253                 fw_error("Failed to reset ohci card.\n");
1254                 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1255         }
1256
1257         /* Now enable LPS, which we need in order to start accessing
1258          * most of the registers.  In fact, on some cards (ALI M5251),
1259          * accessing registers in the SClk domain without LPS enabled
1260          * will lock up the machine.  Wait 50msec to make sure we have
1261          * full link enabled.  */
1262         reg_write(ohci, OHCI1394_HCControlSet,
1263                   OHCI1394_HCControl_LPS |
1264                   OHCI1394_HCControl_postedWriteEnable);
1265         flush_writes(ohci);
1266         msleep(50);
1267
1268         reg_write(ohci, OHCI1394_HCControlClear,
1269                   OHCI1394_HCControl_noByteSwapData);
1270
1271         reg_write(ohci, OHCI1394_LinkControlSet,
1272                   OHCI1394_LinkControl_rcvSelfID |
1273                   OHCI1394_LinkControl_cycleTimerEnable |
1274                   OHCI1394_LinkControl_cycleMaster);
1275
1276         ar_context_init(&ohci->ar_request_ctx, ohci,
1277                         OHCI1394_AsReqRcvContextControlSet);
1278
1279         ar_context_init(&ohci->ar_response_ctx, ohci,
1280                         OHCI1394_AsRspRcvContextControlSet);
1281
1282         at_context_init(&ohci->at_request_ctx, ohci,
1283                         OHCI1394_AsReqTrContextControlSet);
1284
1285         at_context_init(&ohci->at_response_ctx, ohci,
1286                         OHCI1394_AsRspTrContextControlSet);
1287
1288         reg_write(ohci, OHCI1394_ATRetries,
1289                   OHCI1394_MAX_AT_REQ_RETRIES |
1290                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1291                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1292
1293         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1294         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1295         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1296         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1297         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1298
1299         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1300         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1301         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1302         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1303         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1304
1305         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1306                 fw_error("Out of memory for it/ir contexts.\n");
1307                 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1308         }
1309
1310         /* self-id dma buffer allocation */
1311         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1312                                                SELF_ID_BUF_SIZE,
1313                                                &ohci->self_id_bus,
1314                                                GFP_KERNEL);
1315         if (ohci->self_id_cpu == NULL) {
1316                 fw_error("Out of memory for self ID buffer.\n");
1317                 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1318         }
1319
1320         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1321         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1322         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1323         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1324         reg_write(ohci, OHCI1394_IntMaskSet,
1325                   OHCI1394_selfIDComplete |
1326                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1327                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1328                   OHCI1394_isochRx | OHCI1394_isochTx |
1329                   OHCI1394_masterIntEnable);
1330
1331         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1332         max_receive = (bus_options >> 12) & 0xf;
1333         link_speed = bus_options & 0x7;
1334         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1335                 reg_read(ohci, OHCI1394_GUIDLo);
1336
1337         error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1338         if (error_code < 0)
1339                 return cleanup(ohci, CLEANUP_SELF_ID, error_code);
1340
1341         fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id);
1342
1343         return 0;
1344 }
1345
1346 static void pci_remove(struct pci_dev *dev)
1347 {
1348         struct fw_ohci *ohci;
1349
1350         ohci = pci_get_drvdata(dev);
1351         reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable);
1352         fw_core_remove_card(&ohci->card);
1353
1354         /* FIXME: Fail all pending packets here, now that the upper
1355          * layers can't queue any more. */
1356
1357         software_reset(ohci);
1358         free_irq(dev->irq, ohci);
1359         cleanup(ohci, CLEANUP_SELF_ID, 0);
1360
1361         fw_notify("Removed fw-ohci device.\n");
1362 }
1363
1364 static struct pci_device_id pci_table[] = {
1365         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1366         { }
1367 };
1368
1369 MODULE_DEVICE_TABLE(pci, pci_table);
1370
1371 static struct pci_driver fw_ohci_pci_driver = {
1372         .name           = ohci_driver_name,
1373         .id_table       = pci_table,
1374         .probe          = pci_probe,
1375         .remove         = pci_remove,
1376 };
1377
1378 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1379 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1380 MODULE_LICENSE("GPL");
1381
1382 static int __init fw_ohci_init(void)
1383 {
1384         return pci_register_driver(&fw_ohci_pci_driver);
1385 }
1386
1387 static void __exit fw_ohci_cleanup(void)
1388 {
1389         pci_unregister_driver(&fw_ohci_pci_driver);
1390 }
1391
1392 module_init(fw_ohci_init);
1393 module_exit(fw_ohci_cleanup);