2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/spinlock.h>
34 #include <asm/system.h>
36 #ifdef CONFIG_PPC_PMAC
37 #include <asm/pmac_feature.h>
41 #include "fw-transaction.h"
43 #define DESCRIPTOR_OUTPUT_MORE 0
44 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
45 #define DESCRIPTOR_INPUT_MORE (2 << 12)
46 #define DESCRIPTOR_INPUT_LAST (3 << 12)
47 #define DESCRIPTOR_STATUS (1 << 11)
48 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
49 #define DESCRIPTOR_PING (1 << 7)
50 #define DESCRIPTOR_YY (1 << 6)
51 #define DESCRIPTOR_NO_IRQ (0 << 4)
52 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
53 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
54 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
55 #define DESCRIPTOR_WAIT (3 << 0)
61 __le32 branch_address;
63 __le16 transfer_status;
64 } __attribute__((aligned(16)));
66 struct db_descriptor {
69 __le16 second_req_count;
70 __le16 first_req_count;
71 __le32 branch_address;
72 __le16 second_res_count;
73 __le16 first_res_count;
78 } __attribute__((aligned(16)));
80 #define CONTROL_SET(regs) (regs)
81 #define CONTROL_CLEAR(regs) ((regs) + 4)
82 #define COMMAND_PTR(regs) ((regs) + 12)
83 #define CONTEXT_MATCH(regs) ((regs) + 16)
86 struct descriptor descriptor;
87 struct ar_buffer *next;
93 struct ar_buffer *current_buffer;
94 struct ar_buffer *last_buffer;
97 struct tasklet_struct tasklet;
102 typedef int (*descriptor_callback_t)(struct context *ctx,
103 struct descriptor *d,
104 struct descriptor *last);
107 * A buffer that contains a block of DMA-able coherent memory used for
108 * storing a portion of a DMA descriptor program.
110 struct descriptor_buffer {
111 struct list_head list;
112 dma_addr_t buffer_bus;
115 struct descriptor buffer[0];
119 struct fw_ohci *ohci;
121 int total_allocation;
124 * List of page-sized buffers for storing DMA descriptors.
125 * Head of list contains buffers in use and tail of list contains
128 struct list_head buffer_list;
131 * Pointer to a buffer inside buffer_list that contains the tail
132 * end of the current DMA program.
134 struct descriptor_buffer *buffer_tail;
137 * The descriptor containing the branch address of the first
138 * descriptor that has not yet been filled by the device.
140 struct descriptor *last;
143 * The last descriptor in the DMA program. It contains the branch
144 * address that must be updated upon appending a new descriptor.
146 struct descriptor *prev;
148 descriptor_callback_t callback;
150 struct tasklet_struct tasklet;
153 #define IT_HEADER_SY(v) ((v) << 0)
154 #define IT_HEADER_TCODE(v) ((v) << 4)
155 #define IT_HEADER_CHANNEL(v) ((v) << 8)
156 #define IT_HEADER_TAG(v) ((v) << 14)
157 #define IT_HEADER_SPEED(v) ((v) << 16)
158 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
161 struct fw_iso_context base;
162 struct context context;
165 size_t header_length;
168 #define CONFIG_ROM_SIZE 1024
174 __iomem char *registers;
175 dma_addr_t self_id_bus;
177 struct tasklet_struct bus_reset_tasklet;
180 int request_generation;
185 * Spinlock for accessing fw_ohci data. Never call out of
186 * this driver with this lock held.
189 u32 self_id_buffer[512];
191 /* Config rom buffers */
193 dma_addr_t config_rom_bus;
194 __be32 *next_config_rom;
195 dma_addr_t next_config_rom_bus;
198 struct ar_context ar_request_ctx;
199 struct ar_context ar_response_ctx;
200 struct context at_request_ctx;
201 struct context at_response_ctx;
204 struct iso_context *it_context_list;
206 struct iso_context *ir_context_list;
209 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
211 return container_of(card, struct fw_ohci, card);
214 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
215 #define IR_CONTEXT_BUFFER_FILL 0x80000000
216 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
217 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
218 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
219 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
221 #define CONTEXT_RUN 0x8000
222 #define CONTEXT_WAKE 0x1000
223 #define CONTEXT_DEAD 0x0800
224 #define CONTEXT_ACTIVE 0x0400
226 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
227 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
228 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
230 #define FW_OHCI_MAJOR 240
231 #define OHCI1394_REGISTER_SIZE 0x800
232 #define OHCI_LOOP_COUNT 500
233 #define OHCI1394_PCI_HCI_Control 0x40
234 #define SELF_ID_BUF_SIZE 0x800
235 #define OHCI_TCODE_PHY_PACKET 0x0e
236 #define OHCI_VERSION_1_1 0x010010
238 static char ohci_driver_name[] = KBUILD_MODNAME;
240 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
242 writel(data, ohci->registers + offset);
245 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
247 return readl(ohci->registers + offset);
250 static inline void flush_writes(const struct fw_ohci *ohci)
252 /* Do a dummy read to flush writes. */
253 reg_read(ohci, OHCI1394_Version);
257 ohci_update_phy_reg(struct fw_card *card, int addr,
258 int clear_bits, int set_bits)
260 struct fw_ohci *ohci = fw_ohci(card);
263 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
266 val = reg_read(ohci, OHCI1394_PhyControl);
267 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
268 fw_error("failed to set phy reg bits.\n");
272 old = OHCI1394_PhyControl_ReadData(val);
273 old = (old & ~clear_bits) | set_bits;
274 reg_write(ohci, OHCI1394_PhyControl,
275 OHCI1394_PhyControl_Write(addr, old));
280 static int ar_context_add_page(struct ar_context *ctx)
282 struct device *dev = ctx->ohci->card.device;
283 struct ar_buffer *ab;
284 dma_addr_t uninitialized_var(ab_bus);
287 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
291 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
292 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
294 DESCRIPTOR_BRANCH_ALWAYS);
295 offset = offsetof(struct ar_buffer, data);
296 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
297 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
298 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
299 ab->descriptor.branch_address = 0;
301 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
302 ctx->last_buffer->next = ab;
303 ctx->last_buffer = ab;
305 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
306 flush_writes(ctx->ohci);
311 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
312 #define cond_le32_to_cpu(v) \
313 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
315 #define cond_le32_to_cpu(v) le32_to_cpu(v)
318 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
320 struct fw_ohci *ohci = ctx->ohci;
322 u32 status, length, tcode;
324 p.header[0] = cond_le32_to_cpu(buffer[0]);
325 p.header[1] = cond_le32_to_cpu(buffer[1]);
326 p.header[2] = cond_le32_to_cpu(buffer[2]);
328 tcode = (p.header[0] >> 4) & 0x0f;
330 case TCODE_WRITE_QUADLET_REQUEST:
331 case TCODE_READ_QUADLET_RESPONSE:
332 p.header[3] = (__force __u32) buffer[3];
333 p.header_length = 16;
334 p.payload_length = 0;
337 case TCODE_READ_BLOCK_REQUEST :
338 p.header[3] = cond_le32_to_cpu(buffer[3]);
339 p.header_length = 16;
340 p.payload_length = 0;
343 case TCODE_WRITE_BLOCK_REQUEST:
344 case TCODE_READ_BLOCK_RESPONSE:
345 case TCODE_LOCK_REQUEST:
346 case TCODE_LOCK_RESPONSE:
347 p.header[3] = cond_le32_to_cpu(buffer[3]);
348 p.header_length = 16;
349 p.payload_length = p.header[3] >> 16;
352 case TCODE_WRITE_RESPONSE:
353 case TCODE_READ_QUADLET_REQUEST:
354 case OHCI_TCODE_PHY_PACKET:
355 p.header_length = 12;
356 p.payload_length = 0;
360 p.payload = (void *) buffer + p.header_length;
362 /* FIXME: What to do about evt_* errors? */
363 length = (p.header_length + p.payload_length + 3) / 4;
364 status = cond_le32_to_cpu(buffer[length]);
366 p.ack = ((status >> 16) & 0x1f) - 16;
367 p.speed = (status >> 21) & 0x7;
368 p.timestamp = status & 0xffff;
369 p.generation = ohci->request_generation;
372 * The OHCI bus reset handler synthesizes a phy packet with
373 * the new generation number when a bus reset happens (see
374 * section 8.4.2.3). This helps us determine when a request
375 * was received and make sure we send the response in the same
376 * generation. We only need this for requests; for responses
377 * we use the unique tlabel for finding the matching
381 if (p.ack + 16 == 0x09)
382 ohci->request_generation = (p.header[2] >> 16) & 0xff;
383 else if (ctx == &ohci->ar_request_ctx)
384 fw_core_handle_request(&ohci->card, &p);
386 fw_core_handle_response(&ohci->card, &p);
388 return buffer + length + 1;
391 static void ar_context_tasklet(unsigned long data)
393 struct ar_context *ctx = (struct ar_context *)data;
394 struct fw_ohci *ohci = ctx->ohci;
395 struct ar_buffer *ab;
396 struct descriptor *d;
399 ab = ctx->current_buffer;
402 if (d->res_count == 0) {
403 size_t size, rest, offset;
404 dma_addr_t start_bus;
408 * This descriptor is finished and we may have a
409 * packet split across this and the next buffer. We
410 * reuse the page for reassembling the split packet.
413 offset = offsetof(struct ar_buffer, data);
415 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
419 size = buffer + PAGE_SIZE - ctx->pointer;
420 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
421 memmove(buffer, ctx->pointer, size);
422 memcpy(buffer + size, ab->data, rest);
423 ctx->current_buffer = ab;
424 ctx->pointer = (void *) ab->data + rest;
425 end = buffer + size + rest;
428 buffer = handle_ar_packet(ctx, buffer);
430 dma_free_coherent(ohci->card.device, PAGE_SIZE,
432 ar_context_add_page(ctx);
434 buffer = ctx->pointer;
436 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
439 buffer = handle_ar_packet(ctx, buffer);
444 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
450 ctx->last_buffer = &ab;
451 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
453 ar_context_add_page(ctx);
454 ar_context_add_page(ctx);
455 ctx->current_buffer = ab.next;
456 ctx->pointer = ctx->current_buffer->data;
461 static void ar_context_run(struct ar_context *ctx)
463 struct ar_buffer *ab = ctx->current_buffer;
467 offset = offsetof(struct ar_buffer, data);
468 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
470 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
471 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
472 flush_writes(ctx->ohci);
475 static struct descriptor *
476 find_branch_descriptor(struct descriptor *d, int z)
480 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
481 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
483 /* figure out which descriptor the branch address goes in */
484 if (z == 2 && (b == 3 || key == 2))
490 static void context_tasklet(unsigned long data)
492 struct context *ctx = (struct context *) data;
493 struct descriptor *d, *last;
496 struct descriptor_buffer *desc;
498 desc = list_entry(ctx->buffer_list.next,
499 struct descriptor_buffer, list);
501 while (last->branch_address != 0) {
502 struct descriptor_buffer *old_desc = desc;
503 address = le32_to_cpu(last->branch_address);
507 /* If the branch address points to a buffer outside of the
508 * current buffer, advance to the next buffer. */
509 if (address < desc->buffer_bus ||
510 address >= desc->buffer_bus + desc->used)
511 desc = list_entry(desc->list.next,
512 struct descriptor_buffer, list);
513 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
514 last = find_branch_descriptor(d, z);
516 if (!ctx->callback(ctx, d, last))
519 if (old_desc != desc) {
520 /* If we've advanced to the next buffer, move the
521 * previous buffer to the free list. */
524 spin_lock_irqsave(&ctx->ohci->lock, flags);
525 list_move_tail(&old_desc->list, &ctx->buffer_list);
526 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
533 * Allocate a new buffer and add it to the list of free buffers for this
534 * context. Must be called with ohci->lock held.
537 context_add_buffer(struct context *ctx)
539 struct descriptor_buffer *desc;
540 dma_addr_t uninitialized_var(bus_addr);
544 * 16MB of descriptors should be far more than enough for any DMA
545 * program. This will catch run-away userspace or DoS attacks.
547 if (ctx->total_allocation >= 16*1024*1024)
550 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
551 &bus_addr, GFP_ATOMIC);
555 offset = (void *)&desc->buffer - (void *)desc;
556 desc->buffer_size = PAGE_SIZE - offset;
557 desc->buffer_bus = bus_addr + offset;
560 list_add_tail(&desc->list, &ctx->buffer_list);
561 ctx->total_allocation += PAGE_SIZE;
567 context_init(struct context *ctx, struct fw_ohci *ohci,
568 u32 regs, descriptor_callback_t callback)
572 ctx->total_allocation = 0;
574 INIT_LIST_HEAD(&ctx->buffer_list);
575 if (context_add_buffer(ctx) < 0)
578 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
579 struct descriptor_buffer, list);
581 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
582 ctx->callback = callback;
585 * We put a dummy descriptor in the buffer that has a NULL
586 * branch address and looks like it's been sent. That way we
587 * have a descriptor to append DMA programs to.
589 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
590 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
591 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
592 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
593 ctx->last = ctx->buffer_tail->buffer;
594 ctx->prev = ctx->buffer_tail->buffer;
600 context_release(struct context *ctx)
602 struct fw_card *card = &ctx->ohci->card;
603 struct descriptor_buffer *desc, *tmp;
605 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
606 dma_free_coherent(card->device, PAGE_SIZE, desc,
608 ((void *)&desc->buffer - (void *)desc));
611 /* Must be called with ohci->lock held */
612 static struct descriptor *
613 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
615 struct descriptor *d = NULL;
616 struct descriptor_buffer *desc = ctx->buffer_tail;
618 if (z * sizeof(*d) > desc->buffer_size)
621 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
622 /* No room for the descriptor in this buffer, so advance to the
625 if (desc->list.next == &ctx->buffer_list) {
626 /* If there is no free buffer next in the list,
628 if (context_add_buffer(ctx) < 0)
631 desc = list_entry(desc->list.next,
632 struct descriptor_buffer, list);
633 ctx->buffer_tail = desc;
636 d = desc->buffer + desc->used / sizeof(*d);
637 memset(d, 0, z * sizeof(*d));
638 *d_bus = desc->buffer_bus + desc->used;
643 static void context_run(struct context *ctx, u32 extra)
645 struct fw_ohci *ohci = ctx->ohci;
647 reg_write(ohci, COMMAND_PTR(ctx->regs),
648 le32_to_cpu(ctx->last->branch_address));
649 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
650 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
654 static void context_append(struct context *ctx,
655 struct descriptor *d, int z, int extra)
658 struct descriptor_buffer *desc = ctx->buffer_tail;
660 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
662 desc->used += (z + extra) * sizeof(*d);
663 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
664 ctx->prev = find_branch_descriptor(d, z);
666 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
667 flush_writes(ctx->ohci);
670 static void context_stop(struct context *ctx)
675 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
676 flush_writes(ctx->ohci);
678 for (i = 0; i < 10; i++) {
679 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
680 if ((reg & CONTEXT_ACTIVE) == 0)
683 fw_notify("context_stop: still active (0x%08x)\n", reg);
689 struct fw_packet *packet;
693 * This function apppends a packet to the DMA queue for transmission.
694 * Must always be called with the ochi->lock held to ensure proper
695 * generation handling and locking around packet queue manipulation.
698 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
700 struct fw_ohci *ohci = ctx->ohci;
701 dma_addr_t d_bus, uninitialized_var(payload_bus);
702 struct driver_data *driver_data;
703 struct descriptor *d, *last;
708 d = context_get_descriptors(ctx, 4, &d_bus);
710 packet->ack = RCODE_SEND_ERROR;
714 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
715 d[0].res_count = cpu_to_le16(packet->timestamp);
718 * The DMA format for asyncronous link packets is different
719 * from the IEEE1394 layout, so shift the fields around
720 * accordingly. If header_length is 8, it's a PHY packet, to
721 * which we need to prepend an extra quadlet.
724 header = (__le32 *) &d[1];
725 if (packet->header_length > 8) {
726 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
727 (packet->speed << 16));
728 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
729 (packet->header[0] & 0xffff0000));
730 header[2] = cpu_to_le32(packet->header[2]);
732 tcode = (packet->header[0] >> 4) & 0x0f;
733 if (TCODE_IS_BLOCK_PACKET(tcode))
734 header[3] = cpu_to_le32(packet->header[3]);
736 header[3] = (__force __le32) packet->header[3];
738 d[0].req_count = cpu_to_le16(packet->header_length);
740 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
741 (packet->speed << 16));
742 header[1] = cpu_to_le32(packet->header[0]);
743 header[2] = cpu_to_le32(packet->header[1]);
744 d[0].req_count = cpu_to_le16(12);
747 driver_data = (struct driver_data *) &d[3];
748 driver_data->packet = packet;
749 packet->driver_data = driver_data;
751 if (packet->payload_length > 0) {
753 dma_map_single(ohci->card.device, packet->payload,
754 packet->payload_length, DMA_TO_DEVICE);
755 if (dma_mapping_error(payload_bus)) {
756 packet->ack = RCODE_SEND_ERROR;
760 d[2].req_count = cpu_to_le16(packet->payload_length);
761 d[2].data_address = cpu_to_le32(payload_bus);
769 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
770 DESCRIPTOR_IRQ_ALWAYS |
771 DESCRIPTOR_BRANCH_ALWAYS);
773 /* FIXME: Document how the locking works. */
774 if (ohci->generation != packet->generation) {
775 if (packet->payload_length > 0)
776 dma_unmap_single(ohci->card.device, payload_bus,
777 packet->payload_length, DMA_TO_DEVICE);
778 packet->ack = RCODE_GENERATION;
782 context_append(ctx, d, z, 4 - z);
784 /* If the context isn't already running, start it up. */
785 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
786 if ((reg & CONTEXT_RUN) == 0)
792 static int handle_at_packet(struct context *context,
793 struct descriptor *d,
794 struct descriptor *last)
796 struct driver_data *driver_data;
797 struct fw_packet *packet;
798 struct fw_ohci *ohci = context->ohci;
799 dma_addr_t payload_bus;
802 if (last->transfer_status == 0)
803 /* This descriptor isn't done yet, stop iteration. */
806 driver_data = (struct driver_data *) &d[3];
807 packet = driver_data->packet;
809 /* This packet was cancelled, just continue. */
812 payload_bus = le32_to_cpu(last->data_address);
813 if (payload_bus != 0)
814 dma_unmap_single(ohci->card.device, payload_bus,
815 packet->payload_length, DMA_TO_DEVICE);
817 evt = le16_to_cpu(last->transfer_status) & 0x1f;
818 packet->timestamp = le16_to_cpu(last->res_count);
821 case OHCI1394_evt_timeout:
822 /* Async response transmit timed out. */
823 packet->ack = RCODE_CANCELLED;
826 case OHCI1394_evt_flushed:
828 * The packet was flushed should give same error as
829 * when we try to use a stale generation count.
831 packet->ack = RCODE_GENERATION;
834 case OHCI1394_evt_missing_ack:
836 * Using a valid (current) generation count, but the
837 * node is not on the bus or not sending acks.
839 packet->ack = RCODE_NO_ACK;
842 case ACK_COMPLETE + 0x10:
843 case ACK_PENDING + 0x10:
844 case ACK_BUSY_X + 0x10:
845 case ACK_BUSY_A + 0x10:
846 case ACK_BUSY_B + 0x10:
847 case ACK_DATA_ERROR + 0x10:
848 case ACK_TYPE_ERROR + 0x10:
849 packet->ack = evt - 0x10;
853 packet->ack = RCODE_SEND_ERROR;
857 packet->callback(packet, &ohci->card, packet->ack);
862 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
863 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
864 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
865 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
866 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
869 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
871 struct fw_packet response;
872 int tcode, length, i;
874 tcode = HEADER_GET_TCODE(packet->header[0]);
875 if (TCODE_IS_BLOCK_PACKET(tcode))
876 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
880 i = csr - CSR_CONFIG_ROM;
881 if (i + length > CONFIG_ROM_SIZE) {
882 fw_fill_response(&response, packet->header,
883 RCODE_ADDRESS_ERROR, NULL, 0);
884 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
885 fw_fill_response(&response, packet->header,
886 RCODE_TYPE_ERROR, NULL, 0);
888 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
889 (void *) ohci->config_rom + i, length);
892 fw_core_handle_response(&ohci->card, &response);
896 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
898 struct fw_packet response;
899 int tcode, length, ext_tcode, sel;
900 __be32 *payload, lock_old;
901 u32 lock_arg, lock_data;
903 tcode = HEADER_GET_TCODE(packet->header[0]);
904 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
905 payload = packet->payload;
906 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
908 if (tcode == TCODE_LOCK_REQUEST &&
909 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
910 lock_arg = be32_to_cpu(payload[0]);
911 lock_data = be32_to_cpu(payload[1]);
912 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
916 fw_fill_response(&response, packet->header,
917 RCODE_TYPE_ERROR, NULL, 0);
921 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
922 reg_write(ohci, OHCI1394_CSRData, lock_data);
923 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
924 reg_write(ohci, OHCI1394_CSRControl, sel);
926 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
927 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
929 fw_notify("swap not done yet\n");
931 fw_fill_response(&response, packet->header,
932 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
934 fw_core_handle_response(&ohci->card, &response);
938 handle_local_request(struct context *ctx, struct fw_packet *packet)
943 if (ctx == &ctx->ohci->at_request_ctx) {
944 packet->ack = ACK_PENDING;
945 packet->callback(packet, &ctx->ohci->card, packet->ack);
949 ((unsigned long long)
950 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
952 csr = offset - CSR_REGISTER_BASE;
954 /* Handle config rom reads. */
955 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
956 handle_local_rom(ctx->ohci, packet, csr);
958 case CSR_BUS_MANAGER_ID:
959 case CSR_BANDWIDTH_AVAILABLE:
960 case CSR_CHANNELS_AVAILABLE_HI:
961 case CSR_CHANNELS_AVAILABLE_LO:
962 handle_local_lock(ctx->ohci, packet, csr);
965 if (ctx == &ctx->ohci->at_request_ctx)
966 fw_core_handle_request(&ctx->ohci->card, packet);
968 fw_core_handle_response(&ctx->ohci->card, packet);
972 if (ctx == &ctx->ohci->at_response_ctx) {
973 packet->ack = ACK_COMPLETE;
974 packet->callback(packet, &ctx->ohci->card, packet->ack);
979 at_context_transmit(struct context *ctx, struct fw_packet *packet)
984 spin_lock_irqsave(&ctx->ohci->lock, flags);
986 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
987 ctx->ohci->generation == packet->generation) {
988 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
989 handle_local_request(ctx, packet);
993 retval = at_context_queue_packet(ctx, packet);
994 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
997 packet->callback(packet, &ctx->ohci->card, packet->ack);
1001 static void bus_reset_tasklet(unsigned long data)
1003 struct fw_ohci *ohci = (struct fw_ohci *)data;
1004 int self_id_count, i, j, reg;
1005 int generation, new_generation;
1006 unsigned long flags;
1007 void *free_rom = NULL;
1008 dma_addr_t free_rom_bus = 0;
1010 reg = reg_read(ohci, OHCI1394_NodeID);
1011 if (!(reg & OHCI1394_NodeID_idValid)) {
1012 fw_notify("node ID not valid, new bus reset in progress\n");
1015 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1016 fw_notify("malconfigured bus\n");
1019 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1020 OHCI1394_NodeID_nodeNumber);
1022 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1023 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1024 fw_notify("inconsistent self IDs\n");
1028 * The count in the SelfIDCount register is the number of
1029 * bytes in the self ID receive buffer. Since we also receive
1030 * the inverted quadlets and a header quadlet, we shift one
1031 * bit extra to get the actual number of self IDs.
1033 self_id_count = (reg >> 3) & 0x3ff;
1034 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1037 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1038 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1039 fw_notify("inconsistent self IDs\n");
1042 ohci->self_id_buffer[j] =
1043 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1048 * Check the consistency of the self IDs we just read. The
1049 * problem we face is that a new bus reset can start while we
1050 * read out the self IDs from the DMA buffer. If this happens,
1051 * the DMA buffer will be overwritten with new self IDs and we
1052 * will read out inconsistent data. The OHCI specification
1053 * (section 11.2) recommends a technique similar to
1054 * linux/seqlock.h, where we remember the generation of the
1055 * self IDs in the buffer before reading them out and compare
1056 * it to the current generation after reading them out. If
1057 * the two generations match we know we have a consistent set
1061 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1062 if (new_generation != generation) {
1063 fw_notify("recursive bus reset detected, "
1064 "discarding self ids\n");
1068 /* FIXME: Document how the locking works. */
1069 spin_lock_irqsave(&ohci->lock, flags);
1071 ohci->generation = generation;
1072 context_stop(&ohci->at_request_ctx);
1073 context_stop(&ohci->at_response_ctx);
1074 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1077 * This next bit is unrelated to the AT context stuff but we
1078 * have to do it under the spinlock also. If a new config rom
1079 * was set up before this reset, the old one is now no longer
1080 * in use and we can free it. Update the config rom pointers
1081 * to point to the current config rom and clear the
1082 * next_config_rom pointer so a new udpate can take place.
1085 if (ohci->next_config_rom != NULL) {
1086 if (ohci->next_config_rom != ohci->config_rom) {
1087 free_rom = ohci->config_rom;
1088 free_rom_bus = ohci->config_rom_bus;
1090 ohci->config_rom = ohci->next_config_rom;
1091 ohci->config_rom_bus = ohci->next_config_rom_bus;
1092 ohci->next_config_rom = NULL;
1095 * Restore config_rom image and manually update
1096 * config_rom registers. Writing the header quadlet
1097 * will indicate that the config rom is ready, so we
1100 reg_write(ohci, OHCI1394_BusOptions,
1101 be32_to_cpu(ohci->config_rom[2]));
1102 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1103 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1106 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1107 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1108 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1111 spin_unlock_irqrestore(&ohci->lock, flags);
1114 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1115 free_rom, free_rom_bus);
1117 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1118 self_id_count, ohci->self_id_buffer);
1121 static irqreturn_t irq_handler(int irq, void *data)
1123 struct fw_ohci *ohci = data;
1124 u32 event, iso_event, cycle_time;
1127 event = reg_read(ohci, OHCI1394_IntEventClear);
1129 if (!event || !~event)
1132 reg_write(ohci, OHCI1394_IntEventClear, event);
1134 if (event & OHCI1394_selfIDComplete)
1135 tasklet_schedule(&ohci->bus_reset_tasklet);
1137 if (event & OHCI1394_RQPkt)
1138 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1140 if (event & OHCI1394_RSPkt)
1141 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1143 if (event & OHCI1394_reqTxComplete)
1144 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1146 if (event & OHCI1394_respTxComplete)
1147 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1149 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1150 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1153 i = ffs(iso_event) - 1;
1154 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1155 iso_event &= ~(1 << i);
1158 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1159 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1162 i = ffs(iso_event) - 1;
1163 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1164 iso_event &= ~(1 << i);
1167 if (unlikely(event & OHCI1394_postedWriteErr))
1168 fw_error("PCI posted write error\n");
1170 if (unlikely(event & OHCI1394_cycleTooLong)) {
1171 if (printk_ratelimit())
1172 fw_notify("isochronous cycle too long\n");
1173 reg_write(ohci, OHCI1394_LinkControlSet,
1174 OHCI1394_LinkControl_cycleMaster);
1177 if (event & OHCI1394_cycle64Seconds) {
1178 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1179 if ((cycle_time & 0x80000000) == 0)
1180 ohci->bus_seconds++;
1186 static int software_reset(struct fw_ohci *ohci)
1190 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1192 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1193 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1194 OHCI1394_HCControl_softReset) == 0)
1202 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1204 struct fw_ohci *ohci = fw_ohci(card);
1205 struct pci_dev *dev = to_pci_dev(card->device);
1207 if (software_reset(ohci)) {
1208 fw_error("Failed to reset ohci card.\n");
1213 * Now enable LPS, which we need in order to start accessing
1214 * most of the registers. In fact, on some cards (ALI M5251),
1215 * accessing registers in the SClk domain without LPS enabled
1216 * will lock up the machine. Wait 50msec to make sure we have
1217 * full link enabled.
1219 reg_write(ohci, OHCI1394_HCControlSet,
1220 OHCI1394_HCControl_LPS |
1221 OHCI1394_HCControl_postedWriteEnable);
1225 reg_write(ohci, OHCI1394_HCControlClear,
1226 OHCI1394_HCControl_noByteSwapData);
1228 reg_write(ohci, OHCI1394_LinkControlSet,
1229 OHCI1394_LinkControl_rcvSelfID |
1230 OHCI1394_LinkControl_cycleTimerEnable |
1231 OHCI1394_LinkControl_cycleMaster);
1233 reg_write(ohci, OHCI1394_ATRetries,
1234 OHCI1394_MAX_AT_REQ_RETRIES |
1235 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1236 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1238 ar_context_run(&ohci->ar_request_ctx);
1239 ar_context_run(&ohci->ar_response_ctx);
1241 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1242 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1243 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1244 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1245 reg_write(ohci, OHCI1394_IntMaskSet,
1246 OHCI1394_selfIDComplete |
1247 OHCI1394_RQPkt | OHCI1394_RSPkt |
1248 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1249 OHCI1394_isochRx | OHCI1394_isochTx |
1250 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1251 OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable);
1253 /* Activate link_on bit and contender bit in our self ID packets.*/
1254 if (ohci_update_phy_reg(card, 4, 0,
1255 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1259 * When the link is not yet enabled, the atomic config rom
1260 * update mechanism described below in ohci_set_config_rom()
1261 * is not active. We have to update ConfigRomHeader and
1262 * BusOptions manually, and the write to ConfigROMmap takes
1263 * effect immediately. We tie this to the enabling of the
1264 * link, so we have a valid config rom before enabling - the
1265 * OHCI requires that ConfigROMhdr and BusOptions have valid
1266 * values before enabling.
1268 * However, when the ConfigROMmap is written, some controllers
1269 * always read back quadlets 0 and 2 from the config rom to
1270 * the ConfigRomHeader and BusOptions registers on bus reset.
1271 * They shouldn't do that in this initial case where the link
1272 * isn't enabled. This means we have to use the same
1273 * workaround here, setting the bus header to 0 and then write
1274 * the right values in the bus reset tasklet.
1278 ohci->next_config_rom =
1279 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1280 &ohci->next_config_rom_bus,
1282 if (ohci->next_config_rom == NULL)
1285 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1286 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1289 * In the suspend case, config_rom is NULL, which
1290 * means that we just reuse the old config rom.
1292 ohci->next_config_rom = ohci->config_rom;
1293 ohci->next_config_rom_bus = ohci->config_rom_bus;
1296 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1297 ohci->next_config_rom[0] = 0;
1298 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1299 reg_write(ohci, OHCI1394_BusOptions,
1300 be32_to_cpu(ohci->next_config_rom[2]));
1301 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1303 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1305 if (request_irq(dev->irq, irq_handler,
1306 IRQF_SHARED, ohci_driver_name, ohci)) {
1307 fw_error("Failed to allocate shared interrupt %d.\n",
1309 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1310 ohci->config_rom, ohci->config_rom_bus);
1314 reg_write(ohci, OHCI1394_HCControlSet,
1315 OHCI1394_HCControl_linkEnable |
1316 OHCI1394_HCControl_BIBimageValid);
1320 * We are ready to go, initiate bus reset to finish the
1324 fw_core_initiate_bus_reset(&ohci->card, 1);
1330 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1332 struct fw_ohci *ohci;
1333 unsigned long flags;
1334 int retval = -EBUSY;
1335 __be32 *next_config_rom;
1336 dma_addr_t uninitialized_var(next_config_rom_bus);
1338 ohci = fw_ohci(card);
1341 * When the OHCI controller is enabled, the config rom update
1342 * mechanism is a bit tricky, but easy enough to use. See
1343 * section 5.5.6 in the OHCI specification.
1345 * The OHCI controller caches the new config rom address in a
1346 * shadow register (ConfigROMmapNext) and needs a bus reset
1347 * for the changes to take place. When the bus reset is
1348 * detected, the controller loads the new values for the
1349 * ConfigRomHeader and BusOptions registers from the specified
1350 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1351 * shadow register. All automatically and atomically.
1353 * Now, there's a twist to this story. The automatic load of
1354 * ConfigRomHeader and BusOptions doesn't honor the
1355 * noByteSwapData bit, so with a be32 config rom, the
1356 * controller will load be32 values in to these registers
1357 * during the atomic update, even on litte endian
1358 * architectures. The workaround we use is to put a 0 in the
1359 * header quadlet; 0 is endian agnostic and means that the
1360 * config rom isn't ready yet. In the bus reset tasklet we
1361 * then set up the real values for the two registers.
1363 * We use ohci->lock to avoid racing with the code that sets
1364 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1368 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1369 &next_config_rom_bus, GFP_KERNEL);
1370 if (next_config_rom == NULL)
1373 spin_lock_irqsave(&ohci->lock, flags);
1375 if (ohci->next_config_rom == NULL) {
1376 ohci->next_config_rom = next_config_rom;
1377 ohci->next_config_rom_bus = next_config_rom_bus;
1379 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1380 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1383 ohci->next_header = config_rom[0];
1384 ohci->next_config_rom[0] = 0;
1386 reg_write(ohci, OHCI1394_ConfigROMmap,
1387 ohci->next_config_rom_bus);
1391 spin_unlock_irqrestore(&ohci->lock, flags);
1394 * Now initiate a bus reset to have the changes take
1395 * effect. We clean up the old config rom memory and DMA
1396 * mappings in the bus reset tasklet, since the OHCI
1397 * controller could need to access it before the bus reset
1401 fw_core_initiate_bus_reset(&ohci->card, 1);
1403 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1404 next_config_rom, next_config_rom_bus);
1409 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1411 struct fw_ohci *ohci = fw_ohci(card);
1413 at_context_transmit(&ohci->at_request_ctx, packet);
1416 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1418 struct fw_ohci *ohci = fw_ohci(card);
1420 at_context_transmit(&ohci->at_response_ctx, packet);
1423 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1425 struct fw_ohci *ohci = fw_ohci(card);
1426 struct context *ctx = &ohci->at_request_ctx;
1427 struct driver_data *driver_data = packet->driver_data;
1428 int retval = -ENOENT;
1430 tasklet_disable(&ctx->tasklet);
1432 if (packet->ack != 0)
1435 driver_data->packet = NULL;
1436 packet->ack = RCODE_CANCELLED;
1437 packet->callback(packet, &ohci->card, packet->ack);
1441 tasklet_enable(&ctx->tasklet);
1447 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1449 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1452 struct fw_ohci *ohci = fw_ohci(card);
1453 unsigned long flags;
1457 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1458 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1461 spin_lock_irqsave(&ohci->lock, flags);
1463 if (ohci->generation != generation) {
1469 * Note, if the node ID contains a non-local bus ID, physical DMA is
1470 * enabled for _all_ nodes on remote buses.
1473 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1475 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1477 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1481 spin_unlock_irqrestore(&ohci->lock, flags);
1483 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1487 ohci_get_bus_time(struct fw_card *card)
1489 struct fw_ohci *ohci = fw_ohci(card);
1493 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1494 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1499 static int handle_ir_dualbuffer_packet(struct context *context,
1500 struct descriptor *d,
1501 struct descriptor *last)
1503 struct iso_context *ctx =
1504 container_of(context, struct iso_context, context);
1505 struct db_descriptor *db = (struct db_descriptor *) d;
1507 size_t header_length;
1511 if (db->first_res_count != 0 && db->second_res_count != 0) {
1512 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1513 /* This descriptor isn't done yet, stop iteration. */
1516 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1519 header_length = le16_to_cpu(db->first_req_count) -
1520 le16_to_cpu(db->first_res_count);
1522 i = ctx->header_length;
1524 end = p + header_length;
1525 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1527 * The iso header is byteswapped to little endian by
1528 * the controller, but the remaining header quadlets
1529 * are big endian. We want to present all the headers
1530 * as big endian, so we have to swap the first
1533 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1534 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1535 i += ctx->base.header_size;
1536 ctx->excess_bytes +=
1537 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1538 p += ctx->base.header_size + 4;
1540 ctx->header_length = i;
1542 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1543 le16_to_cpu(db->second_res_count);
1545 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1546 ir_header = (__le32 *) (db + 1);
1547 ctx->base.callback(&ctx->base,
1548 le32_to_cpu(ir_header[0]) & 0xffff,
1549 ctx->header_length, ctx->header,
1550 ctx->base.callback_data);
1551 ctx->header_length = 0;
1557 static int handle_ir_packet_per_buffer(struct context *context,
1558 struct descriptor *d,
1559 struct descriptor *last)
1561 struct iso_context *ctx =
1562 container_of(context, struct iso_context, context);
1563 struct descriptor *pd;
1568 for (pd = d; pd <= last; pd++) {
1569 if (pd->transfer_status)
1573 /* Descriptor(s) not done yet, stop iteration */
1576 i = ctx->header_length;
1579 if (ctx->base.header_size > 0 &&
1580 i + ctx->base.header_size <= PAGE_SIZE) {
1582 * The iso header is byteswapped to little endian by
1583 * the controller, but the remaining header quadlets
1584 * are big endian. We want to present all the headers
1585 * as big endian, so we have to swap the first quadlet.
1587 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1588 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1589 ctx->header_length += ctx->base.header_size;
1592 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1593 ir_header = (__le32 *) p;
1594 ctx->base.callback(&ctx->base,
1595 le32_to_cpu(ir_header[0]) & 0xffff,
1596 ctx->header_length, ctx->header,
1597 ctx->base.callback_data);
1598 ctx->header_length = 0;
1604 static int handle_it_packet(struct context *context,
1605 struct descriptor *d,
1606 struct descriptor *last)
1608 struct iso_context *ctx =
1609 container_of(context, struct iso_context, context);
1611 if (last->transfer_status == 0)
1612 /* This descriptor isn't done yet, stop iteration. */
1615 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1616 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1617 0, NULL, ctx->base.callback_data);
1622 static struct fw_iso_context *
1623 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1625 struct fw_ohci *ohci = fw_ohci(card);
1626 struct iso_context *ctx, *list;
1627 descriptor_callback_t callback;
1629 unsigned long flags;
1630 int index, retval = -ENOMEM;
1632 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1633 mask = &ohci->it_context_mask;
1634 list = ohci->it_context_list;
1635 callback = handle_it_packet;
1637 mask = &ohci->ir_context_mask;
1638 list = ohci->ir_context_list;
1639 if (ohci->version >= OHCI_VERSION_1_1)
1640 callback = handle_ir_dualbuffer_packet;
1642 callback = handle_ir_packet_per_buffer;
1645 spin_lock_irqsave(&ohci->lock, flags);
1646 index = ffs(*mask) - 1;
1648 *mask &= ~(1 << index);
1649 spin_unlock_irqrestore(&ohci->lock, flags);
1652 return ERR_PTR(-EBUSY);
1654 if (type == FW_ISO_CONTEXT_TRANSMIT)
1655 regs = OHCI1394_IsoXmitContextBase(index);
1657 regs = OHCI1394_IsoRcvContextBase(index);
1660 memset(ctx, 0, sizeof(*ctx));
1661 ctx->header_length = 0;
1662 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1663 if (ctx->header == NULL)
1666 retval = context_init(&ctx->context, ohci, regs, callback);
1668 goto out_with_header;
1673 free_page((unsigned long)ctx->header);
1675 spin_lock_irqsave(&ohci->lock, flags);
1676 *mask |= 1 << index;
1677 spin_unlock_irqrestore(&ohci->lock, flags);
1679 return ERR_PTR(retval);
1682 static int ohci_start_iso(struct fw_iso_context *base,
1683 s32 cycle, u32 sync, u32 tags)
1685 struct iso_context *ctx = container_of(base, struct iso_context, base);
1686 struct fw_ohci *ohci = ctx->context.ohci;
1690 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1691 index = ctx - ohci->it_context_list;
1694 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1695 (cycle & 0x7fff) << 16;
1697 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1698 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1699 context_run(&ctx->context, match);
1701 index = ctx - ohci->ir_context_list;
1702 control = IR_CONTEXT_ISOCH_HEADER;
1703 if (ohci->version >= OHCI_VERSION_1_1)
1704 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1705 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1707 match |= (cycle & 0x07fff) << 12;
1708 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1711 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1712 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1713 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1714 context_run(&ctx->context, control);
1720 static int ohci_stop_iso(struct fw_iso_context *base)
1722 struct fw_ohci *ohci = fw_ohci(base->card);
1723 struct iso_context *ctx = container_of(base, struct iso_context, base);
1726 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1727 index = ctx - ohci->it_context_list;
1728 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1730 index = ctx - ohci->ir_context_list;
1731 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1734 context_stop(&ctx->context);
1739 static void ohci_free_iso_context(struct fw_iso_context *base)
1741 struct fw_ohci *ohci = fw_ohci(base->card);
1742 struct iso_context *ctx = container_of(base, struct iso_context, base);
1743 unsigned long flags;
1746 ohci_stop_iso(base);
1747 context_release(&ctx->context);
1748 free_page((unsigned long)ctx->header);
1750 spin_lock_irqsave(&ohci->lock, flags);
1752 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1753 index = ctx - ohci->it_context_list;
1754 ohci->it_context_mask |= 1 << index;
1756 index = ctx - ohci->ir_context_list;
1757 ohci->ir_context_mask |= 1 << index;
1760 spin_unlock_irqrestore(&ohci->lock, flags);
1764 ohci_queue_iso_transmit(struct fw_iso_context *base,
1765 struct fw_iso_packet *packet,
1766 struct fw_iso_buffer *buffer,
1767 unsigned long payload)
1769 struct iso_context *ctx = container_of(base, struct iso_context, base);
1770 struct descriptor *d, *last, *pd;
1771 struct fw_iso_packet *p;
1773 dma_addr_t d_bus, page_bus;
1774 u32 z, header_z, payload_z, irq;
1775 u32 payload_index, payload_end_index, next_page_index;
1776 int page, end_page, i, length, offset;
1779 * FIXME: Cycle lost behavior should be configurable: lose
1780 * packet, retransmit or terminate..
1784 payload_index = payload;
1790 if (p->header_length > 0)
1793 /* Determine the first page the payload isn't contained in. */
1794 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1795 if (p->payload_length > 0)
1796 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1802 /* Get header size in number of descriptors. */
1803 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1805 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1810 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1811 d[0].req_count = cpu_to_le16(8);
1813 header = (__le32 *) &d[1];
1814 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1815 IT_HEADER_TAG(p->tag) |
1816 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1817 IT_HEADER_CHANNEL(ctx->base.channel) |
1818 IT_HEADER_SPEED(ctx->base.speed));
1820 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
1821 p->payload_length));
1824 if (p->header_length > 0) {
1825 d[2].req_count = cpu_to_le16(p->header_length);
1826 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
1827 memcpy(&d[z], p->header, p->header_length);
1830 pd = d + z - payload_z;
1831 payload_end_index = payload_index + p->payload_length;
1832 for (i = 0; i < payload_z; i++) {
1833 page = payload_index >> PAGE_SHIFT;
1834 offset = payload_index & ~PAGE_MASK;
1835 next_page_index = (page + 1) << PAGE_SHIFT;
1837 min(next_page_index, payload_end_index) - payload_index;
1838 pd[i].req_count = cpu_to_le16(length);
1840 page_bus = page_private(buffer->pages[page]);
1841 pd[i].data_address = cpu_to_le32(page_bus + offset);
1843 payload_index += length;
1847 irq = DESCRIPTOR_IRQ_ALWAYS;
1849 irq = DESCRIPTOR_NO_IRQ;
1851 last = z == 2 ? d : d + z - 1;
1852 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1854 DESCRIPTOR_BRANCH_ALWAYS |
1857 context_append(&ctx->context, d, z, header_z);
1863 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1864 struct fw_iso_packet *packet,
1865 struct fw_iso_buffer *buffer,
1866 unsigned long payload)
1868 struct iso_context *ctx = container_of(base, struct iso_context, base);
1869 struct db_descriptor *db = NULL;
1870 struct descriptor *d;
1871 struct fw_iso_packet *p;
1872 dma_addr_t d_bus, page_bus;
1873 u32 z, header_z, length, rest;
1874 int page, offset, packet_count, header_size;
1877 * FIXME: Cycle lost behavior should be configurable: lose
1878 * packet, retransmit or terminate..
1885 * The OHCI controller puts the status word in the header
1886 * buffer too, so we need 4 extra bytes per packet.
1888 packet_count = p->header_length / ctx->base.header_size;
1889 header_size = packet_count * (ctx->base.header_size + 4);
1891 /* Get header size in number of descriptors. */
1892 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1893 page = payload >> PAGE_SHIFT;
1894 offset = payload & ~PAGE_MASK;
1895 rest = p->payload_length;
1897 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1899 d = context_get_descriptors(&ctx->context,
1900 z + header_z, &d_bus);
1904 db = (struct db_descriptor *) d;
1905 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1906 DESCRIPTOR_BRANCH_ALWAYS);
1907 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1908 if (p->skip && rest == p->payload_length) {
1909 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
1910 db->first_req_count = db->first_size;
1912 db->first_req_count = cpu_to_le16(header_size);
1914 db->first_res_count = db->first_req_count;
1915 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
1917 if (p->skip && rest == p->payload_length)
1919 else if (offset + rest < PAGE_SIZE)
1922 length = PAGE_SIZE - offset;
1924 db->second_req_count = cpu_to_le16(length);
1925 db->second_res_count = db->second_req_count;
1926 page_bus = page_private(buffer->pages[page]);
1927 db->second_buffer = cpu_to_le32(page_bus + offset);
1929 if (p->interrupt && length == rest)
1930 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1932 context_append(&ctx->context, d, z, header_z);
1933 offset = (offset + length) & ~PAGE_MASK;
1943 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
1944 struct fw_iso_packet *packet,
1945 struct fw_iso_buffer *buffer,
1946 unsigned long payload)
1948 struct iso_context *ctx = container_of(base, struct iso_context, base);
1949 struct descriptor *d = NULL, *pd = NULL;
1950 struct fw_iso_packet *p = packet;
1951 dma_addr_t d_bus, page_bus;
1952 u32 z, header_z, rest;
1954 int page, offset, packet_count, header_size, payload_per_buffer;
1957 * The OHCI controller puts the status word in the
1958 * buffer too, so we need 4 extra bytes per packet.
1960 packet_count = p->header_length / ctx->base.header_size;
1961 header_size = ctx->base.header_size + 4;
1963 /* Get header size in number of descriptors. */
1964 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1965 page = payload >> PAGE_SHIFT;
1966 offset = payload & ~PAGE_MASK;
1967 payload_per_buffer = p->payload_length / packet_count;
1969 for (i = 0; i < packet_count; i++) {
1970 /* d points to the header descriptor */
1971 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
1972 d = context_get_descriptors(&ctx->context,
1973 z + header_z, &d_bus);
1977 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
1978 DESCRIPTOR_INPUT_MORE);
1979 if (p->skip && i == 0)
1980 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
1981 d->req_count = cpu_to_le16(header_size);
1982 d->res_count = d->req_count;
1983 d->transfer_status = 0;
1984 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
1986 rest = payload_per_buffer;
1987 for (j = 1; j < z; j++) {
1989 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
1990 DESCRIPTOR_INPUT_MORE);
1992 if (offset + rest < PAGE_SIZE)
1995 length = PAGE_SIZE - offset;
1996 pd->req_count = cpu_to_le16(length);
1997 pd->res_count = pd->req_count;
1998 pd->transfer_status = 0;
2000 page_bus = page_private(buffer->pages[page]);
2001 pd->data_address = cpu_to_le32(page_bus + offset);
2003 offset = (offset + length) & ~PAGE_MASK;
2008 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2009 DESCRIPTOR_INPUT_LAST |
2010 DESCRIPTOR_BRANCH_ALWAYS);
2011 if (p->interrupt && i == packet_count - 1)
2012 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2014 context_append(&ctx->context, d, z, header_z);
2021 ohci_queue_iso(struct fw_iso_context *base,
2022 struct fw_iso_packet *packet,
2023 struct fw_iso_buffer *buffer,
2024 unsigned long payload)
2026 struct iso_context *ctx = container_of(base, struct iso_context, base);
2027 unsigned long flags;
2030 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2031 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2032 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2033 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2034 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2037 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2040 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2045 static const struct fw_card_driver ohci_driver = {
2046 .name = ohci_driver_name,
2047 .enable = ohci_enable,
2048 .update_phy_reg = ohci_update_phy_reg,
2049 .set_config_rom = ohci_set_config_rom,
2050 .send_request = ohci_send_request,
2051 .send_response = ohci_send_response,
2052 .cancel_packet = ohci_cancel_packet,
2053 .enable_phys_dma = ohci_enable_phys_dma,
2054 .get_bus_time = ohci_get_bus_time,
2056 .allocate_iso_context = ohci_allocate_iso_context,
2057 .free_iso_context = ohci_free_iso_context,
2058 .queue_iso = ohci_queue_iso,
2059 .start_iso = ohci_start_iso,
2060 .stop_iso = ohci_stop_iso,
2063 #ifdef CONFIG_PPC_PMAC
2064 static void ohci_pmac_on(struct pci_dev *dev)
2066 if (machine_is(powermac)) {
2067 struct device_node *ofn = pci_device_to_OF_node(dev);
2070 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2071 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2076 static void ohci_pmac_off(struct pci_dev *dev)
2078 if (machine_is(powermac)) {
2079 struct device_node *ofn = pci_device_to_OF_node(dev);
2082 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2083 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2088 #define ohci_pmac_on(dev)
2089 #define ohci_pmac_off(dev)
2090 #endif /* CONFIG_PPC_PMAC */
2092 static int __devinit
2093 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2095 struct fw_ohci *ohci;
2096 u32 bus_options, max_receive, link_speed;
2103 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2105 fw_error("Could not malloc fw_ohci data.\n");
2109 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2111 err = pci_enable_device(dev);
2113 fw_error("Failed to enable OHCI hardware.\n");
2117 pci_set_master(dev);
2118 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2119 pci_set_drvdata(dev, ohci);
2121 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2122 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2123 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2125 spin_lock_init(&ohci->lock);
2127 tasklet_init(&ohci->bus_reset_tasklet,
2128 bus_reset_tasklet, (unsigned long)ohci);
2130 err = pci_request_region(dev, 0, ohci_driver_name);
2132 fw_error("MMIO resource unavailable\n");
2136 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2137 if (ohci->registers == NULL) {
2138 fw_error("Failed to remap registers\n");
2143 ar_context_init(&ohci->ar_request_ctx, ohci,
2144 OHCI1394_AsReqRcvContextControlSet);
2146 ar_context_init(&ohci->ar_response_ctx, ohci,
2147 OHCI1394_AsRspRcvContextControlSet);
2149 context_init(&ohci->at_request_ctx, ohci,
2150 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2152 context_init(&ohci->at_response_ctx, ohci,
2153 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2155 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2156 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2157 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2158 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2159 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2161 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2162 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2163 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2164 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2165 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2167 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2168 fw_error("Out of memory for it/ir contexts.\n");
2170 goto fail_registers;
2173 /* self-id dma buffer allocation */
2174 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2178 if (ohci->self_id_cpu == NULL) {
2179 fw_error("Out of memory for self ID buffer.\n");
2181 goto fail_registers;
2184 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2185 max_receive = (bus_options >> 12) & 0xf;
2186 link_speed = bus_options & 0x7;
2187 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2188 reg_read(ohci, OHCI1394_GUIDLo);
2190 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2194 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2195 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2196 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2200 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2201 ohci->self_id_cpu, ohci->self_id_bus);
2203 kfree(ohci->it_context_list);
2204 kfree(ohci->ir_context_list);
2205 pci_iounmap(dev, ohci->registers);
2207 pci_release_region(dev, 0);
2209 pci_disable_device(dev);
2216 static void pci_remove(struct pci_dev *dev)
2218 struct fw_ohci *ohci;
2220 ohci = pci_get_drvdata(dev);
2221 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2223 fw_core_remove_card(&ohci->card);
2226 * FIXME: Fail all pending packets here, now that the upper
2227 * layers can't queue any more.
2230 software_reset(ohci);
2231 free_irq(dev->irq, ohci);
2232 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2233 ohci->self_id_cpu, ohci->self_id_bus);
2234 kfree(ohci->it_context_list);
2235 kfree(ohci->ir_context_list);
2236 pci_iounmap(dev, ohci->registers);
2237 pci_release_region(dev, 0);
2238 pci_disable_device(dev);
2242 fw_notify("Removed fw-ohci device.\n");
2246 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2248 struct fw_ohci *ohci = pci_get_drvdata(dev);
2251 software_reset(ohci);
2252 free_irq(dev->irq, ohci);
2253 err = pci_save_state(dev);
2255 fw_error("pci_save_state failed\n");
2258 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2260 fw_error("pci_set_power_state failed with %d\n", err);
2266 static int pci_resume(struct pci_dev *dev)
2268 struct fw_ohci *ohci = pci_get_drvdata(dev);
2272 pci_set_power_state(dev, PCI_D0);
2273 pci_restore_state(dev);
2274 err = pci_enable_device(dev);
2276 fw_error("pci_enable_device failed\n");
2280 return ohci_enable(&ohci->card, NULL, 0);
2284 static struct pci_device_id pci_table[] = {
2285 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2289 MODULE_DEVICE_TABLE(pci, pci_table);
2291 static struct pci_driver fw_ohci_pci_driver = {
2292 .name = ohci_driver_name,
2293 .id_table = pci_table,
2295 .remove = pci_remove,
2297 .resume = pci_resume,
2298 .suspend = pci_suspend,
2302 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2303 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2304 MODULE_LICENSE("GPL");
2306 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2307 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2308 MODULE_ALIAS("ohci1394");
2311 static int __init fw_ohci_init(void)
2313 return pci_register_driver(&fw_ohci_pci_driver);
2316 static void __exit fw_ohci_cleanup(void)
2318 pci_unregister_driver(&fw_ohci_pci_driver);
2321 module_init(fw_ohci_init);
2322 module_exit(fw_ohci_cleanup);