drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/firewire.h>
  26 #include <linux/firewire-constants.h>
  27 #include <linux/gfp.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/pci.h>
  37 #include <linux/pci_ids.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/string.h>
  40
  41 #include <asm/atomic.h>
  42 #include <asm/byteorder.h>
  43 #include <asm/page.h>
  44 #include <asm/system.h>
  45
  46 #ifdef CONFIG_PPC_PMAC
  47 #include <asm/pmac_feature.h>
  48 #endif
  49
  50 #include "core.h"
  51 #include "ohci.h"
  52
  53 #define DESCRIPTOR_OUTPUT_MORE          0
  54 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  55 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  56 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  57 #define DESCRIPTOR_STATUS               (1 << 11)
  58 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  59 #define DESCRIPTOR_PING                 (1 << 7)
  60 #define DESCRIPTOR_YY                   (1 << 6)
  61 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  62 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  63 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  64 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  65 #define DESCRIPTOR_WAIT                 (3 << 0)
  66
  67 struct descriptor {
  68         __le16 req_count;
  69         __le16 control;
  70         __le32 data_address;
  71         __le32 branch_address;
  72         __le16 res_count;
  73         __le16 transfer_status;
  74 } __attribute__((aligned(16)));
  75
  76 struct db_descriptor {
  77         __le16 first_size;
  78         __le16 control;
  79         __le16 second_req_count;
  80         __le16 first_req_count;
  81         __le32 branch_address;
  82         __le16 second_res_count;
  83         __le16 first_res_count;
  84         __le32 reserved0;
  85         __le32 first_buffer;
  86         __le32 second_buffer;
  87         __le32 reserved1;
  88 } __attribute__((aligned(16)));
  89
  90 #define CONTROL_SET(regs)       (regs)
  91 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  92 #define COMMAND_PTR(regs)       ((regs) + 12)
  93 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  94
  95 struct ar_buffer {
  96         struct descriptor descriptor;
  97         struct ar_buffer *next;
  98         __le32 data[0];
  99 };
 100
 101 struct ar_context {
 102         struct fw_ohci *ohci;
 103         struct ar_buffer *current_buffer;
 104         struct ar_buffer *last_buffer;
 105         void *pointer;
 106         u32 regs;
 107         struct tasklet_struct tasklet;
 108 };
 109
 110 struct context;
 111
 112 typedef int (*descriptor_callback_t)(struct context *ctx,
 113                                      struct descriptor *d,
 114                                      struct descriptor *last);
 115
 116 /*
 117  * A buffer that contains a block of DMA-able coherent memory used for
 118  * storing a portion of a DMA descriptor program.
 119  */
 120 struct descriptor_buffer {
 121         struct list_head list;
 122         dma_addr_t buffer_bus;
 123         size_t buffer_size;
 124         size_t used;
 125         struct descriptor buffer[0];
 126 };
 127
 128 struct context {
 129         struct fw_ohci *ohci;
 130         u32 regs;
 131         int total_allocation;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor in the DMA program.  It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157
 158         descriptor_callback_t callback;
 159
 160         struct tasklet_struct tasklet;
 161 };
 162
 163 #define IT_HEADER_SY(v)          ((v) <<  0)
 164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 166 #define IT_HEADER_TAG(v)         ((v) << 14)
 167 #define IT_HEADER_SPEED(v)       ((v) << 16)
 168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 169
 170 struct iso_context {
 171         struct fw_iso_context base;
 172         struct context context;
 173         int excess_bytes;
 174         void *header;
 175         size_t header_length;
 176 };
 177
 178 #define CONFIG_ROM_SIZE 1024
 179
 180 struct fw_ohci {
 181         struct fw_card card;
 182
 183         __iomem char *registers;
 184         dma_addr_t self_id_bus;
 185         __le32 *self_id_cpu;
 186         struct tasklet_struct bus_reset_tasklet;
 187         int node_id;
 188         int generation;
 189         int request_generation; /* for timestamping incoming requests */
 190         atomic_t bus_seconds;
 191
 192         bool use_dualbuffer;
 193         bool old_uninorth;
 194         bool bus_reset_packet_quirk;
 195
 196         /*
 197          * Spinlock for accessing fw_ohci data.  Never call out of
 198          * this driver with this lock held.
 199          */
 200         spinlock_t lock;
 201         u32 self_id_buffer[512];
 202
 203         /* Config rom buffers */
 204         __be32 *config_rom;
 205         dma_addr_t config_rom_bus;
 206         __be32 *next_config_rom;
 207         dma_addr_t next_config_rom_bus;
 208         u32 next_header;
 209
 210         struct ar_context ar_request_ctx;
 211         struct ar_context ar_response_ctx;
 212         struct context at_request_ctx;
 213         struct context at_response_ctx;
 214
 215         u32 it_context_mask;
 216         struct iso_context *it_context_list;
 217         u64 ir_context_channels;
 218         u32 ir_context_mask;
 219         struct iso_context *ir_context_list;
 220 };
 221
 222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 223 {
 224         return container_of(card, struct fw_ohci, card);
 225 }
 226
 227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 228 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 229 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 231 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 232 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 233
 234 #define CONTEXT_RUN     0x8000
 235 #define CONTEXT_WAKE    0x1000
 236 #define CONTEXT_DEAD    0x0800
 237 #define CONTEXT_ACTIVE  0x0400
 238
 239 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 240 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 241 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 242
 243 #define OHCI1394_REGISTER_SIZE          0x800
 244 #define OHCI_LOOP_COUNT                 500
 245 #define OHCI1394_PCI_HCI_Control        0x40
 246 #define SELF_ID_BUF_SIZE                0x800
 247 #define OHCI_TCODE_PHY_PACKET           0x0e
 248 #define OHCI_VERSION_1_1                0x010010
 249
 250 static char ohci_driver_name[] = KBUILD_MODNAME;
 251
 252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 253
 254 #define OHCI_PARAM_DEBUG_AT_AR          1
 255 #define OHCI_PARAM_DEBUG_SELFIDS        2
 256 #define OHCI_PARAM_DEBUG_IRQS           4
 257 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 258
 259 static int param_debug;
 260 module_param_named(debug, param_debug, int, 0644);
 261 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 262         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 263         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 264         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 265         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 266         ", or a combination, or all = -1)");
 267
 268 static void log_irqs(u32 evt)
 269 {
 270         if (likely(!(param_debug &
 271                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 272                 return;
 273
 274         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 275             !(evt & OHCI1394_busReset))
 276                 return;
 277
 278         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 279             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 280             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 281             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 282             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 283             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 284             evt & OHCI1394_isochRx              ? " IR"                 : "",
 285             evt & OHCI1394_isochTx              ? " IT"                 : "",
 286             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 287             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 288             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 289             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 290             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 291             evt & OHCI1394_busReset             ? " busReset"           : "",
 292             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 293                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 294                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 295                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 296                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 297                     OHCI1394_cycleInconsistent |
 298                     OHCI1394_regAccessFail | OHCI1394_busReset)
 299                                                 ? " ?"                  : "");
 300 }
 301
 302 static const char *speed[] = {
 303         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 304 };
 305 static const char *power[] = {
 306         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 307         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 308 };
 309 static const char port[] = { '.', '-', 'p', 'c', };
 310
 311 static char _p(u32 *s, int shift)
 312 {
 313         return port[*s >> shift & 3];
 314 }
 315
 316 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 317 {
 318         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 319                 return;
 320
 321         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 322                   self_id_count, generation, node_id);
 323
 324         for (; self_id_count--; ++s)
 325                 if ((*s & 1 << 23) == 0)
 326                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 327                             "%s gc=%d %s %s%s%s\n",
 328                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 329                             speed[*s >> 14 & 3], *s >> 16 & 63,
 330                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 331                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 332                 else
 333                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 334                             *s, *s >> 24 & 63,
 335                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 336                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 337 }
 338
 339 static const char *evts[] = {
 340         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 341         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 342         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 343         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 344         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 345         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 346         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 347         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 348         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 349         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 350         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 351         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 352         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 353         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 354         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 355         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 356         [0x20] = "pending/cancelled",
 357 };
 358 static const char *tcodes[] = {
 359         [0x0] = "QW req",               [0x1] = "BW req",
 360         [0x2] = "W resp",               [0x3] = "-reserved-",
 361         [0x4] = "QR req",               [0x5] = "BR req",
 362         [0x6] = "QR resp",              [0x7] = "BR resp",
 363         [0x8] = "cycle start",          [0x9] = "Lk req",
 364         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 365         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 366         [0xe] = "link internal",        [0xf] = "-reserved-",
 367 };
 368 static const char *phys[] = {
 369         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 370         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 371 };
 372
 373 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 374 {
 375         int tcode = header[0] >> 4 & 0xf;
 376         char specific[12];
 377
 378         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 379                 return;
 380
 381         if (unlikely(evt >= ARRAY_SIZE(evts)))
 382                         evt = 0x1f;
 383
 384         if (evt == OHCI1394_evt_bus_reset) {
 385                 fw_notify("A%c evt_bus_reset, generation %d\n",
 386                     dir, (header[2] >> 16) & 0xff);
 387                 return;
 388         }
 389
 390         if (header[0] == ~header[1]) {
 391                 fw_notify("A%c %s, %s, %08x\n",
 392                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 393                 return;
 394         }
 395
 396         switch (tcode) {
 397         case 0x0: case 0x6: case 0x8:
 398                 snprintf(specific, sizeof(specific), " = %08x",
 399                          be32_to_cpu((__force __be32)header[3]));
 400                 break;
 401         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 402                 snprintf(specific, sizeof(specific), " %x,%x",
 403                          header[3] >> 16, header[3] & 0xffff);
 404                 break;
 405         default:
 406                 specific[0] = '\0';
 407         }
 408
 409         switch (tcode) {
 410         case 0xe: case 0xa:
 411                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 412                 break;
 413         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 414                 fw_notify("A%c spd %x tl %02x, "
 415                     "%04x -> %04x, %s, "
 416                     "%s, %04x%08x%s\n",
 417                     dir, speed, header[0] >> 10 & 0x3f,
 418                     header[1] >> 16, header[0] >> 16, evts[evt],
 419                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 420                 break;
 421         default:
 422                 fw_notify("A%c spd %x tl %02x, "
 423                     "%04x -> %04x, %s, "
 424                     "%s%s\n",
 425                     dir, speed, header[0] >> 10 & 0x3f,
 426                     header[1] >> 16, header[0] >> 16, evts[evt],
 427                     tcodes[tcode], specific);
 428         }
 429 }
 430
 431 #else
 432
 433 #define log_irqs(evt)
 434 #define log_selfids(node_id, generation, self_id_count, sid)
 435 #define log_ar_at_event(dir, speed, header, evt)
 436
 437 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 438
 439 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 440 {
 441         writel(data, ohci->registers + offset);
 442 }
 443
 444 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 445 {
 446         return readl(ohci->registers + offset);
 447 }
 448
 449 static inline void flush_writes(const struct fw_ohci *ohci)
 450 {
 451         /* Do a dummy read to flush writes. */
 452         reg_read(ohci, OHCI1394_Version);
 453 }
 454
 455 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 456                                int clear_bits, int set_bits)
 457 {
 458         struct fw_ohci *ohci = fw_ohci(card);
 459         u32 val, old;
 460
 461         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 462         flush_writes(ohci);
 463         msleep(2);
 464         val = reg_read(ohci, OHCI1394_PhyControl);
 465         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 466                 fw_error("failed to set phy reg bits.\n");
 467                 return -EBUSY;
 468         }
 469
 470         old = OHCI1394_PhyControl_ReadData(val);
 471         old = (old & ~clear_bits) | set_bits;
 472         reg_write(ohci, OHCI1394_PhyControl,
 473                   OHCI1394_PhyControl_Write(addr, old));
 474
 475         return 0;
 476 }
 477
 478 static int ar_context_add_page(struct ar_context *ctx)
 479 {
 480         struct device *dev = ctx->ohci->card.device;
 481         struct ar_buffer *ab;
 482         dma_addr_t uninitialized_var(ab_bus);
 483         size_t offset;
 484
 485         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 486         if (ab == NULL)
 487                 return -ENOMEM;
 488
 489         ab->next = NULL;
 490         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 491         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 492                                                     DESCRIPTOR_STATUS |
 493                                                     DESCRIPTOR_BRANCH_ALWAYS);
 494         offset = offsetof(struct ar_buffer, data);
 495         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 496         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 497         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 498         ab->descriptor.branch_address = 0;
 499
 500         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 501         ctx->last_buffer->next = ab;
 502         ctx->last_buffer = ab;
 503
 504         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 505         flush_writes(ctx->ohci);
 506
 507         return 0;
 508 }
 509
 510 static void ar_context_release(struct ar_context *ctx)
 511 {
 512         struct ar_buffer *ab, *ab_next;
 513         size_t offset;
 514         dma_addr_t ab_bus;
 515
 516         for (ab = ctx->current_buffer; ab; ab = ab_next) {
 517                 ab_next = ab->next;
 518                 offset = offsetof(struct ar_buffer, data);
 519                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 520                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
 521                                   ab, ab_bus);
 522         }
 523 }
 524
 525 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 526 #define cond_le32_to_cpu(v) \
 527         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
 528 #else
 529 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 530 #endif
 531
 532 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 533 {
 534         struct fw_ohci *ohci = ctx->ohci;
 535         struct fw_packet p;
 536         u32 status, length, tcode;
 537         int evt;
 538
 539         p.header[0] = cond_le32_to_cpu(buffer[0]);
 540         p.header[1] = cond_le32_to_cpu(buffer[1]);
 541         p.header[2] = cond_le32_to_cpu(buffer[2]);
 542
 543         tcode = (p.header[0] >> 4) & 0x0f;
 544         switch (tcode) {
 545         case TCODE_WRITE_QUADLET_REQUEST:
 546         case TCODE_READ_QUADLET_RESPONSE:
 547                 p.header[3] = (__force __u32) buffer[3];
 548                 p.header_length = 16;
 549                 p.payload_length = 0;
 550                 break;
 551
 552         case TCODE_READ_BLOCK_REQUEST :
 553                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 554                 p.header_length = 16;
 555                 p.payload_length = 0;
 556                 break;
 557
 558         case TCODE_WRITE_BLOCK_REQUEST:
 559         case TCODE_READ_BLOCK_RESPONSE:
 560         case TCODE_LOCK_REQUEST:
 561         case TCODE_LOCK_RESPONSE:
 562                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 563                 p.header_length = 16;
 564                 p.payload_length = p.header[3] >> 16;
 565                 break;
 566
 567         case TCODE_WRITE_RESPONSE:
 568         case TCODE_READ_QUADLET_REQUEST:
 569         case OHCI_TCODE_PHY_PACKET:
 570                 p.header_length = 12;
 571                 p.payload_length = 0;
 572                 break;
 573
 574         default:
 575                 /* FIXME: Stop context, discard everything, and restart? */
 576                 p.header_length = 0;
 577                 p.payload_length = 0;
 578         }
 579
 580         p.payload = (void *) buffer + p.header_length;
 581
 582         /* FIXME: What to do about evt_* errors? */
 583         length = (p.header_length + p.payload_length + 3) / 4;
 584         status = cond_le32_to_cpu(buffer[length]);
 585         evt    = (status >> 16) & 0x1f;
 586
 587         p.ack        = evt - 16;
 588         p.speed      = (status >> 21) & 0x7;
 589         p.timestamp  = status & 0xffff;
 590         p.generation = ohci->request_generation;
 591
 592         log_ar_at_event('R', p.speed, p.header, evt);
 593
 594         /*
 595          * The OHCI bus reset handler synthesizes a phy packet with
 596          * the new generation number when a bus reset happens (see
 597          * section 8.4.2.3).  This helps us determine when a request
 598          * was received and make sure we send the response in the same
 599          * generation.  We only need this for requests; for responses
 600          * we use the unique tlabel for finding the matching
 601          * request.
 602          *
 603          * Alas some chips sometimes emit bus reset packets with a
 604          * wrong generation.  We set the correct generation for these
 605          * at a slightly incorrect time (in bus_reset_tasklet).
 606          */
 607         if (evt == OHCI1394_evt_bus_reset) {
 608                 if (!ohci->bus_reset_packet_quirk)
 609                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 610         } else if (ctx == &ohci->ar_request_ctx) {
 611                 fw_core_handle_request(&ohci->card, &p);
 612         } else {
 613                 fw_core_handle_response(&ohci->card, &p);
 614         }
 615
 616         return buffer + length + 1;
 617 }
 618
 619 static void ar_context_tasklet(unsigned long data)
 620 {
 621         struct ar_context *ctx = (struct ar_context *)data;
 622         struct fw_ohci *ohci = ctx->ohci;
 623         struct ar_buffer *ab;
 624         struct descriptor *d;
 625         void *buffer, *end;
 626
 627         ab = ctx->current_buffer;
 628         d = &ab->descriptor;
 629
 630         if (d->res_count == 0) {
 631                 size_t size, size2, rest, pktsize, size3, offset;
 632                 dma_addr_t start_bus;
 633                 void *start;
 634
 635                 /*
 636                  * This descriptor is finished and we may have a
 637                  * packet split across this and the next buffer. We
 638                  * reuse the page for reassembling the split packet.
 639                  */
 640
 641                 offset = offsetof(struct ar_buffer, data);
 642                 start = buffer = ab;
 643                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 644
 645                 ab = ab->next;
 646                 d = &ab->descriptor;
 647                 size = buffer + PAGE_SIZE - ctx->pointer;
 648                 /* valid buffer data in the next page */
 649                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 650                 /* what actually fits in this page */
 651                 size2 = min(rest, (size_t)PAGE_SIZE - size);
 652                 memmove(buffer, ctx->pointer, size);
 653                 memcpy(buffer + size, ab->data, size2);
 654                 ctx->current_buffer = ab;
 655                 ctx->pointer = (void *) ab->data + rest;
 656
 657                 while (size > 0) {
 658                         void *next = handle_ar_packet(ctx, buffer);
 659                         pktsize = next - buffer;
 660                         if (pktsize >= size) {
 661                                 /*
 662                                  * We have handled all the data that was
 663                                  * originally in this page, so we can now
 664                                  * continue in the next page.
 665                                  */
 666                                 buffer = next;
 667                                 break;
 668                         }
 669                         /* move the next packet to the start of the buffer */
 670                         memmove(buffer, next, size + size2 - pktsize);
 671                         size -= pktsize;
 672                         /* fill up this page again */
 673                         size3 = min(rest - size2,
 674                                     (size_t)PAGE_SIZE - size - size2);
 675                         memcpy(buffer + size + size2,
 676                                (void *) ab->data + size2, size3);
 677                         size2 += size3;
 678                 }
 679
 680                 /* handle the packets that are fully in the next page */
 681                 buffer = (void *) ab->data + (buffer - (start + size));
 682                 end = (void *) ab->data + rest;
 683
 684                 while (buffer < end)
 685                         buffer = handle_ar_packet(ctx, buffer);
 686
 687                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
 688                                   start, start_bus);
 689                 ar_context_add_page(ctx);
 690         } else {
 691                 buffer = ctx->pointer;
 692                 ctx->pointer = end =
 693                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 694
 695                 while (buffer < end)
 696                         buffer = handle_ar_packet(ctx, buffer);
 697         }
 698 }
 699
 700 static int ar_context_init(struct ar_context *ctx,
 701                            struct fw_ohci *ohci, u32 regs)
 702 {
 703         struct ar_buffer ab;
 704
 705         ctx->regs        = regs;
 706         ctx->ohci        = ohci;
 707         ctx->last_buffer = &ab;
 708         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 709
 710         ar_context_add_page(ctx);
 711         ar_context_add_page(ctx);
 712         ctx->current_buffer = ab.next;
 713         ctx->pointer = ctx->current_buffer->data;
 714
 715         return 0;
 716 }
 717
 718 static void ar_context_run(struct ar_context *ctx)
 719 {
 720         struct ar_buffer *ab = ctx->current_buffer;
 721         dma_addr_t ab_bus;
 722         size_t offset;
 723
 724         offset = offsetof(struct ar_buffer, data);
 725         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 726
 727         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 728         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 729         flush_writes(ctx->ohci);
 730 }
 731
 732 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 733 {
 734         int b, key;
 735
 736         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 737         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 738
 739         /* figure out which descriptor the branch address goes in */
 740         if (z == 2 && (b == 3 || key == 2))
 741                 return d;
 742         else
 743                 return d + z - 1;
 744 }
 745
 746 static void context_tasklet(unsigned long data)
 747 {
 748         struct context *ctx = (struct context *) data;
 749         struct descriptor *d, *last;
 750         u32 address;
 751         int z;
 752         struct descriptor_buffer *desc;
 753
 754         desc = list_entry(ctx->buffer_list.next,
 755                         struct descriptor_buffer, list);
 756         last = ctx->last;
 757         while (last->branch_address != 0) {
 758                 struct descriptor_buffer *old_desc = desc;
 759                 address = le32_to_cpu(last->branch_address);
 760                 z = address & 0xf;
 761                 address &= ~0xf;
 762
 763                 /* If the branch address points to a buffer outside of the
 764                  * current buffer, advance to the next buffer. */
 765                 if (address < desc->buffer_bus ||
 766                                 address >= desc->buffer_bus + desc->used)
 767                         desc = list_entry(desc->list.next,
 768                                         struct descriptor_buffer, list);
 769                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 770                 last = find_branch_descriptor(d, z);
 771
 772                 if (!ctx->callback(ctx, d, last))
 773                         break;
 774
 775                 if (old_desc != desc) {
 776                         /* If we've advanced to the next buffer, move the
 777                          * previous buffer to the free list. */
 778                         unsigned long flags;
 779                         old_desc->used = 0;
 780                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 781                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 782                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 783                 }
 784                 ctx->last = last;
 785         }
 786 }
 787
 788 /*
 789  * Allocate a new buffer and add it to the list of free buffers for this
 790  * context.  Must be called with ohci->lock held.
 791  */
 792 static int context_add_buffer(struct context *ctx)
 793 {
 794         struct descriptor_buffer *desc;
 795         dma_addr_t uninitialized_var(bus_addr);
 796         int offset;
 797
 798         /*
 799          * 16MB of descriptors should be far more than enough for any DMA
 800          * program.  This will catch run-away userspace or DoS attacks.
 801          */
 802         if (ctx->total_allocation >= 16*1024*1024)
 803                 return -ENOMEM;
 804
 805         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 806                         &bus_addr, GFP_ATOMIC);
 807         if (!desc)
 808                 return -ENOMEM;
 809
 810         offset = (void *)&desc->buffer - (void *)desc;
 811         desc->buffer_size = PAGE_SIZE - offset;
 812         desc->buffer_bus = bus_addr + offset;
 813         desc->used = 0;
 814
 815         list_add_tail(&desc->list, &ctx->buffer_list);
 816         ctx->total_allocation += PAGE_SIZE;
 817
 818         return 0;
 819 }
 820
 821 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 822                         u32 regs, descriptor_callback_t callback)
 823 {
 824         ctx->ohci = ohci;
 825         ctx->regs = regs;
 826         ctx->total_allocation = 0;
 827
 828         INIT_LIST_HEAD(&ctx->buffer_list);
 829         if (context_add_buffer(ctx) < 0)
 830                 return -ENOMEM;
 831
 832         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 833                         struct descriptor_buffer, list);
 834
 835         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 836         ctx->callback = callback;
 837
 838         /*
 839          * We put a dummy descriptor in the buffer that has a NULL
 840          * branch address and looks like it's been sent.  That way we
 841          * have a descriptor to append DMA programs to.
 842          */
 843         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 844         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 845         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 846         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 847         ctx->last = ctx->buffer_tail->buffer;
 848         ctx->prev = ctx->buffer_tail->buffer;
 849
 850         return 0;
 851 }
 852
 853 static void context_release(struct context *ctx)
 854 {
 855         struct fw_card *card = &ctx->ohci->card;
 856         struct descriptor_buffer *desc, *tmp;
 857
 858         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 859                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 860                         desc->buffer_bus -
 861                         ((void *)&desc->buffer - (void *)desc));
 862 }
 863
 864 /* Must be called with ohci->lock held */
 865 static struct descriptor *context_get_descriptors(struct context *ctx,
 866                                                   int z, dma_addr_t *d_bus)
 867 {
 868         struct descriptor *d = NULL;
 869         struct descriptor_buffer *desc = ctx->buffer_tail;
 870
 871         if (z * sizeof(*d) > desc->buffer_size)
 872                 return NULL;
 873
 874         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 875                 /* No room for the descriptor in this buffer, so advance to the
 876                  * next one. */
 877
 878                 if (desc->list.next == &ctx->buffer_list) {
 879                         /* If there is no free buffer next in the list,
 880                          * allocate one. */
 881                         if (context_add_buffer(ctx) < 0)
 882                                 return NULL;
 883                 }
 884                 desc = list_entry(desc->list.next,
 885                                 struct descriptor_buffer, list);
 886                 ctx->buffer_tail = desc;
 887         }
 888
 889         d = desc->buffer + desc->used / sizeof(*d);
 890         memset(d, 0, z * sizeof(*d));
 891         *d_bus = desc->buffer_bus + desc->used;
 892
 893         return d;
 894 }
 895
 896 static void context_run(struct context *ctx, u32 extra)
 897 {
 898         struct fw_ohci *ohci = ctx->ohci;
 899
 900         reg_write(ohci, COMMAND_PTR(ctx->regs),
 901                   le32_to_cpu(ctx->last->branch_address));
 902         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 903         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 904         flush_writes(ohci);
 905 }
 906
 907 static void context_append(struct context *ctx,
 908                            struct descriptor *d, int z, int extra)
 909 {
 910         dma_addr_t d_bus;
 911         struct descriptor_buffer *desc = ctx->buffer_tail;
 912
 913         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 914
 915         desc->used += (z + extra) * sizeof(*d);
 916         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 917         ctx->prev = find_branch_descriptor(d, z);
 918
 919         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 920         flush_writes(ctx->ohci);
 921 }
 922
 923 static void context_stop(struct context *ctx)
 924 {
 925         u32 reg;
 926         int i;
 927
 928         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 929         flush_writes(ctx->ohci);
 930
 931         for (i = 0; i < 10; i++) {
 932                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 933                 if ((reg & CONTEXT_ACTIVE) == 0)
 934                         return;
 935
 936                 mdelay(1);
 937         }
 938         fw_error("Error: DMA context still active (0x%08x)\n", reg);
 939 }
 940
 941 struct driver_data {
 942         struct fw_packet *packet;
 943 };
 944
 945 /*
 946  * This function apppends a packet to the DMA queue for transmission.
 947  * Must always be called with the ochi->lock held to ensure proper
 948  * generation handling and locking around packet queue manipulation.
 949  */
 950 static int at_context_queue_packet(struct context *ctx,
 951                                    struct fw_packet *packet)
 952 {
 953         struct fw_ohci *ohci = ctx->ohci;
 954         dma_addr_t d_bus, uninitialized_var(payload_bus);
 955         struct driver_data *driver_data;
 956         struct descriptor *d, *last;
 957         __le32 *header;
 958         int z, tcode;
 959         u32 reg;
 960
 961         d = context_get_descriptors(ctx, 4, &d_bus);
 962         if (d == NULL) {
 963                 packet->ack = RCODE_SEND_ERROR;
 964                 return -1;
 965         }
 966
 967         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 968         d[0].res_count = cpu_to_le16(packet->timestamp);
 969
 970         /*
 971          * The DMA format for asyncronous link packets is different
 972          * from the IEEE1394 layout, so shift the fields around
 973          * accordingly.  If header_length is 8, it's a PHY packet, to
 974          * which we need to prepend an extra quadlet.
 975          */
 976
 977         header = (__le32 *) &d[1];
 978         switch (packet->header_length) {
 979         case 16:
 980         case 12:
 981                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 982                                         (packet->speed << 16));
 983                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 984                                         (packet->header[0] & 0xffff0000));
 985                 header[2] = cpu_to_le32(packet->header[2]);
 986
 987                 tcode = (packet->header[0] >> 4) & 0x0f;
 988                 if (TCODE_IS_BLOCK_PACKET(tcode))
 989                         header[3] = cpu_to_le32(packet->header[3]);
 990                 else
 991                         header[3] = (__force __le32) packet->header[3];
 992
 993                 d[0].req_count = cpu_to_le16(packet->header_length);
 994                 break;
 995
 996         case 8:
 997                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 998                                         (packet->speed << 16));
 999                 header[1] = cpu_to_le32(packet->header[0]);
1000                 header[2] = cpu_to_le32(packet->header[1]);
1001                 d[0].req_count = cpu_to_le16(12);
1002                 break;
1003
1004         case 4:
1005                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1006                                         (packet->speed << 16));
1007                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1008                 d[0].req_count = cpu_to_le16(8);
1009                 break;
1010
1011         default:
1012                 /* BUG(); */
1013                 packet->ack = RCODE_SEND_ERROR;
1014                 return -1;
1015         }
1016
1017         driver_data = (struct driver_data *) &d[3];
1018         driver_data->packet = packet;
1019         packet->driver_data = driver_data;
1020
1021         if (packet->payload_length > 0) {
1022                 payload_bus =
1023                         dma_map_single(ohci->card.device, packet->payload,
1024                                        packet->payload_length, DMA_TO_DEVICE);
1025                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1026                         packet->ack = RCODE_SEND_ERROR;
1027                         return -1;
1028                 }
1029                 packet->payload_bus = payload_bus;
1030
1031                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1032                 d[2].data_address = cpu_to_le32(payload_bus);
1033                 last = &d[2];
1034                 z = 3;
1035         } else {
1036                 last = &d[0];
1037                 z = 2;
1038         }
1039
1040         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1041                                      DESCRIPTOR_IRQ_ALWAYS |
1042                                      DESCRIPTOR_BRANCH_ALWAYS);
1043
1044         /*
1045          * If the controller and packet generations don't match, we need to
1046          * bail out and try again.  If IntEvent.busReset is set, the AT context
1047          * is halted, so appending to the context and trying to run it is
1048          * futile.  Most controllers do the right thing and just flush the AT
1049          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1050          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1051          * up stalling out.  So we just bail out in software and try again
1052          * later, and everyone is happy.
1053          * FIXME: Document how the locking works.
1054          */
1055         if (ohci->generation != packet->generation ||
1056             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1057                 if (packet->payload_length > 0)
1058                         dma_unmap_single(ohci->card.device, payload_bus,
1059                                          packet->payload_length, DMA_TO_DEVICE);
1060                 packet->ack = RCODE_GENERATION;
1061                 return -1;
1062         }
1063
1064         context_append(ctx, d, z, 4 - z);
1065
1066         /* If the context isn't already running, start it up. */
1067         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1068         if ((reg & CONTEXT_RUN) == 0)
1069                 context_run(ctx, 0);
1070
1071         return 0;
1072 }
1073
1074 static int handle_at_packet(struct context *context,
1075                             struct descriptor *d,
1076                             struct descriptor *last)
1077 {
1078         struct driver_data *driver_data;
1079         struct fw_packet *packet;
1080         struct fw_ohci *ohci = context->ohci;
1081         int evt;
1082
1083         if (last->transfer_status == 0)
1084                 /* This descriptor isn't done yet, stop iteration. */
1085                 return 0;
1086
1087         driver_data = (struct driver_data *) &d[3];
1088         packet = driver_data->packet;
1089         if (packet == NULL)
1090                 /* This packet was cancelled, just continue. */
1091                 return 1;
1092
1093         if (packet->payload_bus)
1094                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1095                                  packet->payload_length, DMA_TO_DEVICE);
1096
1097         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1098         packet->timestamp = le16_to_cpu(last->res_count);
1099
1100         log_ar_at_event('T', packet->speed, packet->header, evt);
1101
1102         switch (evt) {
1103         case OHCI1394_evt_timeout:
1104                 /* Async response transmit timed out. */
1105                 packet->ack = RCODE_CANCELLED;
1106                 break;
1107
1108         case OHCI1394_evt_flushed:
1109                 /*
1110                  * The packet was flushed should give same error as
1111                  * when we try to use a stale generation count.
1112                  */
1113                 packet->ack = RCODE_GENERATION;
1114                 break;
1115
1116         case OHCI1394_evt_missing_ack:
1117                 /*
1118                  * Using a valid (current) generation count, but the
1119                  * node is not on the bus or not sending acks.
1120                  */
1121                 packet->ack = RCODE_NO_ACK;
1122                 break;
1123
1124         case ACK_COMPLETE + 0x10:
1125         case ACK_PENDING + 0x10:
1126         case ACK_BUSY_X + 0x10:
1127         case ACK_BUSY_A + 0x10:
1128         case ACK_BUSY_B + 0x10:
1129         case ACK_DATA_ERROR + 0x10:
1130         case ACK_TYPE_ERROR + 0x10:
1131                 packet->ack = evt - 0x10;
1132                 break;
1133
1134         default:
1135                 packet->ack = RCODE_SEND_ERROR;
1136                 break;
1137         }
1138
1139         packet->callback(packet, &ohci->card, packet->ack);
1140
1141         return 1;
1142 }
1143
1144 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1145 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1146 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1147 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1148 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1149
1150 static void handle_local_rom(struct fw_ohci *ohci,
1151                              struct fw_packet *packet, u32 csr)
1152 {
1153         struct fw_packet response;
1154         int tcode, length, i;
1155
1156         tcode = HEADER_GET_TCODE(packet->header[0]);
1157         if (TCODE_IS_BLOCK_PACKET(tcode))
1158                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1159         else
1160                 length = 4;
1161
1162         i = csr - CSR_CONFIG_ROM;
1163         if (i + length > CONFIG_ROM_SIZE) {
1164                 fw_fill_response(&response, packet->header,
1165                                  RCODE_ADDRESS_ERROR, NULL, 0);
1166         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1167                 fw_fill_response(&response, packet->header,
1168                                  RCODE_TYPE_ERROR, NULL, 0);
1169         } else {
1170                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1171                                  (void *) ohci->config_rom + i, length);
1172         }
1173
1174         fw_core_handle_response(&ohci->card, &response);
1175 }
1176
1177 static void handle_local_lock(struct fw_ohci *ohci,
1178                               struct fw_packet *packet, u32 csr)
1179 {
1180         struct fw_packet response;
1181         int tcode, length, ext_tcode, sel;
1182         __be32 *payload, lock_old;
1183         u32 lock_arg, lock_data;
1184
1185         tcode = HEADER_GET_TCODE(packet->header[0]);
1186         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1187         payload = packet->payload;
1188         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1189
1190         if (tcode == TCODE_LOCK_REQUEST &&
1191             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1192                 lock_arg = be32_to_cpu(payload[0]);
1193                 lock_data = be32_to_cpu(payload[1]);
1194         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1195                 lock_arg = 0;
1196                 lock_data = 0;
1197         } else {
1198                 fw_fill_response(&response, packet->header,
1199                                  RCODE_TYPE_ERROR, NULL, 0);
1200                 goto out;
1201         }
1202
1203         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1204         reg_write(ohci, OHCI1394_CSRData, lock_data);
1205         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1206         reg_write(ohci, OHCI1394_CSRControl, sel);
1207
1208         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1209                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1210         else
1211                 fw_notify("swap not done yet\n");
1212
1213         fw_fill_response(&response, packet->header,
1214                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1215  out:
1216         fw_core_handle_response(&ohci->card, &response);
1217 }
1218
1219 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1220 {
1221         u64 offset;
1222         u32 csr;
1223
1224         if (ctx == &ctx->ohci->at_request_ctx) {
1225                 packet->ack = ACK_PENDING;
1226                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1227         }
1228
1229         offset =
1230                 ((unsigned long long)
1231                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1232                 packet->header[2];
1233         csr = offset - CSR_REGISTER_BASE;
1234
1235         /* Handle config rom reads. */
1236         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1237                 handle_local_rom(ctx->ohci, packet, csr);
1238         else switch (csr) {
1239         case CSR_BUS_MANAGER_ID:
1240         case CSR_BANDWIDTH_AVAILABLE:
1241         case CSR_CHANNELS_AVAILABLE_HI:
1242         case CSR_CHANNELS_AVAILABLE_LO:
1243                 handle_local_lock(ctx->ohci, packet, csr);
1244                 break;
1245         default:
1246                 if (ctx == &ctx->ohci->at_request_ctx)
1247                         fw_core_handle_request(&ctx->ohci->card, packet);
1248                 else
1249                         fw_core_handle_response(&ctx->ohci->card, packet);
1250                 break;
1251         }
1252
1253         if (ctx == &ctx->ohci->at_response_ctx) {
1254                 packet->ack = ACK_COMPLETE;
1255                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1256         }
1257 }
1258
1259 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1260 {
1261         unsigned long flags;
1262         int ret;
1263
1264         spin_lock_irqsave(&ctx->ohci->lock, flags);
1265
1266         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1267             ctx->ohci->generation == packet->generation) {
1268                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1269                 handle_local_request(ctx, packet);
1270                 return;
1271         }
1272
1273         ret = at_context_queue_packet(ctx, packet);
1274         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1275
1276         if (ret < 0)
1277                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1278
1279 }
1280
1281 static void bus_reset_tasklet(unsigned long data)
1282 {
1283         struct fw_ohci *ohci = (struct fw_ohci *)data;
1284         int self_id_count, i, j, reg;
1285         int generation, new_generation;
1286         unsigned long flags;
1287         void *free_rom = NULL;
1288         dma_addr_t free_rom_bus = 0;
1289
1290         reg = reg_read(ohci, OHCI1394_NodeID);
1291         if (!(reg & OHCI1394_NodeID_idValid)) {
1292                 fw_notify("node ID not valid, new bus reset in progress\n");
1293                 return;
1294         }
1295         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1296                 fw_notify("malconfigured bus\n");
1297                 return;
1298         }
1299         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1300                                OHCI1394_NodeID_nodeNumber);
1301
1302         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1303         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1304                 fw_notify("inconsistent self IDs\n");
1305                 return;
1306         }
1307         /*
1308          * The count in the SelfIDCount register is the number of
1309          * bytes in the self ID receive buffer.  Since we also receive
1310          * the inverted quadlets and a header quadlet, we shift one
1311          * bit extra to get the actual number of self IDs.
1312          */
1313         self_id_count = (reg >> 3) & 0xff;
1314         if (self_id_count == 0 || self_id_count > 252) {
1315                 fw_notify("inconsistent self IDs\n");
1316                 return;
1317         }
1318         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1319         rmb();
1320
1321         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1322                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1323                         fw_notify("inconsistent self IDs\n");
1324                         return;
1325                 }
1326                 ohci->self_id_buffer[j] =
1327                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1328         }
1329         rmb();
1330
1331         /*
1332          * Check the consistency of the self IDs we just read.  The
1333          * problem we face is that a new bus reset can start while we
1334          * read out the self IDs from the DMA buffer. If this happens,
1335          * the DMA buffer will be overwritten with new self IDs and we
1336          * will read out inconsistent data.  The OHCI specification
1337          * (section 11.2) recommends a technique similar to
1338          * linux/seqlock.h, where we remember the generation of the
1339          * self IDs in the buffer before reading them out and compare
1340          * it to the current generation after reading them out.  If
1341          * the two generations match we know we have a consistent set
1342          * of self IDs.
1343          */
1344
1345         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1346         if (new_generation != generation) {
1347                 fw_notify("recursive bus reset detected, "
1348                           "discarding self ids\n");
1349                 return;
1350         }
1351
1352         /* FIXME: Document how the locking works. */
1353         spin_lock_irqsave(&ohci->lock, flags);
1354
1355         ohci->generation = generation;
1356         context_stop(&ohci->at_request_ctx);
1357         context_stop(&ohci->at_response_ctx);
1358         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1359
1360         if (ohci->bus_reset_packet_quirk)
1361                 ohci->request_generation = generation;
1362
1363         /*
1364          * This next bit is unrelated to the AT context stuff but we
1365          * have to do it under the spinlock also.  If a new config rom
1366          * was set up before this reset, the old one is now no longer
1367          * in use and we can free it. Update the config rom pointers
1368          * to point to the current config rom and clear the
1369          * next_config_rom pointer so a new udpate can take place.
1370          */
1371
1372         if (ohci->next_config_rom != NULL) {
1373                 if (ohci->next_config_rom != ohci->config_rom) {
1374                         free_rom      = ohci->config_rom;
1375                         free_rom_bus  = ohci->config_rom_bus;
1376                 }
1377                 ohci->config_rom      = ohci->next_config_rom;
1378                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1379                 ohci->next_config_rom = NULL;
1380
1381                 /*
1382                  * Restore config_rom image and manually update
1383                  * config_rom registers.  Writing the header quadlet
1384                  * will indicate that the config rom is ready, so we
1385                  * do that last.
1386                  */
1387                 reg_write(ohci, OHCI1394_BusOptions,
1388                           be32_to_cpu(ohci->config_rom[2]));
1389                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1390                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1391         }
1392
1393 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1394         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1395         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1396 #endif
1397
1398         spin_unlock_irqrestore(&ohci->lock, flags);
1399
1400         if (free_rom)
1401                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1402                                   free_rom, free_rom_bus);
1403
1404         log_selfids(ohci->node_id, generation,
1405                     self_id_count, ohci->self_id_buffer);
1406
1407         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1408                                  self_id_count, ohci->self_id_buffer);
1409 }
1410
1411 static irqreturn_t irq_handler(int irq, void *data)
1412 {
1413         struct fw_ohci *ohci = data;
1414         u32 event, iso_event, cycle_time;
1415         int i;
1416
1417         event = reg_read(ohci, OHCI1394_IntEventClear);
1418
1419         if (!event || !~event)
1420                 return IRQ_NONE;
1421
1422         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1423         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1424         log_irqs(event);
1425
1426         if (event & OHCI1394_selfIDComplete)
1427                 tasklet_schedule(&ohci->bus_reset_tasklet);
1428
1429         if (event & OHCI1394_RQPkt)
1430                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1431
1432         if (event & OHCI1394_RSPkt)
1433                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1434
1435         if (event & OHCI1394_reqTxComplete)
1436                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1437
1438         if (event & OHCI1394_respTxComplete)
1439                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1440
1441         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1442         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1443
1444         while (iso_event) {
1445                 i = ffs(iso_event) - 1;
1446                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1447                 iso_event &= ~(1 << i);
1448         }
1449
1450         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1451         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1452
1453         while (iso_event) {
1454                 i = ffs(iso_event) - 1;
1455                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1456                 iso_event &= ~(1 << i);
1457         }
1458
1459         if (unlikely(event & OHCI1394_regAccessFail))
1460                 fw_error("Register access failure - "
1461                          "please notify linux1394-devel@lists.sf.net\n");
1462
1463         if (unlikely(event & OHCI1394_postedWriteErr))
1464                 fw_error("PCI posted write error\n");
1465
1466         if (unlikely(event & OHCI1394_cycleTooLong)) {
1467                 if (printk_ratelimit())
1468                         fw_notify("isochronous cycle too long\n");
1469                 reg_write(ohci, OHCI1394_LinkControlSet,
1470                           OHCI1394_LinkControl_cycleMaster);
1471         }
1472
1473         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1474                 /*
1475                  * We need to clear this event bit in order to make
1476                  * cycleMatch isochronous I/O work.  In theory we should
1477                  * stop active cycleMatch iso contexts now and restart
1478                  * them at least two cycles later.  (FIXME?)
1479                  */
1480                 if (printk_ratelimit())
1481                         fw_notify("isochronous cycle inconsistent\n");
1482         }
1483
1484         if (event & OHCI1394_cycle64Seconds) {
1485                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1486                 if ((cycle_time & 0x80000000) == 0)
1487                         atomic_inc(&ohci->bus_seconds);
1488         }
1489
1490         return IRQ_HANDLED;
1491 }
1492
1493 static int software_reset(struct fw_ohci *ohci)
1494 {
1495         int i;
1496
1497         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1498
1499         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1500                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1501                      OHCI1394_HCControl_softReset) == 0)
1502                         return 0;
1503                 msleep(1);
1504         }
1505
1506         return -EBUSY;
1507 }
1508
1509 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1510 {
1511         struct fw_ohci *ohci = fw_ohci(card);
1512         struct pci_dev *dev = to_pci_dev(card->device);
1513         u32 lps;
1514         int i;
1515
1516         if (software_reset(ohci)) {
1517                 fw_error("Failed to reset ohci card.\n");
1518                 return -EBUSY;
1519         }
1520
1521         /*
1522          * Now enable LPS, which we need in order to start accessing
1523          * most of the registers.  In fact, on some cards (ALI M5251),
1524          * accessing registers in the SClk domain without LPS enabled
1525          * will lock up the machine.  Wait 50msec to make sure we have
1526          * full link enabled.  However, with some cards (well, at least
1527          * a JMicron PCIe card), we have to try again sometimes.
1528          */
1529         reg_write(ohci, OHCI1394_HCControlSet,
1530                   OHCI1394_HCControl_LPS |
1531                   OHCI1394_HCControl_postedWriteEnable);
1532         flush_writes(ohci);
1533
1534         for (lps = 0, i = 0; !lps && i < 3; i++) {
1535                 msleep(50);
1536                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1537                       OHCI1394_HCControl_LPS;
1538         }
1539
1540         if (!lps) {
1541                 fw_error("Failed to set Link Power Status\n");
1542                 return -EIO;
1543         }
1544
1545         reg_write(ohci, OHCI1394_HCControlClear,
1546                   OHCI1394_HCControl_noByteSwapData);
1547
1548         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1549         reg_write(ohci, OHCI1394_LinkControlClear,
1550                   OHCI1394_LinkControl_rcvPhyPkt);
1551         reg_write(ohci, OHCI1394_LinkControlSet,
1552                   OHCI1394_LinkControl_rcvSelfID |
1553                   OHCI1394_LinkControl_cycleTimerEnable |
1554                   OHCI1394_LinkControl_cycleMaster);
1555
1556         reg_write(ohci, OHCI1394_ATRetries,
1557                   OHCI1394_MAX_AT_REQ_RETRIES |
1558                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1559                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1560
1561         ar_context_run(&ohci->ar_request_ctx);
1562         ar_context_run(&ohci->ar_response_ctx);
1563
1564         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1565         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1566         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1567         reg_write(ohci, OHCI1394_IntMaskSet,
1568                   OHCI1394_selfIDComplete |
1569                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1570                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1571                   OHCI1394_isochRx | OHCI1394_isochTx |
1572                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1573                   OHCI1394_cycleInconsistent |
1574                   OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1575                   OHCI1394_masterIntEnable);
1576         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1577                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1578
1579         /* Activate link_on bit and contender bit in our self ID packets.*/
1580         if (ohci_update_phy_reg(card, 4, 0,
1581                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1582                 return -EIO;
1583
1584         /*
1585          * When the link is not yet enabled, the atomic config rom
1586          * update mechanism described below in ohci_set_config_rom()
1587          * is not active.  We have to update ConfigRomHeader and
1588          * BusOptions manually, and the write to ConfigROMmap takes
1589          * effect immediately.  We tie this to the enabling of the
1590          * link, so we have a valid config rom before enabling - the
1591          * OHCI requires that ConfigROMhdr and BusOptions have valid
1592          * values before enabling.
1593          *
1594          * However, when the ConfigROMmap is written, some controllers
1595          * always read back quadlets 0 and 2 from the config rom to
1596          * the ConfigRomHeader and BusOptions registers on bus reset.
1597          * They shouldn't do that in this initial case where the link
1598          * isn't enabled.  This means we have to use the same
1599          * workaround here, setting the bus header to 0 and then write
1600          * the right values in the bus reset tasklet.
1601          */
1602
1603         if (config_rom) {
1604                 ohci->next_config_rom =
1605                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1606                                            &ohci->next_config_rom_bus,
1607                                            GFP_KERNEL);
1608                 if (ohci->next_config_rom == NULL)
1609                         return -ENOMEM;
1610
1611                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1612                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1613         } else {
1614                 /*
1615                  * In the suspend case, config_rom is NULL, which
1616                  * means that we just reuse the old config rom.
1617                  */
1618                 ohci->next_config_rom = ohci->config_rom;
1619                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1620         }
1621
1622         ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1623         ohci->next_config_rom[0] = 0;
1624         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1625         reg_write(ohci, OHCI1394_BusOptions,
1626                   be32_to_cpu(ohci->next_config_rom[2]));
1627         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1628
1629         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1630
1631         if (request_irq(dev->irq, irq_handler,
1632                         IRQF_SHARED, ohci_driver_name, ohci)) {
1633                 fw_error("Failed to allocate shared interrupt %d.\n",
1634                          dev->irq);
1635                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1636                                   ohci->config_rom, ohci->config_rom_bus);
1637                 return -EIO;
1638         }
1639
1640         reg_write(ohci, OHCI1394_HCControlSet,
1641                   OHCI1394_HCControl_linkEnable |
1642                   OHCI1394_HCControl_BIBimageValid);
1643         flush_writes(ohci);
1644
1645         /*
1646          * We are ready to go, initiate bus reset to finish the
1647          * initialization.
1648          */
1649
1650         fw_core_initiate_bus_reset(&ohci->card, 1);
1651
1652         return 0;
1653 }
1654
1655 static int ohci_set_config_rom(struct fw_card *card,
1656                                u32 *config_rom, size_t length)
1657 {
1658         struct fw_ohci *ohci;
1659         unsigned long flags;
1660         int ret = -EBUSY;
1661         __be32 *next_config_rom;
1662         dma_addr_t uninitialized_var(next_config_rom_bus);
1663
1664         ohci = fw_ohci(card);
1665
1666         /*
1667          * When the OHCI controller is enabled, the config rom update
1668          * mechanism is a bit tricky, but easy enough to use.  See
1669          * section 5.5.6 in the OHCI specification.
1670          *
1671          * The OHCI controller caches the new config rom address in a
1672          * shadow register (ConfigROMmapNext) and needs a bus reset
1673          * for the changes to take place.  When the bus reset is
1674          * detected, the controller loads the new values for the
1675          * ConfigRomHeader and BusOptions registers from the specified
1676          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1677          * shadow register. All automatically and atomically.
1678          *
1679          * Now, there's a twist to this story.  The automatic load of
1680          * ConfigRomHeader and BusOptions doesn't honor the
1681          * noByteSwapData bit, so with a be32 config rom, the
1682          * controller will load be32 values in to these registers
1683          * during the atomic update, even on litte endian
1684          * architectures.  The workaround we use is to put a 0 in the
1685          * header quadlet; 0 is endian agnostic and means that the
1686          * config rom isn't ready yet.  In the bus reset tasklet we
1687          * then set up the real values for the two registers.
1688          *
1689          * We use ohci->lock to avoid racing with the code that sets
1690          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1691          */
1692
1693         next_config_rom =
1694                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1695                                    &next_config_rom_bus, GFP_KERNEL);
1696         if (next_config_rom == NULL)
1697                 return -ENOMEM;
1698
1699         spin_lock_irqsave(&ohci->lock, flags);
1700
1701         if (ohci->next_config_rom == NULL) {
1702                 ohci->next_config_rom = next_config_rom;
1703                 ohci->next_config_rom_bus = next_config_rom_bus;
1704
1705                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1706                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1707                                   length * 4);
1708
1709                 ohci->next_header = config_rom[0];
1710                 ohci->next_config_rom[0] = 0;
1711
1712                 reg_write(ohci, OHCI1394_ConfigROMmap,
1713                           ohci->next_config_rom_bus);
1714                 ret = 0;
1715         }
1716
1717         spin_unlock_irqrestore(&ohci->lock, flags);
1718
1719         /*
1720          * Now initiate a bus reset to have the changes take
1721          * effect. We clean up the old config rom memory and DMA
1722          * mappings in the bus reset tasklet, since the OHCI
1723          * controller could need to access it before the bus reset
1724          * takes effect.
1725          */
1726         if (ret == 0)
1727                 fw_core_initiate_bus_reset(&ohci->card, 1);
1728         else
1729                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1730                                   next_config_rom, next_config_rom_bus);
1731
1732         return ret;
1733 }
1734
1735 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1736 {
1737         struct fw_ohci *ohci = fw_ohci(card);
1738
1739         at_context_transmit(&ohci->at_request_ctx, packet);
1740 }
1741
1742 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1743 {
1744         struct fw_ohci *ohci = fw_ohci(card);
1745
1746         at_context_transmit(&ohci->at_response_ctx, packet);
1747 }
1748
1749 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1750 {
1751         struct fw_ohci *ohci = fw_ohci(card);
1752         struct context *ctx = &ohci->at_request_ctx;
1753         struct driver_data *driver_data = packet->driver_data;
1754         int ret = -ENOENT;
1755
1756         tasklet_disable(&ctx->tasklet);
1757
1758         if (packet->ack != 0)
1759                 goto out;
1760
1761         if (packet->payload_bus)
1762                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1763                                  packet->payload_length, DMA_TO_DEVICE);
1764
1765         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1766         driver_data->packet = NULL;
1767         packet->ack = RCODE_CANCELLED;
1768         packet->callback(packet, &ohci->card, packet->ack);
1769         ret = 0;
1770  out:
1771         tasklet_enable(&ctx->tasklet);
1772
1773         return ret;
1774 }
1775
1776 static int ohci_enable_phys_dma(struct fw_card *card,
1777                                 int node_id, int generation)
1778 {
1779 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1780         return 0;
1781 #else
1782         struct fw_ohci *ohci = fw_ohci(card);
1783         unsigned long flags;
1784         int n, ret = 0;
1785
1786         /*
1787          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1788          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1789          */
1790
1791         spin_lock_irqsave(&ohci->lock, flags);
1792
1793         if (ohci->generation != generation) {
1794                 ret = -ESTALE;
1795                 goto out;
1796         }
1797
1798         /*
1799          * Note, if the node ID contains a non-local bus ID, physical DMA is
1800          * enabled for _all_ nodes on remote buses.
1801          */
1802
1803         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1804         if (n < 32)
1805                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1806         else
1807                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1808
1809         flush_writes(ohci);
1810  out:
1811         spin_unlock_irqrestore(&ohci->lock, flags);
1812
1813         return ret;
1814 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1815 }
1816
1817 static u64 ohci_get_bus_time(struct fw_card *card)
1818 {
1819         struct fw_ohci *ohci = fw_ohci(card);
1820         u32 cycle_time;
1821         u64 bus_time;
1822
1823         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1824         bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1825
1826         return bus_time;
1827 }
1828
1829 static void copy_iso_headers(struct iso_context *ctx, void *p)
1830 {
1831         int i = ctx->header_length;
1832
1833         if (i + ctx->base.header_size > PAGE_SIZE)
1834                 return;
1835
1836         /*
1837          * The iso header is byteswapped to little endian by
1838          * the controller, but the remaining header quadlets
1839          * are big endian.  We want to present all the headers
1840          * as big endian, so we have to swap the first quadlet.
1841          */
1842         if (ctx->base.header_size > 0)
1843                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1844         if (ctx->base.header_size > 4)
1845                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1846         if (ctx->base.header_size > 8)
1847                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1848         ctx->header_length += ctx->base.header_size;
1849 }
1850
1851 static int handle_ir_dualbuffer_packet(struct context *context,
1852                                        struct descriptor *d,
1853                                        struct descriptor *last)
1854 {
1855         struct iso_context *ctx =
1856                 container_of(context, struct iso_context, context);
1857         struct db_descriptor *db = (struct db_descriptor *) d;
1858         __le32 *ir_header;
1859         size_t header_length;
1860         void *p, *end;
1861
1862         if (db->first_res_count != 0 && db->second_res_count != 0) {
1863                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1864                         /* This descriptor isn't done yet, stop iteration. */
1865                         return 0;
1866                 }
1867                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1868         }
1869
1870         header_length = le16_to_cpu(db->first_req_count) -
1871                 le16_to_cpu(db->first_res_count);
1872
1873         p = db + 1;
1874         end = p + header_length;
1875         while (p < end) {
1876                 copy_iso_headers(ctx, p);
1877                 ctx->excess_bytes +=
1878                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1879                 p += max(ctx->base.header_size, (size_t)8);
1880         }
1881
1882         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1883                 le16_to_cpu(db->second_res_count);
1884
1885         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1886                 ir_header = (__le32 *) (db + 1);
1887                 ctx->base.callback(&ctx->base,
1888                                    le32_to_cpu(ir_header[0]) & 0xffff,
1889                                    ctx->header_length, ctx->header,
1890                                    ctx->base.callback_data);
1891                 ctx->header_length = 0;
1892         }
1893
1894         return 1;
1895 }
1896
1897 static int handle_ir_packet_per_buffer(struct context *context,
1898                                        struct descriptor *d,
1899                                        struct descriptor *last)
1900 {
1901         struct iso_context *ctx =
1902                 container_of(context, struct iso_context, context);
1903         struct descriptor *pd;
1904         __le32 *ir_header;
1905         void *p;
1906
1907         for (pd = d; pd <= last; pd++) {
1908                 if (pd->transfer_status)
1909                         break;
1910         }
1911         if (pd > last)
1912                 /* Descriptor(s) not done yet, stop iteration */
1913                 return 0;
1914
1915         p = last + 1;
1916         copy_iso_headers(ctx, p);
1917
1918         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1919                 ir_header = (__le32 *) p;
1920                 ctx->base.callback(&ctx->base,
1921                                    le32_to_cpu(ir_header[0]) & 0xffff,
1922                                    ctx->header_length, ctx->header,
1923                                    ctx->base.callback_data);
1924                 ctx->header_length = 0;
1925         }
1926
1927         return 1;
1928 }
1929
1930 static int handle_it_packet(struct context *context,
1931                             struct descriptor *d,
1932                             struct descriptor *last)
1933 {
1934         struct iso_context *ctx =
1935                 container_of(context, struct iso_context, context);
1936         int i;
1937         struct descriptor *pd;
1938
1939         for (pd = d; pd <= last; pd++)
1940                 if (pd->transfer_status)
1941                         break;
1942         if (pd > last)
1943                 /* Descriptor(s) not done yet, stop iteration */
1944                 return 0;
1945
1946         i = ctx->header_length;
1947         if (i + 4 < PAGE_SIZE) {
1948                 /* Present this value as big-endian to match the receive code */
1949                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1950                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1951                                 le16_to_cpu(pd->res_count));
1952                 ctx->header_length += 4;
1953         }
1954         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1955                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1956                                    ctx->header_length, ctx->header,
1957                                    ctx->base.callback_data);
1958                 ctx->header_length = 0;
1959         }
1960         return 1;
1961 }
1962
1963 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1964                                 int type, int channel, size_t header_size)
1965 {
1966         struct fw_ohci *ohci = fw_ohci(card);
1967         struct iso_context *ctx, *list;
1968         descriptor_callback_t callback;
1969         u64 *channels, dont_care = ~0ULL;
1970         u32 *mask, regs;
1971         unsigned long flags;
1972         int index, ret = -ENOMEM;
1973
1974         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1975                 channels = &dont_care;
1976                 mask = &ohci->it_context_mask;
1977                 list = ohci->it_context_list;
1978                 callback = handle_it_packet;
1979         } else {
1980                 channels = &ohci->ir_context_channels;
1981                 mask = &ohci->ir_context_mask;
1982                 list = ohci->ir_context_list;
1983                 if (ohci->use_dualbuffer)
1984                         callback = handle_ir_dualbuffer_packet;
1985                 else
1986                         callback = handle_ir_packet_per_buffer;
1987         }
1988
1989         spin_lock_irqsave(&ohci->lock, flags);
1990         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1991         if (index >= 0) {
1992                 *channels &= ~(1ULL << channel);
1993                 *mask &= ~(1 << index);
1994         }
1995         spin_unlock_irqrestore(&ohci->lock, flags);
1996
1997         if (index < 0)
1998                 return ERR_PTR(-EBUSY);
1999
2000         if (type == FW_ISO_CONTEXT_TRANSMIT)
2001                 regs = OHCI1394_IsoXmitContextBase(index);
2002         else
2003                 regs = OHCI1394_IsoRcvContextBase(index);
2004
2005         ctx = &list[index];
2006         memset(ctx, 0, sizeof(*ctx));
2007         ctx->header_length = 0;
2008         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2009         if (ctx->header == NULL)
2010                 goto out;
2011
2012         ret = context_init(&ctx->context, ohci, regs, callback);
2013         if (ret < 0)
2014                 goto out_with_header;
2015
2016         return &ctx->base;
2017
2018  out_with_header:
2019         free_page((unsigned long)ctx->header);
2020  out:
2021         spin_lock_irqsave(&ohci->lock, flags);
2022         *mask |= 1 << index;
2023         spin_unlock_irqrestore(&ohci->lock, flags);
2024
2025         return ERR_PTR(ret);
2026 }
2027
2028 static int ohci_start_iso(struct fw_iso_context *base,
2029                           s32 cycle, u32 sync, u32 tags)
2030 {
2031         struct iso_context *ctx = container_of(base, struct iso_context, base);
2032         struct fw_ohci *ohci = ctx->context.ohci;
2033         u32 control, match;
2034         int index;
2035
2036         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2037                 index = ctx - ohci->it_context_list;
2038                 match = 0;
2039                 if (cycle >= 0)
2040                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2041                                 (cycle & 0x7fff) << 16;
2042
2043                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2044                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2045                 context_run(&ctx->context, match);
2046         } else {
2047                 index = ctx - ohci->ir_context_list;
2048                 control = IR_CONTEXT_ISOCH_HEADER;
2049                 if (ohci->use_dualbuffer)
2050                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2051                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2052                 if (cycle >= 0) {
2053                         match |= (cycle & 0x07fff) << 12;
2054                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2055                 }
2056
2057                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2058                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2059                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2060                 context_run(&ctx->context, control);
2061         }
2062
2063         return 0;
2064 }
2065
2066 static int ohci_stop_iso(struct fw_iso_context *base)
2067 {
2068         struct fw_ohci *ohci = fw_ohci(base->card);
2069         struct iso_context *ctx = container_of(base, struct iso_context, base);
2070         int index;
2071
2072         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2073                 index = ctx - ohci->it_context_list;
2074                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2075         } else {
2076                 index = ctx - ohci->ir_context_list;
2077                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2078         }
2079         flush_writes(ohci);
2080         context_stop(&ctx->context);
2081
2082         return 0;
2083 }
2084
2085 static void ohci_free_iso_context(struct fw_iso_context *base)
2086 {
2087         struct fw_ohci *ohci = fw_ohci(base->card);
2088         struct iso_context *ctx = container_of(base, struct iso_context, base);
2089         unsigned long flags;
2090         int index;
2091
2092         ohci_stop_iso(base);
2093         context_release(&ctx->context);
2094         free_page((unsigned long)ctx->header);
2095
2096         spin_lock_irqsave(&ohci->lock, flags);
2097
2098         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2099                 index = ctx - ohci->it_context_list;
2100                 ohci->it_context_mask |= 1 << index;
2101         } else {
2102                 index = ctx - ohci->ir_context_list;
2103                 ohci->ir_context_mask |= 1 << index;
2104                 ohci->ir_context_channels |= 1ULL << base->channel;
2105         }
2106
2107         spin_unlock_irqrestore(&ohci->lock, flags);
2108 }
2109
2110 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2111                                    struct fw_iso_packet *packet,
2112                                    struct fw_iso_buffer *buffer,
2113                                    unsigned long payload)
2114 {
2115         struct iso_context *ctx = container_of(base, struct iso_context, base);
2116         struct descriptor *d, *last, *pd;
2117         struct fw_iso_packet *p;
2118         __le32 *header;
2119         dma_addr_t d_bus, page_bus;
2120         u32 z, header_z, payload_z, irq;
2121         u32 payload_index, payload_end_index, next_page_index;
2122         int page, end_page, i, length, offset;
2123
2124         /*
2125          * FIXME: Cycle lost behavior should be configurable: lose
2126          * packet, retransmit or terminate..
2127          */
2128
2129         p = packet;
2130         payload_index = payload;
2131
2132         if (p->skip)
2133                 z = 1;
2134         else
2135                 z = 2;
2136         if (p->header_length > 0)
2137                 z++;
2138
2139         /* Determine the first page the payload isn't contained in. */
2140         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2141         if (p->payload_length > 0)
2142                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2143         else
2144                 payload_z = 0;
2145
2146         z += payload_z;
2147
2148         /* Get header size in number of descriptors. */
2149         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2150
2151         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2152         if (d == NULL)
2153                 return -ENOMEM;
2154
2155         if (!p->skip) {
2156                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2157                 d[0].req_count = cpu_to_le16(8);
2158
2159                 header = (__le32 *) &d[1];
2160                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2161                                         IT_HEADER_TAG(p->tag) |
2162                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2163                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2164                                         IT_HEADER_SPEED(ctx->base.speed));
2165                 header[1] =
2166                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2167                                                           p->payload_length));
2168         }
2169
2170         if (p->header_length > 0) {
2171                 d[2].req_count    = cpu_to_le16(p->header_length);
2172                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2173                 memcpy(&d[z], p->header, p->header_length);
2174         }
2175
2176         pd = d + z - payload_z;
2177         payload_end_index = payload_index + p->payload_length;
2178         for (i = 0; i < payload_z; i++) {
2179                 page               = payload_index >> PAGE_SHIFT;
2180                 offset             = payload_index & ~PAGE_MASK;
2181                 next_page_index    = (page + 1) << PAGE_SHIFT;
2182                 length             =
2183                         min(next_page_index, payload_end_index) - payload_index;
2184                 pd[i].req_count    = cpu_to_le16(length);
2185
2186                 page_bus = page_private(buffer->pages[page]);
2187                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2188
2189                 payload_index += length;
2190         }
2191
2192         if (p->interrupt)
2193                 irq = DESCRIPTOR_IRQ_ALWAYS;
2194         else
2195                 irq = DESCRIPTOR_NO_IRQ;
2196
2197         last = z == 2 ? d : d + z - 1;
2198         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2199                                      DESCRIPTOR_STATUS |
2200                                      DESCRIPTOR_BRANCH_ALWAYS |
2201                                      irq);
2202
2203         context_append(&ctx->context, d, z, header_z);
2204
2205         return 0;
2206 }
2207
2208 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2209                                              struct fw_iso_packet *packet,
2210                                              struct fw_iso_buffer *buffer,
2211                                              unsigned long payload)
2212 {
2213         struct iso_context *ctx = container_of(base, struct iso_context, base);
2214         struct db_descriptor *db = NULL;
2215         struct descriptor *d;
2216         struct fw_iso_packet *p;
2217         dma_addr_t d_bus, page_bus;
2218         u32 z, header_z, length, rest;
2219         int page, offset, packet_count, header_size;
2220
2221         /*
2222          * FIXME: Cycle lost behavior should be configurable: lose
2223          * packet, retransmit or terminate..
2224          */
2225
2226         p = packet;
2227         z = 2;
2228
2229         /*
2230          * The OHCI controller puts the isochronous header and trailer in the
2231          * buffer, so we need at least 8 bytes.
2232          */
2233         packet_count = p->header_length / ctx->base.header_size;
2234         header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2235
2236         /* Get header size in number of descriptors. */
2237         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2238         page     = payload >> PAGE_SHIFT;
2239         offset   = payload & ~PAGE_MASK;
2240         rest     = p->payload_length;
2241         /*
2242          * The controllers I've tested have not worked correctly when
2243          * second_req_count is zero.  Rather than do something we know won't
2244          * work, return an error
2245          */
2246         if (rest == 0)
2247                 return -EINVAL;
2248
2249         /* FIXME: make packet-per-buffer/dual-buffer a context option */
2250         while (rest > 0) {
2251                 d = context_get_descriptors(&ctx->context,
2252                                             z + header_z, &d_bus);
2253                 if (d == NULL)
2254                         return -ENOMEM;
2255
2256                 db = (struct db_descriptor *) d;
2257                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2258                                           DESCRIPTOR_BRANCH_ALWAYS);
2259                 db->first_size =
2260                     cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2261                 if (p->skip && rest == p->payload_length) {
2262                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2263                         db->first_req_count = db->first_size;
2264                 } else {
2265                         db->first_req_count = cpu_to_le16(header_size);
2266                 }
2267                 db->first_res_count = db->first_req_count;
2268                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2269
2270                 if (p->skip && rest == p->payload_length)
2271                         length = 4;
2272                 else if (offset + rest < PAGE_SIZE)
2273                         length = rest;
2274                 else
2275                         length = PAGE_SIZE - offset;
2276
2277                 db->second_req_count = cpu_to_le16(length);
2278                 db->second_res_count = db->second_req_count;
2279                 page_bus = page_private(buffer->pages[page]);
2280                 db->second_buffer = cpu_to_le32(page_bus + offset);
2281
2282                 if (p->interrupt && length == rest)
2283                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2284
2285                 context_append(&ctx->context, d, z, header_z);
2286                 offset = (offset + length) & ~PAGE_MASK;
2287                 rest -= length;
2288                 if (offset == 0)
2289                         page++;
2290         }
2291
2292         return 0;
2293 }
2294
2295 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2296                                         struct fw_iso_packet *packet,
2297                                         struct fw_iso_buffer *buffer,
2298                                         unsigned long payload)
2299 {
2300         struct iso_context *ctx = container_of(base, struct iso_context, base);
2301         struct descriptor *d, *pd;
2302         struct fw_iso_packet *p = packet;
2303         dma_addr_t d_bus, page_bus;
2304         u32 z, header_z, rest;
2305         int i, j, length;
2306         int page, offset, packet_count, header_size, payload_per_buffer;
2307
2308         /*
2309          * The OHCI controller puts the isochronous header and trailer in the
2310          * buffer, so we need at least 8 bytes.
2311          */
2312         packet_count = p->header_length / ctx->base.header_size;
2313         header_size  = max(ctx->base.header_size, (size_t)8);
2314
2315         /* Get header size in number of descriptors. */
2316         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2317         page     = payload >> PAGE_SHIFT;
2318         offset   = payload & ~PAGE_MASK;
2319         payload_per_buffer = p->payload_length / packet_count;
2320
2321         for (i = 0; i < packet_count; i++) {
2322                 /* d points to the header descriptor */
2323                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2324                 d = context_get_descriptors(&ctx->context,
2325                                 z + header_z, &d_bus);
2326                 if (d == NULL)
2327                         return -ENOMEM;
2328
2329                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2330                                               DESCRIPTOR_INPUT_MORE);
2331                 if (p->skip && i == 0)
2332                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2333                 d->req_count    = cpu_to_le16(header_size);
2334                 d->res_count    = d->req_count;
2335                 d->transfer_status = 0;
2336                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2337
2338                 rest = payload_per_buffer;
2339                 pd = d;
2340                 for (j = 1; j < z; j++) {
2341                         pd++;
2342                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2343                                                   DESCRIPTOR_INPUT_MORE);
2344
2345                         if (offset + rest < PAGE_SIZE)
2346                                 length = rest;
2347                         else
2348                                 length = PAGE_SIZE - offset;
2349                         pd->req_count = cpu_to_le16(length);
2350                         pd->res_count = pd->req_count;
2351                         pd->transfer_status = 0;
2352
2353                         page_bus = page_private(buffer->pages[page]);
2354                         pd->data_address = cpu_to_le32(page_bus + offset);
2355
2356                         offset = (offset + length) & ~PAGE_MASK;
2357                         rest -= length;
2358                         if (offset == 0)
2359                                 page++;
2360                 }
2361                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2362                                           DESCRIPTOR_INPUT_LAST |
2363                                           DESCRIPTOR_BRANCH_ALWAYS);
2364                 if (p->interrupt && i == packet_count - 1)
2365                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2366
2367                 context_append(&ctx->context, d, z, header_z);
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int ohci_queue_iso(struct fw_iso_context *base,
2374                           struct fw_iso_packet *packet,
2375                           struct fw_iso_buffer *buffer,
2376                           unsigned long payload)
2377 {
2378         struct iso_context *ctx = container_of(base, struct iso_context, base);
2379         unsigned long flags;
2380         int ret;
2381
2382         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2383         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2384                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2385         else if (ctx->context.ohci->use_dualbuffer)
2386                 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2387                                                         buffer, payload);
2388         else
2389                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2390                                                         buffer, payload);
2391         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2392
2393         return ret;
2394 }
2395
2396 static const struct fw_card_driver ohci_driver = {
2397         .enable                 = ohci_enable,
2398         .update_phy_reg         = ohci_update_phy_reg,
2399         .set_config_rom         = ohci_set_config_rom,
2400         .send_request           = ohci_send_request,
2401         .send_response          = ohci_send_response,
2402         .cancel_packet          = ohci_cancel_packet,
2403         .enable_phys_dma        = ohci_enable_phys_dma,
2404         .get_bus_time           = ohci_get_bus_time,
2405
2406         .allocate_iso_context   = ohci_allocate_iso_context,
2407         .free_iso_context       = ohci_free_iso_context,
2408         .queue_iso              = ohci_queue_iso,
2409         .start_iso              = ohci_start_iso,
2410         .stop_iso               = ohci_stop_iso,
2411 };
2412
2413 #ifdef CONFIG_PPC_PMAC
2414 static void ohci_pmac_on(struct pci_dev *dev)
2415 {
2416         if (machine_is(powermac)) {
2417                 struct device_node *ofn = pci_device_to_OF_node(dev);
2418
2419                 if (ofn) {
2420                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2421                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2422                 }
2423         }
2424 }
2425
2426 static void ohci_pmac_off(struct pci_dev *dev)
2427 {
2428         if (machine_is(powermac)) {
2429                 struct device_node *ofn = pci_device_to_OF_node(dev);
2430
2431                 if (ofn) {
2432                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2433                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2434                 }
2435         }
2436 }
2437 #else
2438 #define ohci_pmac_on(dev)
2439 #define ohci_pmac_off(dev)
2440 #endif /* CONFIG_PPC_PMAC */
2441
2442 #define PCI_VENDOR_ID_AGERE             PCI_VENDOR_ID_ATT
2443 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
2444 #define PCI_DEVICE_ID_TI_TSB43AB23      0x8024
2445
2446 static int __devinit pci_probe(struct pci_dev *dev,
2447                                const struct pci_device_id *ent)
2448 {
2449         struct fw_ohci *ohci;
2450         u32 bus_options, max_receive, link_speed, version;
2451         u64 guid;
2452         int err;
2453         size_t size;
2454
2455         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2456         if (ohci == NULL) {
2457                 err = -ENOMEM;
2458                 goto fail;
2459         }
2460
2461         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2462
2463         ohci_pmac_on(dev);
2464
2465         err = pci_enable_device(dev);
2466         if (err) {
2467                 fw_error("Failed to enable OHCI hardware\n");
2468                 goto fail_free;
2469         }
2470
2471         pci_set_master(dev);
2472         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2473         pci_set_drvdata(dev, ohci);
2474
2475         spin_lock_init(&ohci->lock);
2476
2477         tasklet_init(&ohci->bus_reset_tasklet,
2478                      bus_reset_tasklet, (unsigned long)ohci);
2479
2480         err = pci_request_region(dev, 0, ohci_driver_name);
2481         if (err) {
2482                 fw_error("MMIO resource unavailable\n");
2483                 goto fail_disable;
2484         }
2485
2486         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2487         if (ohci->registers == NULL) {
2488                 fw_error("Failed to remap registers\n");
2489                 err = -ENXIO;
2490                 goto fail_iomem;
2491         }
2492
2493         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2494         ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2495
2496         /* dual-buffer mode is broken if more than one IR context is active */
2497         if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2498             dev->device == PCI_DEVICE_ID_AGERE_FW643)
2499                 ohci->use_dualbuffer = false;
2500
2501         /* dual-buffer mode is broken */
2502         if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2503             dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2504                 ohci->use_dualbuffer = false;
2505
2506 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2507 #if !defined(CONFIG_X86_32)
2508         /* dual-buffer mode is broken with descriptor addresses above 2G */
2509         if (dev->vendor == PCI_VENDOR_ID_TI &&
2510             (dev->device == PCI_DEVICE_ID_TI_TSB43AB22 ||
2511              dev->device == PCI_DEVICE_ID_TI_TSB43AB23))
2512                 ohci->use_dualbuffer = false;
2513 #endif
2514
2515 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2516         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2517                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2518 #endif
2519         ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2520
2521         ar_context_init(&ohci->ar_request_ctx, ohci,
2522                         OHCI1394_AsReqRcvContextControlSet);
2523
2524         ar_context_init(&ohci->ar_response_ctx, ohci,
2525                         OHCI1394_AsRspRcvContextControlSet);
2526
2527         context_init(&ohci->at_request_ctx, ohci,
2528                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2529
2530         context_init(&ohci->at_response_ctx, ohci,
2531                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2532
2533         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2534         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2535         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2536         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2537         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2538
2539         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2540         ohci->ir_context_channels = ~0ULL;
2541         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2542         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2543         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2544         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2545
2546         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2547                 err = -ENOMEM;
2548                 goto fail_contexts;
2549         }
2550
2551         /* self-id dma buffer allocation */
2552         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2553                                                SELF_ID_BUF_SIZE,
2554                                                &ohci->self_id_bus,
2555                                                GFP_KERNEL);
2556         if (ohci->self_id_cpu == NULL) {
2557                 err = -ENOMEM;
2558                 goto fail_contexts;
2559         }
2560
2561         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2562         max_receive = (bus_options >> 12) & 0xf;
2563         link_speed = bus_options & 0x7;
2564         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2565                 reg_read(ohci, OHCI1394_GUIDLo);
2566
2567         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2568         if (err)
2569                 goto fail_self_id;
2570
2571         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2572                   dev_name(&dev->dev), version >> 16, version & 0xff);
2573
2574         return 0;
2575
2576  fail_self_id:
2577         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2578                           ohci->self_id_cpu, ohci->self_id_bus);
2579  fail_contexts:
2580         kfree(ohci->ir_context_list);
2581         kfree(ohci->it_context_list);
2582         context_release(&ohci->at_response_ctx);
2583         context_release(&ohci->at_request_ctx);
2584         ar_context_release(&ohci->ar_response_ctx);
2585         ar_context_release(&ohci->ar_request_ctx);
2586         pci_iounmap(dev, ohci->registers);
2587  fail_iomem:
2588         pci_release_region(dev, 0);
2589  fail_disable:
2590         pci_disable_device(dev);
2591  fail_free:
2592         kfree(&ohci->card);
2593         ohci_pmac_off(dev);
2594  fail:
2595         if (err == -ENOMEM)
2596                 fw_error("Out of memory\n");
2597
2598         return err;
2599 }
2600
2601 static void pci_remove(struct pci_dev *dev)
2602 {
2603         struct fw_ohci *ohci;
2604
2605         ohci = pci_get_drvdata(dev);
2606         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2607         flush_writes(ohci);
2608         fw_core_remove_card(&ohci->card);
2609
2610         /*
2611          * FIXME: Fail all pending packets here, now that the upper
2612          * layers can't queue any more.
2613          */
2614
2615         software_reset(ohci);
2616         free_irq(dev->irq, ohci);
2617
2618         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2619                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2620                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2621         if (ohci->config_rom)
2622                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2623                                   ohci->config_rom, ohci->config_rom_bus);
2624         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2625                           ohci->self_id_cpu, ohci->self_id_bus);
2626         ar_context_release(&ohci->ar_request_ctx);
2627         ar_context_release(&ohci->ar_response_ctx);
2628         context_release(&ohci->at_request_ctx);
2629         context_release(&ohci->at_response_ctx);
2630         kfree(ohci->it_context_list);
2631         kfree(ohci->ir_context_list);
2632         pci_iounmap(dev, ohci->registers);
2633         pci_release_region(dev, 0);
2634         pci_disable_device(dev);
2635         kfree(&ohci->card);
2636         ohci_pmac_off(dev);
2637
2638         fw_notify("Removed fw-ohci device.\n");
2639 }
2640
2641 #ifdef CONFIG_PM
2642 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2643 {
2644         struct fw_ohci *ohci = pci_get_drvdata(dev);
2645         int err;
2646
2647         software_reset(ohci);
2648         free_irq(dev->irq, ohci);
2649         err = pci_save_state(dev);
2650         if (err) {
2651                 fw_error("pci_save_state failed\n");
2652                 return err;
2653         }
2654         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2655         if (err)
2656                 fw_error("pci_set_power_state failed with %d\n", err);
2657         ohci_pmac_off(dev);
2658
2659         return 0;
2660 }
2661
2662 static int pci_resume(struct pci_dev *dev)
2663 {
2664         struct fw_ohci *ohci = pci_get_drvdata(dev);
2665         int err;
2666
2667         ohci_pmac_on(dev);
2668         pci_set_power_state(dev, PCI_D0);
2669         pci_restore_state(dev);
2670         err = pci_enable_device(dev);
2671         if (err) {
2672                 fw_error("pci_enable_device failed\n");
2673                 return err;
2674         }
2675
2676         return ohci_enable(&ohci->card, NULL, 0);
2677 }
2678 #endif
2679
2680 static struct pci_device_id pci_table[] = {
2681         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2682         { }
2683 };
2684
2685 MODULE_DEVICE_TABLE(pci, pci_table);
2686
2687 static struct pci_driver fw_ohci_pci_driver = {
2688         .name           = ohci_driver_name,
2689         .id_table       = pci_table,
2690         .probe          = pci_probe,
2691         .remove         = pci_remove,
2692 #ifdef CONFIG_PM
2693         .resume         = pci_resume,
2694         .suspend        = pci_suspend,
2695 #endif
2696 };
2697
2698 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2699 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2700 MODULE_LICENSE("GPL");
2701
2702 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2703 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2704 MODULE_ALIAS("ohci1394");
2705 #endif
2706
2707 static int __init fw_ohci_init(void)
2708 {
2709         return pci_register_driver(&fw_ohci_pci_driver);
2710 }
2711
2712 static void __exit fw_ohci_cleanup(void)
2713 {
2714         pci_unregister_driver(&fw_ohci_pci_driver);
2715 }
2716
2717 module_init(fw_ohci_init);
2718 module_exit(fw_ohci_cleanup);