2 * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
4 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * Author: Yang, Bin <bin.yang@intel.com>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
21 #include <linux/seq_file.h>
22 #include <linux/bitops.h>
23 #include <linux/regmap.h>
24 #include <linux/mfd/intel_soc_pmic.h>
26 #define CRYSTALCOVE_GPIO_NUM 16
27 #define CRYSTALCOVE_VGPIO_NUM 94
29 #define UPDATE_IRQ_TYPE BIT(0)
30 #define UPDATE_IRQ_MASK BIT(1)
34 #define MGPIO0IRQS0 0x19
35 #define MGPIO1IRQS0 0x1a
36 #define MGPIO0IRQSX 0x1b
37 #define MGPIO1IRQSX 0x1c
38 #define GPIO0P0CTLO 0x2b
39 #define GPIO0P0CTLI 0x33
40 #define GPIO1P0CTLO 0x3b
41 #define GPIO1P0CTLI 0x43
43 #define CTLI_INTCNT_DIS (0)
44 #define CTLI_INTCNT_NE (1 << 1)
45 #define CTLI_INTCNT_PE (2 << 1)
46 #define CTLI_INTCNT_BE (3 << 1)
48 #define CTLO_DIR_IN (0)
49 #define CTLO_DIR_OUT (1 << 5)
51 #define CTLO_DRV_CMOS (0)
52 #define CTLO_DRV_OD (1 << 4)
54 #define CTLO_DRV_REN (1 << 3)
56 #define CTLO_RVAL_2KDW (0)
57 #define CTLO_RVAL_2KUP (1 << 1)
58 #define CTLO_RVAL_50KDW (2 << 1)
59 #define CTLO_RVAL_50KUP (3 << 1)
61 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
62 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
70 * struct crystalcove_gpio - Crystal Cove GPIO controller
71 * @buslock: for bus lock/sync and unlock.
72 * @chip: the abstract gpio_chip structure.
73 * @regmap: the regmap from the parent device.
74 * @update: pending IRQ setting update, to be written to the chip upon unlock.
75 * @intcnt_value: the Interrupt Detect value to be written.
76 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
78 struct crystalcove_gpio {
79 struct mutex buslock; /* irq_bus_lock */
80 struct gpio_chip chip;
81 struct regmap *regmap;
87 static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
89 return container_of(gc, struct crystalcove_gpio, chip);
92 static inline int to_reg(int gpio, enum ctrl_register reg_type)
96 if (reg_type == CTRL_IN) {
108 return reg + gpio % 8;
111 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
114 u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
115 int mask = BIT(gpio % 8);
117 if (cg->set_irq_mask)
118 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
120 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
123 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
125 int reg = to_reg(gpio, CTRL_IN);
127 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
130 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
132 struct crystalcove_gpio *cg = to_cg(chip);
134 if (gpio > CRYSTALCOVE_VGPIO_NUM)
137 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
141 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
144 struct crystalcove_gpio *cg = to_cg(chip);
146 if (gpio > CRYSTALCOVE_VGPIO_NUM)
149 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
150 CTLO_OUTPUT_SET | value);
153 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
155 struct crystalcove_gpio *cg = to_cg(chip);
159 if (gpio > CRYSTALCOVE_VGPIO_NUM)
162 ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
169 static void crystalcove_gpio_set(struct gpio_chip *chip,
170 unsigned gpio, int value)
172 struct crystalcove_gpio *cg = to_cg(chip);
174 if (gpio > CRYSTALCOVE_VGPIO_NUM)
178 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
180 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
183 static int crystalcove_irq_type(struct irq_data *data, unsigned type)
185 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
189 cg->intcnt_value = CTLI_INTCNT_DIS;
191 case IRQ_TYPE_EDGE_BOTH:
192 cg->intcnt_value = CTLI_INTCNT_BE;
194 case IRQ_TYPE_EDGE_RISING:
195 cg->intcnt_value = CTLI_INTCNT_PE;
197 case IRQ_TYPE_EDGE_FALLING:
198 cg->intcnt_value = CTLI_INTCNT_NE;
204 cg->update |= UPDATE_IRQ_TYPE;
209 static void crystalcove_bus_lock(struct irq_data *data)
211 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
213 mutex_lock(&cg->buslock);
216 static void crystalcove_bus_sync_unlock(struct irq_data *data)
218 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
219 int gpio = data->hwirq;
221 if (cg->update & UPDATE_IRQ_TYPE)
222 crystalcove_update_irq_ctrl(cg, gpio);
223 if (cg->update & UPDATE_IRQ_MASK)
224 crystalcove_update_irq_mask(cg, gpio);
227 mutex_unlock(&cg->buslock);
230 static void crystalcove_irq_unmask(struct irq_data *data)
232 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
234 cg->set_irq_mask = false;
235 cg->update |= UPDATE_IRQ_MASK;
238 static void crystalcove_irq_mask(struct irq_data *data)
240 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
242 cg->set_irq_mask = true;
243 cg->update |= UPDATE_IRQ_MASK;
246 static struct irq_chip crystalcove_irqchip = {
247 .name = "Crystal Cove",
248 .irq_mask = crystalcove_irq_mask,
249 .irq_unmask = crystalcove_irq_unmask,
250 .irq_set_type = crystalcove_irq_type,
251 .irq_bus_lock = crystalcove_bus_lock,
252 .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
255 static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
257 struct crystalcove_gpio *cg = data;
263 if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
264 regmap_read(cg->regmap, GPIO1IRQ, &p1))
267 regmap_write(cg->regmap, GPIO0IRQ, p0);
268 regmap_write(cg->regmap, GPIO1IRQ, p1);
270 pending = p0 | p1 << 8;
272 for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
273 if (pending & BIT(gpio)) {
274 virq = irq_find_mapping(cg->chip.irqdomain, gpio);
275 generic_handle_irq(virq);
282 static void crystalcove_gpio_dbg_show(struct seq_file *s,
283 struct gpio_chip *chip)
285 struct crystalcove_gpio *cg = to_cg(chip);
287 unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
289 for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
290 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
291 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
292 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
294 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
296 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
300 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
301 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
302 ctli & 0x1 ? "hi" : "lo",
303 ctli & CTLI_INTCNT_NE ? "fall" : " ",
304 ctli & CTLI_INTCNT_PE ? "rise" : " ",
306 mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
307 mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
308 irq & BIT(offset) ? "pending" : " ");
312 static int crystalcove_gpio_probe(struct platform_device *pdev)
314 int irq = platform_get_irq(pdev, 0);
315 struct crystalcove_gpio *cg;
317 struct device *dev = pdev->dev.parent;
318 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
323 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
327 platform_set_drvdata(pdev, cg);
329 mutex_init(&cg->buslock);
330 cg->chip.label = KBUILD_MODNAME;
331 cg->chip.direction_input = crystalcove_gpio_dir_in;
332 cg->chip.direction_output = crystalcove_gpio_dir_out;
333 cg->chip.get = crystalcove_gpio_get;
334 cg->chip.set = crystalcove_gpio_set;
336 cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
337 cg->chip.can_sleep = true;
339 cg->chip.dbg_show = crystalcove_gpio_dbg_show;
340 cg->regmap = pmic->regmap;
342 retval = gpiochip_add(&cg->chip);
344 dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
348 gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
349 handle_simple_irq, IRQ_TYPE_NONE);
351 retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
352 IRQF_ONESHOT, KBUILD_MODNAME, cg);
355 dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
356 goto out_remove_gpio;
362 gpiochip_remove(&cg->chip);
366 static int crystalcove_gpio_remove(struct platform_device *pdev)
368 struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
369 int irq = platform_get_irq(pdev, 0);
371 gpiochip_remove(&cg->chip);
377 static struct platform_driver crystalcove_gpio_driver = {
378 .probe = crystalcove_gpio_probe,
379 .remove = crystalcove_gpio_remove,
381 .name = "crystal_cove_gpio",
385 module_platform_driver(crystalcove_gpio_driver);
387 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
388 MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
389 MODULE_LICENSE("GPL v2");