2 * AMD CS5535/CS5536 GPIO driver
3 * Copyright (C) 2006 Advanced Micro Devices, Inc.
4 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/spinlock.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
17 #include <linux/cs5535.h>
20 #define DRV_NAME "cs5535-gpio"
24 * 31-29,23 : reserved (always mask out)
36 * If a mask was not specified, allow all except
37 * reserved and Power Button
39 #define GPIO_DEFAULT_MASK 0x0F7FFFFF
41 static ulong mask = GPIO_DEFAULT_MASK;
42 module_param_named(mask, mask, ulong, 0444);
43 MODULE_PARM_DESC(mask, "GPIO channel mask.");
45 static struct cs5535_gpio_chip {
46 struct gpio_chip chip;
49 struct platform_device *pdev;
54 * The CS5535/CS5536 GPIOs support a number of extra features not defined
55 * by the gpio_chip API, so these are exported. For a full list of the
56 * registers, see include/linux/cs5535.h.
59 static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
62 unsigned long addr = chip->base + 0x80 + reg;
65 * According to the CS5536 errata (#36), after suspend
66 * a write to the high bank GPIO register will clear all
67 * non-selected bits; the recommended workaround is a
68 * read-modify-write operation.
70 * Don't apply this errata to the edge status GPIOs, as writing
71 * to their lower bits will clear them.
73 if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
75 val |= (inl(addr) & 0xffff); /* ignore the high bits */
77 val |= (inl(addr) ^ (val >> 16));
82 static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
86 /* low bank register */
87 outl(1 << offset, chip->base + reg);
89 /* high bank register */
90 errata_outl(chip, 1 << (offset - 16), reg);
93 void cs5535_gpio_set(unsigned offset, unsigned int reg)
95 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
98 spin_lock_irqsave(&chip->lock, flags);
99 __cs5535_gpio_set(chip, offset, reg);
100 spin_unlock_irqrestore(&chip->lock, flags);
102 EXPORT_SYMBOL_GPL(cs5535_gpio_set);
104 static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
108 /* low bank register */
109 outl(1 << (offset + 16), chip->base + reg);
111 /* high bank register */
112 errata_outl(chip, 1 << offset, reg);
115 void cs5535_gpio_clear(unsigned offset, unsigned int reg)
117 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
120 spin_lock_irqsave(&chip->lock, flags);
121 __cs5535_gpio_clear(chip, offset, reg);
122 spin_unlock_irqrestore(&chip->lock, flags);
124 EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
126 int cs5535_gpio_isset(unsigned offset, unsigned int reg)
128 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
132 spin_lock_irqsave(&chip->lock, flags);
134 /* low bank register */
135 val = inl(chip->base + reg);
137 /* high bank register */
138 val = inl(chip->base + 0x80 + reg);
141 spin_unlock_irqrestore(&chip->lock, flags);
143 return (val & (1 << offset)) ? 1 : 0;
145 EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
147 int cs5535_gpio_set_irq(unsigned group, unsigned irq)
151 if (group > 7 || irq > 15)
154 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
156 lo &= ~(0xF << (group * 4));
157 lo |= (irq & 0xF) << (group * 4);
159 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
162 EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
164 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
166 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
167 uint32_t shift = (offset % 8) * 4;
173 else if (offset >= 16)
175 else if (offset >= 8)
180 spin_lock_irqsave(&chip->lock, flags);
181 val = inl(chip->base + offset);
183 /* Clear whatever was there before */
184 val &= ~(0xF << shift);
186 /* Set the new value */
187 val |= ((pair & 7) << shift);
189 /* Set the PME bit if this is a PME event */
191 val |= (1 << (shift + 3));
193 outl(val, chip->base + offset);
194 spin_unlock_irqrestore(&chip->lock, flags);
196 EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
199 * Generic gpio_chip API support.
202 static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
204 struct cs5535_gpio_chip *chip =
205 container_of(c, struct cs5535_gpio_chip, chip);
208 spin_lock_irqsave(&chip->lock, flags);
210 /* check if this pin is available */
211 if ((mask & (1 << offset)) == 0) {
212 dev_info(&chip->pdev->dev,
213 "pin %u is not available (check mask)\n", offset);
214 spin_unlock_irqrestore(&chip->lock, flags);
218 /* disable output aux 1 & 2 on this pin */
219 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
220 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
222 /* disable input aux 1 on this pin */
223 __cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
225 spin_unlock_irqrestore(&chip->lock, flags);
230 static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
232 return cs5535_gpio_isset(offset, GPIO_READ_BACK);
235 static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
238 cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
240 cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
243 static int chip_direction_input(struct gpio_chip *c, unsigned offset)
245 struct cs5535_gpio_chip *chip =
246 container_of(c, struct cs5535_gpio_chip, chip);
249 spin_lock_irqsave(&chip->lock, flags);
250 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
251 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
252 spin_unlock_irqrestore(&chip->lock, flags);
257 static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
259 struct cs5535_gpio_chip *chip =
260 container_of(c, struct cs5535_gpio_chip, chip);
263 spin_lock_irqsave(&chip->lock, flags);
265 __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
266 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
268 __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
270 __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
272 spin_unlock_irqrestore(&chip->lock, flags);
277 static const char * const cs5535_gpio_names[] = {
278 "GPIO0", "GPIO1", "GPIO2", "GPIO3",
279 "GPIO4", "GPIO5", "GPIO6", "GPIO7",
280 "GPIO8", "GPIO9", "GPIO10", "GPIO11",
281 "GPIO12", "GPIO13", "GPIO14", "GPIO15",
282 "GPIO16", "GPIO17", "GPIO18", "GPIO19",
283 "GPIO20", "GPIO21", "GPIO22", NULL,
284 "GPIO24", "GPIO25", "GPIO26", "GPIO27",
285 "GPIO28", NULL, NULL, NULL,
288 static struct cs5535_gpio_chip cs5535_gpio_chip = {
290 .owner = THIS_MODULE,
295 .names = cs5535_gpio_names,
296 .request = chip_gpio_request,
298 .get = chip_gpio_get,
299 .set = chip_gpio_set,
301 .direction_input = chip_direction_input,
302 .direction_output = chip_direction_output,
306 static int cs5535_gpio_probe(struct platform_device *pdev)
308 struct resource *res;
310 ulong mask_orig = mask;
312 /* There are two ways to get the GPIO base address; one is by
313 * fetching it from MSR_LBAR_GPIO, the other is by reading the
314 * PCI BAR info. The latter method is easier (especially across
315 * different architectures), so we'll stick with that for now. If
316 * it turns out to be unreliable in the face of crappy BIOSes, we
317 * can always go back to using MSRs.. */
319 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
321 dev_err(&pdev->dev, "can't fetch device resource info\n");
325 if (!request_region(res->start, resource_size(res), pdev->name)) {
326 dev_err(&pdev->dev, "can't request region\n");
330 /* set up the driver-specific struct */
331 cs5535_gpio_chip.base = res->start;
332 cs5535_gpio_chip.pdev = pdev;
333 spin_lock_init(&cs5535_gpio_chip.lock);
335 dev_info(&pdev->dev, "reserved resource region %pR\n", res);
337 /* mask out reserved pins */
340 /* do not allow pin 28, Power Button, as there's special handling
341 * in the PMC needed. (note 12, p. 48) */
344 if (mask_orig != mask)
345 dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
348 /* finally, register with the generic GPIO API */
349 err = gpiochip_add(&cs5535_gpio_chip.chip);
356 release_region(res->start, resource_size(res));
361 static int cs5535_gpio_remove(struct platform_device *pdev)
365 gpiochip_remove(&cs5535_gpio_chip.chip);
367 r = platform_get_resource(pdev, IORESOURCE_IO, 0);
368 release_region(r->start, resource_size(r));
372 static struct platform_driver cs5535_gpio_driver = {
375 .owner = THIS_MODULE,
377 .probe = cs5535_gpio_probe,
378 .remove = cs5535_gpio_remove,
381 module_platform_driver(cs5535_gpio_driver);
383 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
384 MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
385 MODULE_LICENSE("GPL");
386 MODULE_ALIAS("platform:" DRV_NAME);