2 * Driver for the Diolan DLN-2 USB-GPIO adapter
4 * Copyright (c) 2014 Intel Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/types.h>
15 #include <linux/irqdomain.h>
16 #include <linux/irq.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/gpio.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/platform_device.h>
21 #include <linux/mfd/dln2.h>
23 #define DLN2_GPIO_ID 0x01
25 #define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
26 #define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
27 #define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
28 #define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
29 #define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
30 #define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
31 #define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
32 #define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
33 #define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
34 #define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
35 #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
36 #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
37 #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
38 #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
40 #define DLN2_GPIO_EVENT_NONE 0
41 #define DLN2_GPIO_EVENT_CHANGE 1
42 #define DLN2_GPIO_EVENT_LVL_HIGH 2
43 #define DLN2_GPIO_EVENT_LVL_LOW 3
44 #define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
45 #define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
46 #define DLN2_GPIO_EVENT_MASK 0x0F
48 #define DLN2_GPIO_MAX_PINS 32
50 struct dln2_irq_work {
51 struct work_struct work;
52 struct dln2_gpio *dln2;
58 struct platform_device *pdev;
59 struct gpio_chip gpio;
62 * Cache pin direction to save us one transfer, since the hardware has
63 * separate commands to read the in and out values.
65 DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
67 /* active IRQs - not synced to hardware */
68 DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
69 struct dln2_irq_work *irq_work;
72 struct dln2_gpio_pin {
76 struct dln2_gpio_pin_val {
81 static int dln2_gpio_get_pin_count(struct platform_device *pdev)
85 int len = sizeof(count);
87 ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
90 if (len < sizeof(count))
93 return le16_to_cpu(count);
96 static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
98 struct dln2_gpio_pin req = {
99 .pin = cpu_to_le16(pin),
102 return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
105 static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
108 struct dln2_gpio_pin req = {
109 .pin = cpu_to_le16(pin),
111 struct dln2_gpio_pin_val rsp;
112 int len = sizeof(rsp);
114 ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
117 if (len < sizeof(rsp) || req.pin != rsp.pin)
123 static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
127 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
133 static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
137 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
143 static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
144 unsigned int pin, int value)
146 struct dln2_gpio_pin_val req = {
147 .pin = cpu_to_le16(pin),
151 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
155 #define DLN2_GPIO_DIRECTION_IN 0
156 #define DLN2_GPIO_DIRECTION_OUT 1
158 static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
160 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
161 struct dln2_gpio_pin req = {
162 .pin = cpu_to_le16(offset),
164 struct dln2_gpio_pin_val rsp;
165 int len = sizeof(rsp);
168 ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
172 /* cache the pin direction */
173 ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
174 &req, sizeof(req), &rsp, &len);
177 if (len < sizeof(rsp) || req.pin != rsp.pin) {
183 case DLN2_GPIO_DIRECTION_IN:
184 clear_bit(offset, dln2->output_enabled);
186 case DLN2_GPIO_DIRECTION_OUT:
187 set_bit(offset, dln2->output_enabled);
195 dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
199 static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
201 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
203 dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
206 static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
208 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
210 if (test_bit(offset, dln2->output_enabled))
211 return GPIOF_DIR_OUT;
216 static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
218 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
221 dir = dln2_gpio_get_direction(chip, offset);
225 if (dir == GPIOF_DIR_IN)
226 return dln2_gpio_pin_get_in_val(dln2, offset);
228 return dln2_gpio_pin_get_out_val(dln2, offset);
231 static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
233 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
235 dln2_gpio_pin_set_out_val(dln2, offset, value);
238 static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
241 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
242 struct dln2_gpio_pin_val req = {
243 .pin = cpu_to_le16(offset),
248 ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
253 if (dir == DLN2_GPIO_DIRECTION_OUT)
254 set_bit(offset, dln2->output_enabled);
256 clear_bit(offset, dln2->output_enabled);
261 static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
263 return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
266 static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
269 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
272 ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
276 return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
279 static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
282 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
283 __le32 duration = cpu_to_le32(debounce);
285 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
286 &duration, sizeof(duration));
289 static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
290 unsigned type, unsigned period)
297 .pin = cpu_to_le16(pin),
299 .period = cpu_to_le16(period),
302 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
306 static void dln2_irq_work(struct work_struct *w)
308 struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
309 struct dln2_gpio *dln2 = iw->dln2;
310 u8 type = iw->type & DLN2_GPIO_EVENT_MASK;
312 if (test_bit(iw->pin, dln2->unmasked_irqs))
313 dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
315 dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
318 static void dln2_irq_unmask(struct irq_data *irqd)
320 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
321 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
322 int pin = irqd_to_hwirq(irqd);
324 set_bit(pin, dln2->unmasked_irqs);
325 schedule_work(&dln2->irq_work[pin].work);
328 static void dln2_irq_mask(struct irq_data *irqd)
330 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
331 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
332 int pin = irqd_to_hwirq(irqd);
334 clear_bit(pin, dln2->unmasked_irqs);
335 schedule_work(&dln2->irq_work[pin].work);
338 static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
340 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
341 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
342 int pin = irqd_to_hwirq(irqd);
345 case IRQ_TYPE_LEVEL_HIGH:
346 dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
348 case IRQ_TYPE_LEVEL_LOW:
349 dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
351 case IRQ_TYPE_EDGE_BOTH:
352 dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
354 case IRQ_TYPE_EDGE_RISING:
355 dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
357 case IRQ_TYPE_EDGE_FALLING:
358 dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
367 static struct irq_chip dln2_gpio_irqchip = {
369 .irq_mask = dln2_irq_mask,
370 .irq_unmask = dln2_irq_unmask,
371 .irq_set_type = dln2_irq_set_type,
374 static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
375 const void *data, int len)
383 } __packed *event = data;
384 struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
386 if (len < sizeof(*event)) {
387 dev_err(dln2->gpio.dev, "short event message\n");
391 pin = le16_to_cpu(event->pin);
392 if (pin >= dln2->gpio.ngpio) {
393 dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
397 irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
399 dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
403 switch (dln2->irq_work[pin].type) {
404 case DLN2_GPIO_EVENT_CHANGE_RISING:
406 generic_handle_irq(irq);
408 case DLN2_GPIO_EVENT_CHANGE_FALLING:
410 generic_handle_irq(irq);
413 generic_handle_irq(irq);
417 static int dln2_gpio_probe(struct platform_device *pdev)
419 struct dln2_gpio *dln2;
420 struct device *dev = &pdev->dev;
424 pins = dln2_gpio_get_pin_count(pdev);
426 dev_err(dev, "failed to get pin count: %d\n", pins);
429 if (pins > DLN2_GPIO_MAX_PINS) {
430 pins = DLN2_GPIO_MAX_PINS;
431 dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
434 dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
438 dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
439 sizeof(struct dln2_irq_work), GFP_KERNEL);
442 for (i = 0; i < pins; i++) {
443 INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
444 dln2->irq_work[i].pin = i;
445 dln2->irq_work[i].dln2 = dln2;
450 dln2->gpio.label = "dln2";
451 dln2->gpio.dev = dev;
452 dln2->gpio.owner = THIS_MODULE;
453 dln2->gpio.base = -1;
454 dln2->gpio.ngpio = pins;
455 dln2->gpio.exported = true;
456 dln2->gpio.can_sleep = true;
457 dln2->gpio.irq_not_threaded = true;
458 dln2->gpio.set = dln2_gpio_set;
459 dln2->gpio.get = dln2_gpio_get;
460 dln2->gpio.request = dln2_gpio_request;
461 dln2->gpio.free = dln2_gpio_free;
462 dln2->gpio.get_direction = dln2_gpio_get_direction;
463 dln2->gpio.direction_input = dln2_gpio_direction_input;
464 dln2->gpio.direction_output = dln2_gpio_direction_output;
465 dln2->gpio.set_debounce = dln2_gpio_set_debounce;
467 platform_set_drvdata(pdev, dln2);
469 ret = gpiochip_add(&dln2->gpio);
471 dev_err(dev, "failed to add gpio chip: %d\n", ret);
475 ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
476 handle_simple_irq, IRQ_TYPE_NONE);
478 dev_err(dev, "failed to add irq chip: %d\n", ret);
479 goto out_gpiochip_remove;
482 ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
485 dev_err(dev, "failed to register event cb: %d\n", ret);
486 goto out_gpiochip_remove;
492 gpiochip_remove(&dln2->gpio);
497 static int dln2_gpio_remove(struct platform_device *pdev)
499 struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
502 dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
503 for (i = 0; i < dln2->gpio.ngpio; i++)
504 flush_work(&dln2->irq_work[i].work);
505 gpiochip_remove(&dln2->gpio);
510 static struct platform_driver dln2_gpio_driver = {
511 .driver.name = "dln2-gpio",
512 .probe = dln2_gpio_probe,
513 .remove = dln2_gpio_remove,
516 module_platform_driver(dln2_gpio_driver);
518 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
519 MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
520 MODULE_LICENSE("GPL v2");
521 MODULE_ALIAS("platform:dln2-gpio");