2 * Copyright (c) 2011 Jamie Iles
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * All enquiries to support@picochip.com
10 #include <linux/basic_mmio_gpio.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/platform_data/gpio-dwapb.h>
25 #include <linux/slab.h>
27 #define GPIO_SWPORTA_DR 0x00
28 #define GPIO_SWPORTA_DDR 0x04
29 #define GPIO_SWPORTB_DR 0x0c
30 #define GPIO_SWPORTB_DDR 0x10
31 #define GPIO_SWPORTC_DR 0x18
32 #define GPIO_SWPORTC_DDR 0x1c
33 #define GPIO_SWPORTD_DR 0x24
34 #define GPIO_SWPORTD_DDR 0x28
35 #define GPIO_INTEN 0x30
36 #define GPIO_INTMASK 0x34
37 #define GPIO_INTTYPE_LEVEL 0x38
38 #define GPIO_INT_POLARITY 0x3c
39 #define GPIO_INTSTATUS 0x40
40 #define GPIO_PORTA_EOI 0x4c
41 #define GPIO_EXT_PORTA 0x50
42 #define GPIO_EXT_PORTB 0x54
43 #define GPIO_EXT_PORTC 0x58
44 #define GPIO_EXT_PORTD 0x5c
46 #define DWAPB_MAX_PORTS 4
47 #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
48 #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
49 #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
53 struct dwapb_gpio_port {
54 struct bgpio_chip bgc;
56 struct dwapb_gpio *gpio;
62 struct dwapb_gpio_port *ports;
63 unsigned int nr_ports;
64 struct irq_domain *domain;
67 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
69 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
70 void __iomem *reg_base = gpio->regs;
72 return bgc->read_reg(reg_base + offset);
75 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
78 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
79 void __iomem *reg_base = gpio->regs;
81 bgc->write_reg(reg_base + offset, val);
84 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
86 struct bgpio_chip *bgc = to_bgpio_chip(gc);
87 struct dwapb_gpio_port *port = container_of(bgc, struct
88 dwapb_gpio_port, bgc);
89 struct dwapb_gpio *gpio = port->gpio;
91 return irq_find_mapping(gpio->domain, offset);
94 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
96 u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
98 if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
103 dwapb_write(gpio, GPIO_INT_POLARITY, v);
106 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
108 u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
109 u32 ret = irq_status;
112 int hwirq = fls(irq_status) - 1;
113 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
115 generic_handle_irq(gpio_irq);
116 irq_status &= ~BIT(hwirq);
118 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
119 == IRQ_TYPE_EDGE_BOTH)
120 dwapb_toggle_trigger(gpio, hwirq);
126 static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
128 struct dwapb_gpio *gpio = irq_get_handler_data(irq);
129 struct irq_chip *chip = irq_desc_get_chip(desc);
134 chip->irq_eoi(irq_desc_get_irq_data(desc));
137 static void dwapb_irq_enable(struct irq_data *d)
139 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
140 struct dwapb_gpio *gpio = igc->private;
141 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
145 spin_lock_irqsave(&bgc->lock, flags);
146 val = dwapb_read(gpio, GPIO_INTEN);
147 val |= BIT(d->hwirq);
148 dwapb_write(gpio, GPIO_INTEN, val);
149 spin_unlock_irqrestore(&bgc->lock, flags);
152 static void dwapb_irq_disable(struct irq_data *d)
154 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
155 struct dwapb_gpio *gpio = igc->private;
156 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
160 spin_lock_irqsave(&bgc->lock, flags);
161 val = dwapb_read(gpio, GPIO_INTEN);
162 val &= ~BIT(d->hwirq);
163 dwapb_write(gpio, GPIO_INTEN, val);
164 spin_unlock_irqrestore(&bgc->lock, flags);
167 static int dwapb_irq_reqres(struct irq_data *d)
169 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
170 struct dwapb_gpio *gpio = igc->private;
171 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
173 if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
174 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
181 static void dwapb_irq_relres(struct irq_data *d)
183 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
184 struct dwapb_gpio *gpio = igc->private;
185 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
187 gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
190 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
192 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
193 struct dwapb_gpio *gpio = igc->private;
194 struct bgpio_chip *bgc = &gpio->ports[0].bgc;
196 unsigned long level, polarity, flags;
198 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
199 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
202 spin_lock_irqsave(&bgc->lock, flags);
203 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
204 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
207 case IRQ_TYPE_EDGE_BOTH:
209 dwapb_toggle_trigger(gpio, bit);
211 case IRQ_TYPE_EDGE_RISING:
213 polarity |= BIT(bit);
215 case IRQ_TYPE_EDGE_FALLING:
217 polarity &= ~BIT(bit);
219 case IRQ_TYPE_LEVEL_HIGH:
221 polarity |= BIT(bit);
223 case IRQ_TYPE_LEVEL_LOW:
225 polarity &= ~BIT(bit);
229 irq_setup_alt_chip(d, type);
231 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
232 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
233 spin_unlock_irqrestore(&bgc->lock, flags);
238 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
241 struct dwapb_gpio *gpio = dev_id;
243 worked = dwapb_do_irq(gpio);
245 return worked ? IRQ_HANDLED : IRQ_NONE;
248 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
249 struct dwapb_gpio_port *port,
250 struct dwapb_port_property *pp)
252 struct gpio_chip *gc = &port->bgc.gc;
253 struct device_node *node = pp->node;
254 struct irq_chip_generic *irq_gc = NULL;
255 unsigned int hwirq, ngpio = gc->ngpio;
256 struct irq_chip_type *ct;
259 gpio->domain = irq_domain_add_linear(node, ngpio,
260 &irq_generic_chip_ops, gpio);
264 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
265 "gpio-dwapb", handle_level_irq,
267 IRQ_GC_INIT_NESTED_LOCK);
269 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
270 irq_domain_remove(gpio->domain);
275 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
277 irq_domain_remove(gpio->domain);
282 irq_gc->reg_base = gpio->regs;
283 irq_gc->private = gpio;
285 for (i = 0; i < 2; i++) {
286 ct = &irq_gc->chip_types[i];
287 ct->chip.irq_ack = irq_gc_ack_set_bit;
288 ct->chip.irq_mask = irq_gc_mask_set_bit;
289 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
290 ct->chip.irq_set_type = dwapb_irq_set_type;
291 ct->chip.irq_enable = dwapb_irq_enable;
292 ct->chip.irq_disable = dwapb_irq_disable;
293 ct->chip.irq_request_resources = dwapb_irq_reqres;
294 ct->chip.irq_release_resources = dwapb_irq_relres;
295 ct->regs.ack = GPIO_PORTA_EOI;
296 ct->regs.mask = GPIO_INTMASK;
297 ct->type = IRQ_TYPE_LEVEL_MASK;
300 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
301 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
302 irq_gc->chip_types[1].handler = handle_edge_irq;
304 if (!pp->irq_shared) {
305 irq_set_chained_handler(pp->irq, dwapb_irq_handler);
306 irq_set_handler_data(pp->irq, gpio);
309 * Request a shared IRQ since where MFD would have devices
310 * using the same irq pin
312 err = devm_request_irq(gpio->dev, pp->irq,
313 dwapb_irq_handler_mfd,
314 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
316 dev_err(gpio->dev, "error requesting IRQ\n");
317 irq_domain_remove(gpio->domain);
323 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
324 irq_create_mapping(gpio->domain, hwirq);
326 port->bgc.gc.to_irq = dwapb_gpio_to_irq;
329 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
331 struct dwapb_gpio_port *port = &gpio->ports[0];
332 struct gpio_chip *gc = &port->bgc.gc;
333 unsigned int ngpio = gc->ngpio;
334 irq_hw_number_t hwirq;
339 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
340 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
342 irq_domain_remove(gpio->domain);
346 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
347 struct dwapb_port_property *pp,
350 struct dwapb_gpio_port *port;
351 void __iomem *dat, *set, *dirout;
354 port = &gpio->ports[offs];
357 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
358 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
359 dirout = gpio->regs + GPIO_SWPORTA_DDR +
360 (pp->idx * GPIO_SWPORT_DDR_SIZE);
362 err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
365 dev_err(gpio->dev, "failed to init gpio chip for %s\n",
370 #ifdef CONFIG_OF_GPIO
371 port->bgc.gc.of_node = pp->node;
373 port->bgc.gc.ngpio = pp->ngpio;
374 port->bgc.gc.base = pp->gpio_base;
377 dwapb_configure_irqs(gpio, port, pp);
379 err = gpiochip_add(&port->bgc.gc);
381 dev_err(gpio->dev, "failed to register gpiochip for %s\n",
384 port->is_registered = true;
389 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
393 for (m = 0; m < gpio->nr_ports; ++m)
394 if (gpio->ports[m].is_registered)
395 gpiochip_remove(&gpio->ports[m].bgc.gc);
398 static struct dwapb_platform_data *
399 dwapb_gpio_get_pdata_of(struct device *dev)
401 struct device_node *node, *port_np;
402 struct dwapb_platform_data *pdata;
403 struct dwapb_port_property *pp;
408 if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
409 return ERR_PTR(-ENODEV);
411 nports = of_get_child_count(node);
413 return ERR_PTR(-ENODEV);
415 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
417 return ERR_PTR(-ENOMEM);
419 pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
420 if (!pdata->properties) {
422 return ERR_PTR(-ENOMEM);
425 pdata->nports = nports;
428 for_each_child_of_node(node, port_np) {
429 pp = &pdata->properties[i++];
432 if (of_property_read_u32(port_np, "reg", &pp->idx) ||
433 pp->idx >= DWAPB_MAX_PORTS) {
434 dev_err(dev, "missing/invalid port index for %s\n",
436 kfree(pdata->properties);
438 return ERR_PTR(-EINVAL);
441 if (of_property_read_u32(port_np, "snps,nr-gpios",
443 dev_info(dev, "failed to get number of gpios for %s\n",
449 * Only port A can provide interrupts in all configurations of
453 of_property_read_bool(port_np, "interrupt-controller")) {
454 pp->irq = irq_of_parse_and_map(port_np, 0);
456 dev_warn(dev, "no irq for bank %s\n",
461 pp->irq_shared = false;
463 pp->name = port_np->full_name;
469 static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
471 if (!IS_ENABLED(CONFIG_OF_GPIO) || !pdata)
474 kfree(pdata->properties);
478 static int dwapb_gpio_probe(struct platform_device *pdev)
481 struct resource *res;
482 struct dwapb_gpio *gpio;
484 struct device *dev = &pdev->dev;
485 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
486 bool is_pdata_alloc = !pdata;
488 if (is_pdata_alloc) {
489 pdata = dwapb_gpio_get_pdata_of(dev);
491 return PTR_ERR(pdata);
494 if (!pdata->nports) {
499 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
504 gpio->dev = &pdev->dev;
505 gpio->nr_ports = pdata->nports;
507 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
508 sizeof(*gpio->ports), GFP_KERNEL);
514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
516 if (IS_ERR(gpio->regs)) {
517 err = PTR_ERR(gpio->regs);
521 for (i = 0; i < gpio->nr_ports; i++) {
522 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
526 platform_set_drvdata(pdev, gpio);
531 dwapb_gpio_unregister(gpio);
532 dwapb_irq_teardown(gpio);
536 dwapb_free_pdata_of(pdata);
541 static int dwapb_gpio_remove(struct platform_device *pdev)
543 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
545 dwapb_gpio_unregister(gpio);
546 dwapb_irq_teardown(gpio);
551 static const struct of_device_id dwapb_of_match[] = {
552 { .compatible = "snps,dw-apb-gpio" },
555 MODULE_DEVICE_TABLE(of, dwapb_of_match);
557 static struct platform_driver dwapb_gpio_driver = {
559 .name = "gpio-dwapb",
560 .owner = THIS_MODULE,
561 .of_match_table = of_match_ptr(dwapb_of_match),
563 .probe = dwapb_gpio_probe,
564 .remove = dwapb_gpio_remove,
567 module_platform_driver(dwapb_gpio_driver);
569 MODULE_LICENSE("GPL");
570 MODULE_AUTHOR("Jamie Iles");
571 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");