2 * Intel ICH6-10, Series 5 and 6 GPIO driver
4 * Copyright (C) 2010 Extreme Engineering Solutions.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/mfd/lpc_ich.h>
29 #define DRV_NAME "gpio_ich"
32 * GPIO register offsets in GPIO I/O space.
33 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
34 * LVLx registers. Logic in the read/write functions takes a register and
35 * an absolute bit number and determines the proper register offset and bit
36 * number in that register. For example, to read the value of GPIO bit 50
37 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
47 static const u8 ichx_regs[4][3] = {
48 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
49 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
50 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
51 {0x18, 0x18, 0x18}, /* BLINK offset */
54 static const u8 ichx_reglen[3] = {
58 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
59 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
62 /* Max GPIO pins the chipset can have */
65 /* chipset registers */
69 /* GPO_BLINK is available on this chipset */
72 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
75 /* USE_SEL is bogus on some chipsets, eg 3100 */
76 u32 use_sel_ignore[3];
78 /* Some chipsets have quirks, let these use their own request/get */
79 int (*request)(struct gpio_chip *chip, unsigned offset);
80 int (*get)(struct gpio_chip *chip, unsigned offset);
83 * Some chipsets don't let reading output values on GPIO_LVL register
84 * this option allows driver caching written output values
86 bool use_outlvl_cache;
91 struct platform_device *dev;
92 struct gpio_chip chip;
93 struct resource *gpio_base; /* GPIO IO base */
94 struct resource *pm_base; /* Power Mangagment IO base */
95 struct ichx_desc *desc; /* Pointer to chipset-specific description */
96 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
97 u8 use_gpio; /* Which GPIO groups are usable */
98 int outlvl_cache[3]; /* cached output values */
101 static int modparam_gpiobase = -1; /* dynamic */
102 module_param_named(gpiobase, modparam_gpiobase, int, 0444);
103 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
104 "which is the default.");
106 static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
110 int reg_nr = nr / 32;
114 spin_lock_irqsave(&ichx_priv.lock, flags);
116 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
117 data = ichx_priv.outlvl_cache[reg_nr];
119 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
120 ichx_priv.gpio_base);
126 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
127 ichx_priv.gpio_base);
128 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
129 ichx_priv.outlvl_cache[reg_nr] = data;
131 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
132 ichx_priv.gpio_base);
133 if (verify && data != tmp)
136 spin_unlock_irqrestore(&ichx_priv.lock, flags);
141 static int ichx_read_bit(int reg, unsigned nr)
145 int reg_nr = nr / 32;
148 spin_lock_irqsave(&ichx_priv.lock, flags);
150 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
151 ichx_priv.gpio_base);
153 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
154 data = ichx_priv.outlvl_cache[reg_nr] | data;
156 spin_unlock_irqrestore(&ichx_priv.lock, flags);
158 return data & (1 << bit) ? 1 : 0;
161 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
163 return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
166 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
169 * Try setting pin as an input and verify it worked since many pins
172 if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
178 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
181 /* Disable blink hardware which is available for GPIOs from 0 to 31. */
182 if (nr < 32 && ichx_priv.desc->have_blink)
183 ichx_write_bit(GPO_BLINK, nr, 0, 0);
185 /* Set GPIO output value. */
186 ichx_write_bit(GPIO_LVL, nr, val, 0);
189 * Try setting pin as an output and verify it worked since many pins
192 if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
198 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
200 return ichx_read_bit(GPIO_LVL, nr);
203 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
209 * GPI 0 - 15 need to be read from the power management registers on
210 * a ICH6/3100 bridge.
213 if (!ichx_priv.pm_base)
216 spin_lock_irqsave(&ichx_priv.lock, flags);
218 /* GPI 0 - 15 are latched, write 1 to clear*/
219 ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
220 data = ICHX_READ(0, ichx_priv.pm_base);
222 spin_unlock_irqrestore(&ichx_priv.lock, flags);
224 return (data >> 16) & (1 << nr) ? 1 : 0;
226 return ichx_gpio_get(chip, nr);
230 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
232 if (!ichx_gpio_check_available(chip, nr))
236 * Note we assume the BIOS properly set a bridge's USE value. Some
237 * chips (eg Intel 3100) have bogus USE values though, so first see if
238 * the chipset's USE value can be trusted for this specific bit.
239 * If it can't be trusted, assume that the pin can be used as a GPIO.
241 if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
244 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
247 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
250 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
251 * bridge as they are controlled by USE register bits 0 and 1. See
252 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
255 if (nr == 16 || nr == 17)
258 return ichx_gpio_request(chip, nr);
261 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
263 ichx_write_bit(GPIO_LVL, nr, val, 0);
266 static void ichx_gpiolib_setup(struct gpio_chip *chip)
268 chip->owner = THIS_MODULE;
269 chip->label = DRV_NAME;
270 chip->dev = &ichx_priv.dev->dev;
272 /* Allow chip-specific overrides of request()/get() */
273 chip->request = ichx_priv.desc->request ?
274 ichx_priv.desc->request : ichx_gpio_request;
275 chip->get = ichx_priv.desc->get ?
276 ichx_priv.desc->get : ichx_gpio_get;
278 chip->set = ichx_gpio_set;
279 chip->direction_input = ichx_gpio_direction_input;
280 chip->direction_output = ichx_gpio_direction_output;
281 chip->base = modparam_gpiobase;
282 chip->ngpio = ichx_priv.desc->ngpio;
283 chip->can_sleep = false;
284 chip->dbg_show = NULL;
287 /* ICH6-based, 631xesb-based */
288 static struct ichx_desc ich6_desc = {
289 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
290 .request = ich6_gpio_request,
291 .get = ich6_gpio_get,
293 /* GPIO 0-15 are read in the GPE0_STS PM register */
301 static struct ichx_desc i3100_desc = {
303 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
304 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
305 * Datasheet for more info.
307 .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
309 /* The 3100 needs fixups for GPIO 0 - 17 */
310 .request = ich6_gpio_request,
311 .get = ich6_gpio_get,
313 /* GPIO 0-15 are read in the GPE0_STS PM register */
319 /* ICH7 and ICH8-based */
320 static struct ichx_desc ich7_desc = {
324 .reglen = ichx_reglen,
328 static struct ichx_desc ich9_desc = {
332 .reglen = ichx_reglen,
335 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
336 static struct ichx_desc ich10_cons_desc = {
340 .reglen = ichx_reglen,
342 static struct ichx_desc ich10_corp_desc = {
346 .reglen = ichx_reglen,
349 /* Intel 5 series, 6 series, 3400 series, and C200 series */
350 static struct ichx_desc intel5_desc = {
353 .reglen = ichx_reglen,
356 static int ichx_gpio_request_regions(struct resource *res_base,
357 const char *name, u8 use_gpio)
361 if (!res_base || !res_base->start || !res_base->end)
364 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
365 if (!(use_gpio & (1 << i)))
368 res_base->start + ichx_priv.desc->regs[0][i],
369 ichx_priv.desc->reglen[i], name))
375 /* Clean up: release already requested regions, if any */
376 for (i--; i >= 0; i--) {
377 if (!(use_gpio & (1 << i)))
379 release_region(res_base->start + ichx_priv.desc->regs[0][i],
380 ichx_priv.desc->reglen[i]);
385 static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
389 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
390 if (!(use_gpio & (1 << i)))
392 release_region(res_base->start + ichx_priv.desc->regs[0][i],
393 ichx_priv.desc->reglen[i]);
397 static int ichx_gpio_probe(struct platform_device *pdev)
399 struct resource *res_base, *res_pm;
401 struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
406 ichx_priv.dev = pdev;
408 switch (ich_info->gpio_version) {
410 ichx_priv.desc = &i3100_desc;
413 ichx_priv.desc = &intel5_desc;
416 ichx_priv.desc = &ich6_desc;
419 ichx_priv.desc = &ich7_desc;
422 ichx_priv.desc = &ich9_desc;
424 case ICH_V10CORP_GPIO:
425 ichx_priv.desc = &ich10_corp_desc;
427 case ICH_V10CONS_GPIO:
428 ichx_priv.desc = &ich10_cons_desc;
434 spin_lock_init(&ichx_priv.lock);
435 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
436 ichx_priv.use_gpio = ich_info->use_gpio;
437 err = ichx_gpio_request_regions(res_base, pdev->name,
442 ichx_priv.gpio_base = res_base;
445 * If necessary, determine the I/O address of ACPI/power management
446 * registers which are needed to read the the GPE0 register for GPI pins
447 * 0 - 15 on some chipsets.
449 if (!ichx_priv.desc->uses_gpe0)
452 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
454 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
458 if (!request_region(res_pm->start, resource_size(res_pm),
460 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
464 ichx_priv.pm_base = res_pm;
467 ichx_gpiolib_setup(&ichx_priv.chip);
468 err = gpiochip_add(&ichx_priv.chip);
470 pr_err("Failed to register GPIOs\n");
474 pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
475 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
480 ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
481 if (ichx_priv.pm_base)
482 release_region(ichx_priv.pm_base->start,
483 resource_size(ichx_priv.pm_base));
487 static int ichx_gpio_remove(struct platform_device *pdev)
491 err = gpiochip_remove(&ichx_priv.chip);
493 dev_err(&pdev->dev, "%s failed, %d\n",
494 "gpiochip_remove()", err);
498 ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
499 if (ichx_priv.pm_base)
500 release_region(ichx_priv.pm_base->start,
501 resource_size(ichx_priv.pm_base));
506 static struct platform_driver ichx_gpio_driver = {
508 .owner = THIS_MODULE,
511 .probe = ichx_gpio_probe,
512 .remove = ichx_gpio_remove,
515 module_platform_driver(ichx_gpio_driver);
517 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
518 MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
519 MODULE_LICENSE("GPL");
520 MODULE_ALIAS("platform:"DRV_NAME);