2 * GPIOs on MPC512x/8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_irq.h>
18 #include <linux/gpio.h>
19 #include <linux/slab.h>
20 #include <linux/irq.h>
22 #define MPC8XXX_GPIO_PINS 32
30 #define GPIO_ICR2 0x18
32 struct mpc8xxx_gpio_chip {
33 struct of_mm_gpio_chip mm_gc;
37 * shadowed data register to be able to clear/set output pins in
38 * open drain mode safely
41 struct irq_domain *irq;
42 const void *of_dev_id_data;
45 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
47 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
50 static inline struct mpc8xxx_gpio_chip *
51 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
53 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
56 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
58 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
60 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
63 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
64 * defined as output cannot be determined by reading GPDAT register,
65 * so we use shadow data register instead. The status of input pins
66 * is determined by reading GPDAT register.
68 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
71 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
72 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
73 u32 out_mask, out_shadow;
75 out_mask = in_be32(mm->regs + GPIO_DIR);
77 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
78 out_shadow = mpc8xxx_gc->data & out_mask;
80 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
83 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
85 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
87 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
90 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
92 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
93 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
96 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
99 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
101 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
103 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
105 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
108 static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
109 unsigned long *mask, unsigned long *bits)
111 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
116 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
118 for (i = 0; i < gc->ngpio; i++) {
121 if (__test_and_clear_bit(i, mask)) {
122 if (test_bit(i, bits))
123 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
125 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
129 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
131 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
134 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
136 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
137 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
140 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
142 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
144 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
149 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
151 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
152 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
155 mpc8xxx_gpio_set(gc, gpio, val);
157 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
159 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
161 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
166 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
168 /* GPIO 28..31 are input only on MPC5121 */
172 return mpc8xxx_gpio_dir_out(gc, gpio, val);
175 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
177 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
178 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
180 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
181 return irq_create_mapping(mpc8xxx_gc->irq, offset);
186 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
188 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
189 struct irq_chip *chip = irq_desc_get_chip(desc);
190 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
193 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
195 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
198 chip->irq_eoi(&desc->irq_data);
201 static void mpc8xxx_irq_unmask(struct irq_data *d)
203 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
204 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
207 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
209 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
211 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
214 static void mpc8xxx_irq_mask(struct irq_data *d)
216 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
217 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
220 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
222 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
224 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
227 static void mpc8xxx_irq_ack(struct irq_data *d)
229 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
230 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
232 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
235 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
237 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
238 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
242 case IRQ_TYPE_EDGE_FALLING:
243 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
244 setbits32(mm->regs + GPIO_ICR,
245 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
246 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
249 case IRQ_TYPE_EDGE_BOTH:
250 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
251 clrbits32(mm->regs + GPIO_ICR,
252 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
253 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
263 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
265 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
266 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
267 unsigned long gpio = irqd_to_hwirq(d);
273 reg = mm->regs + GPIO_ICR;
274 shift = (15 - gpio) * 2;
276 reg = mm->regs + GPIO_ICR2;
277 shift = (15 - (gpio % 16)) * 2;
281 case IRQ_TYPE_EDGE_FALLING:
282 case IRQ_TYPE_LEVEL_LOW:
283 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
284 clrsetbits_be32(reg, 3 << shift, 2 << shift);
285 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
288 case IRQ_TYPE_EDGE_RISING:
289 case IRQ_TYPE_LEVEL_HIGH:
290 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
291 clrsetbits_be32(reg, 3 << shift, 1 << shift);
292 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
295 case IRQ_TYPE_EDGE_BOTH:
296 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
297 clrbits32(reg, 3 << shift);
298 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
308 static struct irq_chip mpc8xxx_irq_chip = {
309 .name = "mpc8xxx-gpio",
310 .irq_unmask = mpc8xxx_irq_unmask,
311 .irq_mask = mpc8xxx_irq_mask,
312 .irq_ack = mpc8xxx_irq_ack,
313 .irq_set_type = mpc8xxx_irq_set_type,
316 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
317 irq_hw_number_t hwirq)
319 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
321 if (mpc8xxx_gc->of_dev_id_data)
322 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
324 irq_set_chip_data(irq, h->host_data);
325 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
330 static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
331 .map = mpc8xxx_gpio_irq_map,
332 .xlate = irq_domain_xlate_twocell,
335 static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
336 { .compatible = "fsl,mpc8349-gpio", },
337 { .compatible = "fsl,mpc8572-gpio", },
338 { .compatible = "fsl,mpc8610-gpio", },
339 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
340 { .compatible = "fsl,pq3-gpio", },
341 { .compatible = "fsl,qoriq-gpio", },
345 static void __init mpc8xxx_add_controller(struct device_node *np)
347 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
348 struct of_mm_gpio_chip *mm_gc;
349 struct gpio_chip *gc;
350 const struct of_device_id *id;
354 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
360 spin_lock_init(&mpc8xxx_gc->lock);
362 mm_gc = &mpc8xxx_gc->mm_gc;
365 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
366 gc->ngpio = MPC8XXX_GPIO_PINS;
367 gc->direction_input = mpc8xxx_gpio_dir_in;
368 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
369 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
370 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
371 mpc8572_gpio_get : mpc8xxx_gpio_get;
372 gc->set = mpc8xxx_gpio_set;
373 gc->set_multiple = mpc8xxx_gpio_set_multiple;
374 gc->to_irq = mpc8xxx_gpio_to_irq;
376 ret = of_mm_gpiochip_add(np, mm_gc);
380 hwirq = irq_of_parse_and_map(np, 0);
384 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
385 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
386 if (!mpc8xxx_gc->irq)
389 id = of_match_node(mpc8xxx_gpio_ids, np);
391 mpc8xxx_gc->of_dev_id_data = id->data;
393 /* ack and mask all irqs */
394 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
395 out_be32(mm_gc->regs + GPIO_IMR, 0);
397 irq_set_handler_data(hwirq, mpc8xxx_gc);
398 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
404 pr_err("%s: registration failed with status %d\n",
411 static int __init mpc8xxx_add_gpiochips(void)
413 struct device_node *np;
415 for_each_matching_node(np, mpc8xxx_gpio_ids)
416 mpc8xxx_add_controller(np);
420 arch_initcall(mpc8xxx_add_gpiochips);