2 * GPIOs on MPC512x/8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/gpio.h>
20 #include <linux/slab.h>
21 #include <linux/irq.h>
23 #define MPC8XXX_GPIO_PINS 32
31 #define GPIO_ICR2 0x18
33 struct mpc8xxx_gpio_chip {
34 struct of_mm_gpio_chip mm_gc;
38 * shadowed data register to be able to clear/set output pins in
39 * open drain mode safely
42 struct irq_domain *irq;
44 const void *of_dev_id_data;
47 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
49 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
52 static inline struct mpc8xxx_gpio_chip *
53 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
55 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
58 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
60 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
62 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
65 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
66 * defined as output cannot be determined by reading GPDAT register,
67 * so we use shadow data register instead. The status of input pins
68 * is determined by reading GPDAT register.
70 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
73 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
74 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
75 u32 out_mask, out_shadow;
77 out_mask = in_be32(mm->regs + GPIO_DIR);
79 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
80 out_shadow = mpc8xxx_gc->data & out_mask;
82 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
85 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
89 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
92 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
94 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
95 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
98 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
101 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
103 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
105 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
107 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
110 static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
111 unsigned long *mask, unsigned long *bits)
113 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
114 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
118 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
120 for (i = 0; i < gc->ngpio; i++) {
123 if (__test_and_clear_bit(i, mask)) {
124 if (test_bit(i, bits))
125 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
127 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
131 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
133 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
136 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
138 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
139 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
142 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
144 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
146 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
151 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
153 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
157 mpc8xxx_gpio_set(gc, gpio, val);
159 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
161 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
163 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
168 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
170 /* GPIO 28..31 are input only on MPC5121 */
174 return mpc8xxx_gpio_dir_out(gc, gpio, val);
177 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
179 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
180 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
182 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
183 return irq_create_mapping(mpc8xxx_gc->irq, offset);
188 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
190 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
191 struct irq_chip *chip = irq_desc_get_chip(desc);
192 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
195 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
197 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
200 chip->irq_eoi(&desc->irq_data);
203 static void mpc8xxx_irq_unmask(struct irq_data *d)
205 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
206 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
209 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
211 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
213 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
216 static void mpc8xxx_irq_mask(struct irq_data *d)
218 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
219 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
222 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
224 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
226 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
229 static void mpc8xxx_irq_ack(struct irq_data *d)
231 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
232 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
234 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
237 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
239 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
240 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
244 case IRQ_TYPE_EDGE_FALLING:
245 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
246 setbits32(mm->regs + GPIO_ICR,
247 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
248 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
251 case IRQ_TYPE_EDGE_BOTH:
252 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
253 clrbits32(mm->regs + GPIO_ICR,
254 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
255 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
265 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
267 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
268 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
269 unsigned long gpio = irqd_to_hwirq(d);
275 reg = mm->regs + GPIO_ICR;
276 shift = (15 - gpio) * 2;
278 reg = mm->regs + GPIO_ICR2;
279 shift = (15 - (gpio % 16)) * 2;
283 case IRQ_TYPE_EDGE_FALLING:
284 case IRQ_TYPE_LEVEL_LOW:
285 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
286 clrsetbits_be32(reg, 3 << shift, 2 << shift);
287 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
290 case IRQ_TYPE_EDGE_RISING:
291 case IRQ_TYPE_LEVEL_HIGH:
292 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
293 clrsetbits_be32(reg, 3 << shift, 1 << shift);
294 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
297 case IRQ_TYPE_EDGE_BOTH:
298 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
299 clrbits32(reg, 3 << shift);
300 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
310 static struct irq_chip mpc8xxx_irq_chip = {
311 .name = "mpc8xxx-gpio",
312 .irq_unmask = mpc8xxx_irq_unmask,
313 .irq_mask = mpc8xxx_irq_mask,
314 .irq_ack = mpc8xxx_irq_ack,
315 .irq_set_type = mpc8xxx_irq_set_type,
318 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
319 irq_hw_number_t hwirq)
321 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
323 if (mpc8xxx_gc->of_dev_id_data)
324 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
326 irq_set_chip_data(irq, h->host_data);
327 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
332 static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
333 .map = mpc8xxx_gpio_irq_map,
334 .xlate = irq_domain_xlate_twocell,
337 static struct of_device_id mpc8xxx_gpio_ids[] = {
338 { .compatible = "fsl,mpc8349-gpio", },
339 { .compatible = "fsl,mpc8572-gpio", },
340 { .compatible = "fsl,mpc8610-gpio", },
341 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
342 { .compatible = "fsl,pq3-gpio", },
343 { .compatible = "fsl,qoriq-gpio", },
347 static int mpc8xxx_probe(struct platform_device *pdev)
349 struct device_node *np = pdev->dev.of_node;
350 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
351 struct of_mm_gpio_chip *mm_gc;
352 struct gpio_chip *gc;
353 const struct of_device_id *id;
356 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
360 platform_set_drvdata(pdev, mpc8xxx_gc);
362 spin_lock_init(&mpc8xxx_gc->lock);
364 mm_gc = &mpc8xxx_gc->mm_gc;
367 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
368 gc->ngpio = MPC8XXX_GPIO_PINS;
369 gc->direction_input = mpc8xxx_gpio_dir_in;
370 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
371 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
372 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
373 mpc8572_gpio_get : mpc8xxx_gpio_get;
374 gc->set = mpc8xxx_gpio_set;
375 gc->set_multiple = mpc8xxx_gpio_set_multiple;
376 gc->to_irq = mpc8xxx_gpio_to_irq;
378 ret = of_mm_gpiochip_add(np, mm_gc);
382 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
383 if (mpc8xxx_gc->irqn == NO_IRQ)
386 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
387 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
388 if (!mpc8xxx_gc->irq)
391 id = of_match_node(mpc8xxx_gpio_ids, np);
393 mpc8xxx_gc->of_dev_id_data = id->data;
395 /* ack and mask all irqs */
396 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
397 out_be32(mm_gc->regs + GPIO_IMR, 0);
399 irq_set_handler_data(mpc8xxx_gc->irqn, mpc8xxx_gc);
400 irq_set_chained_handler(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade);
405 static int mpc8xxx_remove(struct platform_device *pdev)
407 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
409 if (mpc8xxx_gc->irq) {
410 irq_set_handler_data(mpc8xxx_gc->irqn, NULL);
411 irq_set_chained_handler(mpc8xxx_gc->irqn, NULL);
412 irq_domain_remove(mpc8xxx_gc->irq);
415 of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
420 static struct platform_driver mpc8xxx_plat_driver = {
421 .probe = mpc8xxx_probe,
422 .remove = mpc8xxx_remove,
424 .name = "gpio-mpc8xxx",
425 .of_match_table = mpc8xxx_gpio_ids,
429 static int __init mpc8xxx_init(void)
431 return platform_driver_register(&mpc8xxx_plat_driver);
434 arch_initcall(mpc8xxx_init);