2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/irqdomain.h>
27 #include <linux/gpio.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/basic_mmio_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/module.h>
34 #include <asm-generic/bug.h>
35 #include <asm/mach/irq.h>
37 enum mxc_gpio_hwtype {
38 IMX1_GPIO, /* runs on i.mx1 */
39 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
40 IMX31_GPIO, /* runs on all other i.mx */
43 /* device type dependent stuff */
44 struct mxc_gpio_hwdata {
58 struct mxc_gpio_port {
59 struct list_head node;
63 struct irq_domain *domain;
64 struct bgpio_chip bgc;
68 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
82 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
96 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
97 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
99 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
100 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
101 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
102 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
103 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
104 #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
105 #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
107 #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
108 #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
109 #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
110 #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
111 #define GPIO_INT_NONE 0x4
113 static struct platform_device_id mxc_gpio_devtype[] = {
116 .driver_data = IMX1_GPIO,
118 .name = "imx21-gpio",
119 .driver_data = IMX21_GPIO,
121 .name = "imx31-gpio",
122 .driver_data = IMX31_GPIO,
128 static const struct of_device_id mxc_gpio_dt_ids[] = {
129 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
130 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
131 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
136 * MX2 has one interrupt *for all* gpio ports. The list is used
137 * to save the references to all ports, so that mx2_gpio_irq_handler
138 * can walk through all interrupt status registers.
140 static LIST_HEAD(mxc_gpio_ports);
142 /* Note: This driver assumes 32 GPIOs are handled in one register */
144 static int gpio_set_irq_type(struct irq_data *d, u32 type)
146 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
147 struct mxc_gpio_port *port = gc->private;
149 u32 gpio_idx = d->hwirq;
150 u32 gpio = port->bgc.gc.base + gpio_idx;
152 void __iomem *reg = port->base;
154 port->both_edges &= ~(1 << gpio_idx);
156 case IRQ_TYPE_EDGE_RISING:
157 edge = GPIO_INT_RISE_EDGE;
159 case IRQ_TYPE_EDGE_FALLING:
160 edge = GPIO_INT_FALL_EDGE;
162 case IRQ_TYPE_EDGE_BOTH:
163 val = gpio_get_value(gpio);
165 edge = GPIO_INT_LOW_LEV;
166 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
168 edge = GPIO_INT_HIGH_LEV;
169 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
171 port->both_edges |= 1 << gpio_idx;
173 case IRQ_TYPE_LEVEL_LOW:
174 edge = GPIO_INT_LOW_LEV;
176 case IRQ_TYPE_LEVEL_HIGH:
177 edge = GPIO_INT_HIGH_LEV;
183 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* ICR1 or ICR2 */
184 bit = gpio_idx & 0xf;
185 val = readl(reg) & ~(0x3 << (bit << 1));
186 writel(val | (edge << (bit << 1)), reg);
187 writel(1 << gpio_idx, port->base + GPIO_ISR);
192 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
194 void __iomem *reg = port->base;
198 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
201 edge = (val >> (bit << 1)) & 3;
202 val &= ~(0x3 << (bit << 1));
203 if (edge == GPIO_INT_HIGH_LEV) {
204 edge = GPIO_INT_LOW_LEV;
205 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
206 } else if (edge == GPIO_INT_LOW_LEV) {
207 edge = GPIO_INT_HIGH_LEV;
208 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
210 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
214 writel(val | (edge << (bit << 1)), reg);
217 /* handle 32 interrupts in one status register */
218 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
220 while (irq_stat != 0) {
221 int irqoffset = fls(irq_stat) - 1;
223 if (port->both_edges & (1 << irqoffset))
224 mxc_flip_edge(port, irqoffset);
226 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
228 irq_stat &= ~(1 << irqoffset);
232 /* MX1 and MX3 has one interrupt *per* gpio port */
233 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
236 struct mxc_gpio_port *port = irq_get_handler_data(irq);
237 struct irq_chip *chip = irq_get_chip(irq);
239 chained_irq_enter(chip, desc);
241 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
243 mxc_gpio_irq_handler(port, irq_stat);
245 chained_irq_exit(chip, desc);
248 /* MX2 has one interrupt *for all* gpio ports */
249 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
251 u32 irq_msk, irq_stat;
252 struct mxc_gpio_port *port;
254 /* walk through all interrupt status registers */
255 list_for_each_entry(port, &mxc_gpio_ports, node) {
256 irq_msk = readl(port->base + GPIO_IMR);
260 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
262 mxc_gpio_irq_handler(port, irq_stat);
267 * Set interrupt number "irq" in the GPIO as a wake-up source.
268 * While system is running, all registered GPIO interrupts need to have
269 * wake-up enabled. When system is suspended, only selected GPIO interrupts
270 * need to have wake-up enabled.
271 * @param irq interrupt source number
272 * @param enable enable as wake-up if equal to non-zero
273 * @return This function returns 0 on success.
275 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
277 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
278 struct mxc_gpio_port *port = gc->private;
279 u32 gpio_idx = d->hwirq;
282 if (port->irq_high && (gpio_idx >= 16))
283 enable_irq_wake(port->irq_high);
285 enable_irq_wake(port->irq);
287 if (port->irq_high && (gpio_idx >= 16))
288 disable_irq_wake(port->irq_high);
290 disable_irq_wake(port->irq);
296 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
298 struct irq_chip_generic *gc;
299 struct irq_chip_type *ct;
301 gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
302 port->base, handle_level_irq);
306 ct->chip.irq_ack = irq_gc_ack_set_bit;
307 ct->chip.irq_mask = irq_gc_mask_clr_bit;
308 ct->chip.irq_unmask = irq_gc_mask_set_bit;
309 ct->chip.irq_set_type = gpio_set_irq_type;
310 ct->chip.irq_set_wake = gpio_set_wake_irq;
311 ct->regs.ack = GPIO_ISR;
312 ct->regs.mask = GPIO_IMR;
314 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
318 static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
320 const struct of_device_id *of_id =
321 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
322 enum mxc_gpio_hwtype hwtype;
325 pdev->id_entry = of_id->data;
326 hwtype = pdev->id_entry->driver_data;
328 if (mxc_gpio_hwtype) {
330 * The driver works with a reasonable presupposition,
331 * that is all gpio ports must be the same type when
332 * running on one soc.
334 BUG_ON(mxc_gpio_hwtype != hwtype);
338 if (hwtype == IMX31_GPIO)
339 mxc_gpio_hwdata = &imx31_gpio_hwdata;
341 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
343 mxc_gpio_hwtype = hwtype;
346 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
348 struct bgpio_chip *bgc = to_bgpio_chip(gc);
349 struct mxc_gpio_port *port =
350 container_of(bgc, struct mxc_gpio_port, bgc);
352 return irq_find_mapping(port->domain, offset);
355 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
357 struct device_node *np = pdev->dev.of_node;
358 struct mxc_gpio_port *port;
359 struct resource *iores;
363 mxc_gpio_get_hw(pdev);
365 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
369 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
375 if (!request_mem_region(iores->start, resource_size(iores),
381 port->base = ioremap(iores->start, resource_size(iores));
384 goto out_release_mem;
387 port->irq_high = platform_get_irq(pdev, 1);
388 port->irq = platform_get_irq(pdev, 0);
394 /* disable the interrupt and clear the status */
395 writel(0, port->base + GPIO_IMR);
396 writel(~0, port->base + GPIO_ISR);
398 if (mxc_gpio_hwtype == IMX21_GPIO) {
400 * Setup one handler for all GPIO interrupts. Actually setting
401 * the handler is needed only once, but doing it for every port
402 * is more robust and easier.
404 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
406 /* setup one handler for each entry */
407 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
408 irq_set_handler_data(port->irq, port);
409 if (port->irq_high > 0) {
410 /* setup handler for GPIO 16 to 31 */
411 irq_set_chained_handler(port->irq_high,
412 mx3_gpio_irq_handler);
413 irq_set_handler_data(port->irq_high, port);
417 err = bgpio_init(&port->bgc, &pdev->dev, 4,
418 port->base + GPIO_PSR,
419 port->base + GPIO_DR, NULL,
420 port->base + GPIO_GDIR, NULL, 0);
424 port->bgc.gc.to_irq = mxc_gpio_to_irq;
425 port->bgc.gc.base = pdev->id * 32;
426 port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
427 port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
429 err = gpiochip_add(&port->bgc.gc);
431 goto out_bgpio_remove;
433 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
436 goto out_gpiochip_remove;
439 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
440 &irq_domain_simple_ops, NULL);
443 goto out_irqdesc_free;
446 /* gpio-mxc can be a generic irq chip */
447 mxc_gpio_init_gc(port, irq_base);
449 list_add_tail(&port->node, &mxc_gpio_ports);
454 irq_free_descs(irq_base, 32);
456 WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
458 bgpio_remove(&port->bgc);
462 release_mem_region(iores->start, resource_size(iores));
465 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
469 static struct platform_driver mxc_gpio_driver = {
472 .owner = THIS_MODULE,
473 .of_match_table = mxc_gpio_dt_ids,
475 .probe = mxc_gpio_probe,
476 .id_table = mxc_gpio_devtype,
479 static int __init gpio_mxc_init(void)
481 return platform_driver_register(&mxc_gpio_driver);
483 postcore_initcall(gpio_mxc_init);
485 MODULE_AUTHOR("Freescale Semiconductor, "
486 "Daniel Mack <danielncaiaq.de>, "
487 "Juergen Beisert <kernel@pengutronix.de>");
488 MODULE_DESCRIPTION("Freescale MXC GPIO");
489 MODULE_LICENSE("GPL");