2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
34 static LIST_HEAD(omap_gpio_list);
52 struct list_head node;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
62 struct gpio_chip chip;
75 int context_loss_count;
77 bool workaround_enabled;
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
82 struct omap_gpio_reg_offs *regs;
85 #define GPIO_MOD_CTRL_BIT BIT(0)
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
90 static void omap_gpio_unmask_irq(struct irq_data *d);
92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return container_of(chip, struct gpio_bank, chip);
98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
101 void __iomem *reg = bank->base;
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
119 void __iomem *reg = bank->base;
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
130 writel_relaxed(l, reg);
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
141 l = readl_relaxed(reg);
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
152 void __iomem *reg = bank->base + bank->regs->datain;
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
159 void __iomem *reg = bank->base + bank->regs->dataout;
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
166 int l = readl_relaxed(base + reg);
173 writel_relaxed(l, base + reg);
176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
212 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
218 bool enable = !!debounce;
220 if (!bank->dbck_flag)
224 debounce = DIV_ROUND_UP(debounce, 31) - 1;
225 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
230 clk_enable(bank->dbck);
231 reg = bank->base + bank->regs->debounce;
232 writel_relaxed(debounce, reg);
234 reg = bank->base + bank->regs->debounce_en;
235 val = readl_relaxed(reg);
241 bank->dbck_enable_mask = val;
243 writel_relaxed(val, reg);
244 clk_disable(bank->dbck);
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
253 omap_gpio_dbck_enable(bank);
254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
261 * omap_clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @offset: the gpio number on this @bank
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
270 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
272 u32 gpio_bit = BIT(offset);
274 if (!bank->dbck_flag)
277 if (!(bank->dbck_enable_mask & gpio_bit))
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 writel_relaxed(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 writel_relaxed(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable(bank->dbck);
290 bank->dbck_enabled = false;
294 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
297 void __iomem *base = bank->base;
298 u32 gpio_bit = BIT(gpio);
300 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
309 bank->context.leveldetect0 =
310 readl_relaxed(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 readl_relaxed(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 readl_relaxed(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 readl_relaxed(bank->base + bank->regs->fallingdetect);
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 bank->context.wake_en =
321 readl_relaxed(bank->base + bank->regs->wkup_en);
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
339 bank->enabled_non_wakeup_gpios |= gpio_bit;
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
346 readl_relaxed(bank->base + bank->regs->leveldetect0) |
347 readl_relaxed(bank->base + bank->regs->leveldetect1);
350 #ifdef CONFIG_ARCH_OMAP1
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
355 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
357 void __iomem *reg = bank->base;
360 if (!bank->regs->irqctrl)
363 reg += bank->regs->irqctrl;
365 l = readl_relaxed(reg);
371 writel_relaxed(l, reg);
374 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
377 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
380 void __iomem *reg = bank->base;
381 void __iomem *base = bank->base;
384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 omap_set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
389 l = readl_relaxed(reg);
390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 bank->toggle_mask |= BIT(gpio);
392 if (trigger & IRQ_TYPE_EDGE_RISING)
394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
399 writel_relaxed(l, reg);
400 } else if (bank->regs->edgectrl1) {
402 reg += bank->regs->edgectrl2;
404 reg += bank->regs->edgectrl1;
407 l = readl_relaxed(reg);
408 l &= ~(3 << (gpio << 1));
409 if (trigger & IRQ_TYPE_EDGE_RISING)
410 l |= 2 << (gpio << 1);
411 if (trigger & IRQ_TYPE_EDGE_FALLING)
414 /* Enable wake-up during idle for dynamic tick */
415 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
416 bank->context.wake_en =
417 readl_relaxed(bank->base + bank->regs->wkup_en);
418 writel_relaxed(l, reg);
423 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
425 if (bank->regs->pinctrl) {
426 void __iomem *reg = bank->base + bank->regs->pinctrl;
428 /* Claim the pin for MPU */
429 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
432 if (bank->regs->ctrl && !BANK_USED(bank)) {
433 void __iomem *reg = bank->base + bank->regs->ctrl;
436 ctrl = readl_relaxed(reg);
437 /* Module is enabled, clocks are not gated */
438 ctrl &= ~GPIO_MOD_CTRL_BIT;
439 writel_relaxed(ctrl, reg);
440 bank->context.ctrl = ctrl;
444 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
446 void __iomem *base = bank->base;
448 if (bank->regs->wkup_en &&
449 !LINE_USED(bank->mod_usage, offset) &&
450 !LINE_USED(bank->irq_usage, offset)) {
451 /* Disable wake-up during idle for dynamic tick */
452 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
453 bank->context.wake_en =
454 readl_relaxed(bank->base + bank->regs->wkup_en);
457 if (bank->regs->ctrl && !BANK_USED(bank)) {
458 void __iomem *reg = bank->base + bank->regs->ctrl;
461 ctrl = readl_relaxed(reg);
462 /* Module is disabled, clocks are gated */
463 ctrl |= GPIO_MOD_CTRL_BIT;
464 writel_relaxed(ctrl, reg);
465 bank->context.ctrl = ctrl;
469 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
471 void __iomem *reg = bank->base + bank->regs->direction;
473 return readl_relaxed(reg) & BIT(offset);
476 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
478 if (!LINE_USED(bank->mod_usage, offset)) {
479 omap_enable_gpio_module(bank, offset);
480 omap_set_gpio_direction(bank, offset, 1);
482 bank->irq_usage |= BIT(offset);
485 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
487 struct gpio_bank *bank = omap_irq_data_get_bank(d);
490 unsigned offset = d->hwirq;
492 if (type & ~IRQ_TYPE_SENSE_MASK)
495 if (!bank->regs->leveldetect0 &&
496 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
499 if (!BANK_USED(bank))
500 pm_runtime_get_sync(bank->dev);
502 raw_spin_lock_irqsave(&bank->lock, flags);
503 retval = omap_set_gpio_triggering(bank, offset, type);
505 raw_spin_unlock_irqrestore(&bank->lock, flags);
508 omap_gpio_init_irq(bank, offset);
509 if (!omap_gpio_is_input(bank, offset)) {
510 raw_spin_unlock_irqrestore(&bank->lock, flags);
514 raw_spin_unlock_irqrestore(&bank->lock, flags);
516 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
517 irq_set_handler_locked(d, handle_level_irq);
518 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
519 irq_set_handler_locked(d, handle_edge_irq);
524 if (!BANK_USED(bank))
525 pm_runtime_put(bank->dev);
529 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
531 void __iomem *reg = bank->base;
533 reg += bank->regs->irqstatus;
534 writel_relaxed(gpio_mask, reg);
536 /* Workaround for clearing DSP GPIO interrupts to allow retention */
537 if (bank->regs->irqstatus2) {
538 reg = bank->base + bank->regs->irqstatus2;
539 writel_relaxed(gpio_mask, reg);
542 /* Flush posted write for the irq status to avoid spurious interrupts */
546 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
549 omap_clear_gpio_irqbank(bank, BIT(offset));
552 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
554 void __iomem *reg = bank->base;
556 u32 mask = (BIT(bank->width)) - 1;
558 reg += bank->regs->irqenable;
559 l = readl_relaxed(reg);
560 if (bank->regs->irqenable_inv)
566 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
568 void __iomem *reg = bank->base;
571 if (bank->regs->set_irqenable) {
572 reg += bank->regs->set_irqenable;
574 bank->context.irqenable1 |= gpio_mask;
576 reg += bank->regs->irqenable;
577 l = readl_relaxed(reg);
578 if (bank->regs->irqenable_inv)
582 bank->context.irqenable1 = l;
585 writel_relaxed(l, reg);
588 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
590 void __iomem *reg = bank->base;
593 if (bank->regs->clr_irqenable) {
594 reg += bank->regs->clr_irqenable;
596 bank->context.irqenable1 &= ~gpio_mask;
598 reg += bank->regs->irqenable;
599 l = readl_relaxed(reg);
600 if (bank->regs->irqenable_inv)
604 bank->context.irqenable1 = l;
607 writel_relaxed(l, reg);
610 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
611 unsigned offset, int enable)
614 omap_enable_gpio_irqbank(bank, BIT(offset));
616 omap_disable_gpio_irqbank(bank, BIT(offset));
620 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
621 * 1510 does not seem to have a wake-up register. If JTAG is connected
622 * to the target, system will wake up always on GPIO events. While
623 * system is running all registered GPIO interrupts need to have wake-up
624 * enabled. When system is suspended, only selected GPIO interrupts need
625 * to have wake-up enabled.
627 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
630 u32 gpio_bit = BIT(offset);
633 if (bank->non_wakeup_gpios & gpio_bit) {
635 "Unable to modify wakeup on non-wakeup GPIO%d\n",
640 raw_spin_lock_irqsave(&bank->lock, flags);
642 bank->context.wake_en |= gpio_bit;
644 bank->context.wake_en &= ~gpio_bit;
646 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
647 raw_spin_unlock_irqrestore(&bank->lock, flags);
652 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
653 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
655 struct gpio_bank *bank = omap_irq_data_get_bank(d);
656 unsigned offset = d->hwirq;
658 return omap_set_gpio_wakeup(bank, offset, enable);
661 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
663 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
667 * If this is the first gpio_request for the bank,
668 * enable the bank module.
670 if (!BANK_USED(bank))
671 pm_runtime_get_sync(bank->dev);
673 raw_spin_lock_irqsave(&bank->lock, flags);
674 omap_enable_gpio_module(bank, offset);
675 bank->mod_usage |= BIT(offset);
676 raw_spin_unlock_irqrestore(&bank->lock, flags);
681 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
683 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
686 raw_spin_lock_irqsave(&bank->lock, flags);
687 bank->mod_usage &= ~(BIT(offset));
688 if (!LINE_USED(bank->irq_usage, offset)) {
689 omap_set_gpio_direction(bank, offset, 1);
690 omap_clear_gpio_debounce(bank, offset);
692 omap_disable_gpio_module(bank, offset);
693 raw_spin_unlock_irqrestore(&bank->lock, flags);
696 * If this is the last gpio to be freed in the bank,
697 * disable the bank module.
699 if (!BANK_USED(bank))
700 pm_runtime_put(bank->dev);
704 * We need to unmask the GPIO bank interrupt as soon as possible to
705 * avoid missing GPIO interrupts for other lines in the bank.
706 * Then we need to mask-read-clear-unmask the triggered GPIO lines
707 * in the bank to avoid missing nested interrupts for a GPIO line.
708 * If we wait to unmask individual GPIO lines in the bank after the
709 * line's interrupt handler has been run, we may miss some nested
712 static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
714 void __iomem *isr_reg = NULL;
717 struct gpio_bank *bank;
719 struct irq_chip *irqchip = irq_desc_get_chip(desc);
720 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
721 unsigned long lock_flags;
723 chained_irq_enter(irqchip, desc);
725 bank = container_of(chip, struct gpio_bank, chip);
726 isr_reg = bank->base + bank->regs->irqstatus;
727 pm_runtime_get_sync(bank->dev);
729 if (WARN_ON(!isr_reg))
733 u32 isr_saved, level_mask = 0;
736 raw_spin_lock_irqsave(&bank->lock, lock_flags);
738 enabled = omap_get_gpio_irqbank_mask(bank);
739 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
741 if (bank->level_mask)
742 level_mask = bank->level_mask & enabled;
744 /* clear edge sensitive interrupts before handler(s) are
745 called so that we don't miss any interrupt occurred while
747 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
748 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
749 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
751 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
753 /* if there is only edge sensitive GPIO pin interrupts
754 configured, we could unmask GPIO bank interrupt immediately */
755 if (!level_mask && !unmasked) {
757 chained_irq_exit(irqchip, desc);
767 raw_spin_lock_irqsave(&bank->lock, lock_flags);
769 * Some chips can't respond to both rising and falling
770 * at the same time. If this irq was requested with
771 * both flags, we need to flip the ICR data for the IRQ
772 * to respond to the IRQ for the opposite direction.
773 * This will be indicated in the bank toggle_mask.
775 if (bank->toggle_mask & (BIT(bit)))
776 omap_toggle_gpio_edge_triggering(bank, bit);
778 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
780 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
784 /* if bank has any level sensitive GPIO pin interrupt
785 configured, we must unmask the bank interrupt only after
786 handler(s) are executed in order to avoid spurious bank
790 chained_irq_exit(irqchip, desc);
791 pm_runtime_put(bank->dev);
794 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
796 struct gpio_bank *bank = omap_irq_data_get_bank(d);
798 unsigned offset = d->hwirq;
800 if (!BANK_USED(bank))
801 pm_runtime_get_sync(bank->dev);
803 raw_spin_lock_irqsave(&bank->lock, flags);
805 if (!LINE_USED(bank->mod_usage, offset))
806 omap_set_gpio_direction(bank, offset, 1);
807 else if (!omap_gpio_is_input(bank, offset))
809 omap_enable_gpio_module(bank, offset);
810 bank->irq_usage |= BIT(offset);
812 raw_spin_unlock_irqrestore(&bank->lock, flags);
813 omap_gpio_unmask_irq(d);
817 raw_spin_unlock_irqrestore(&bank->lock, flags);
818 if (!BANK_USED(bank))
819 pm_runtime_put(bank->dev);
823 static void omap_gpio_irq_shutdown(struct irq_data *d)
825 struct gpio_bank *bank = omap_irq_data_get_bank(d);
827 unsigned offset = d->hwirq;
829 raw_spin_lock_irqsave(&bank->lock, flags);
830 bank->irq_usage &= ~(BIT(offset));
831 omap_set_gpio_irqenable(bank, offset, 0);
832 omap_clear_gpio_irqstatus(bank, offset);
833 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
834 if (!LINE_USED(bank->mod_usage, offset))
835 omap_clear_gpio_debounce(bank, offset);
836 omap_disable_gpio_module(bank, offset);
837 raw_spin_unlock_irqrestore(&bank->lock, flags);
840 * If this is the last IRQ to be freed in the bank,
841 * disable the bank module.
843 if (!BANK_USED(bank))
844 pm_runtime_put(bank->dev);
847 static void omap_gpio_ack_irq(struct irq_data *d)
849 struct gpio_bank *bank = omap_irq_data_get_bank(d);
850 unsigned offset = d->hwirq;
852 omap_clear_gpio_irqstatus(bank, offset);
855 static void omap_gpio_mask_irq(struct irq_data *d)
857 struct gpio_bank *bank = omap_irq_data_get_bank(d);
858 unsigned offset = d->hwirq;
861 raw_spin_lock_irqsave(&bank->lock, flags);
862 omap_set_gpio_irqenable(bank, offset, 0);
863 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
864 raw_spin_unlock_irqrestore(&bank->lock, flags);
867 static void omap_gpio_unmask_irq(struct irq_data *d)
869 struct gpio_bank *bank = omap_irq_data_get_bank(d);
870 unsigned offset = d->hwirq;
871 u32 trigger = irqd_get_trigger_type(d);
874 raw_spin_lock_irqsave(&bank->lock, flags);
876 omap_set_gpio_triggering(bank, offset, trigger);
878 /* For level-triggered GPIOs, the clearing must be done after
879 * the HW source is cleared, thus after the handler has run */
880 if (bank->level_mask & BIT(offset)) {
881 omap_set_gpio_irqenable(bank, offset, 0);
882 omap_clear_gpio_irqstatus(bank, offset);
885 omap_set_gpio_irqenable(bank, offset, 1);
886 raw_spin_unlock_irqrestore(&bank->lock, flags);
889 /*---------------------------------------------------------------------*/
891 static int omap_mpuio_suspend_noirq(struct device *dev)
893 struct platform_device *pdev = to_platform_device(dev);
894 struct gpio_bank *bank = platform_get_drvdata(pdev);
895 void __iomem *mask_reg = bank->base +
896 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
899 raw_spin_lock_irqsave(&bank->lock, flags);
900 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
901 raw_spin_unlock_irqrestore(&bank->lock, flags);
906 static int omap_mpuio_resume_noirq(struct device *dev)
908 struct platform_device *pdev = to_platform_device(dev);
909 struct gpio_bank *bank = platform_get_drvdata(pdev);
910 void __iomem *mask_reg = bank->base +
911 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
914 raw_spin_lock_irqsave(&bank->lock, flags);
915 writel_relaxed(bank->context.wake_en, mask_reg);
916 raw_spin_unlock_irqrestore(&bank->lock, flags);
921 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
922 .suspend_noirq = omap_mpuio_suspend_noirq,
923 .resume_noirq = omap_mpuio_resume_noirq,
926 /* use platform_driver for this. */
927 static struct platform_driver omap_mpuio_driver = {
930 .pm = &omap_mpuio_dev_pm_ops,
934 static struct platform_device omap_mpuio_device = {
938 .driver = &omap_mpuio_driver.driver,
940 /* could list the /proc/iomem resources */
943 static inline void omap_mpuio_init(struct gpio_bank *bank)
945 platform_set_drvdata(&omap_mpuio_device, bank);
947 if (platform_driver_register(&omap_mpuio_driver) == 0)
948 (void) platform_device_register(&omap_mpuio_device);
951 /*---------------------------------------------------------------------*/
953 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
955 struct gpio_bank *bank;
960 bank = container_of(chip, struct gpio_bank, chip);
961 reg = bank->base + bank->regs->direction;
962 raw_spin_lock_irqsave(&bank->lock, flags);
963 dir = !!(readl_relaxed(reg) & BIT(offset));
964 raw_spin_unlock_irqrestore(&bank->lock, flags);
968 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
970 struct gpio_bank *bank;
973 bank = container_of(chip, struct gpio_bank, chip);
974 raw_spin_lock_irqsave(&bank->lock, flags);
975 omap_set_gpio_direction(bank, offset, 1);
976 raw_spin_unlock_irqrestore(&bank->lock, flags);
980 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
982 struct gpio_bank *bank;
984 bank = container_of(chip, struct gpio_bank, chip);
986 if (omap_gpio_is_input(bank, offset))
987 return omap_get_gpio_datain(bank, offset);
989 return omap_get_gpio_dataout(bank, offset);
992 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
994 struct gpio_bank *bank;
997 bank = container_of(chip, struct gpio_bank, chip);
998 raw_spin_lock_irqsave(&bank->lock, flags);
999 bank->set_dataout(bank, offset, value);
1000 omap_set_gpio_direction(bank, offset, 0);
1001 raw_spin_unlock_irqrestore(&bank->lock, flags);
1005 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1008 struct gpio_bank *bank;
1009 unsigned long flags;
1011 bank = container_of(chip, struct gpio_bank, chip);
1013 raw_spin_lock_irqsave(&bank->lock, flags);
1014 omap2_set_gpio_debounce(bank, offset, debounce);
1015 raw_spin_unlock_irqrestore(&bank->lock, flags);
1020 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1022 struct gpio_bank *bank;
1023 unsigned long flags;
1025 bank = container_of(chip, struct gpio_bank, chip);
1026 raw_spin_lock_irqsave(&bank->lock, flags);
1027 bank->set_dataout(bank, offset, value);
1028 raw_spin_unlock_irqrestore(&bank->lock, flags);
1031 /*---------------------------------------------------------------------*/
1033 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1038 if (called || bank->regs->revision == USHRT_MAX)
1041 rev = readw_relaxed(bank->base + bank->regs->revision);
1042 pr_info("OMAP GPIO hardware version %d.%d\n",
1043 (rev >> 4) & 0x0f, rev & 0x0f);
1048 static void omap_gpio_mod_init(struct gpio_bank *bank)
1050 void __iomem *base = bank->base;
1053 if (bank->width == 16)
1056 if (bank->is_mpuio) {
1057 writel_relaxed(l, bank->base + bank->regs->irqenable);
1061 omap_gpio_rmw(base, bank->regs->irqenable, l,
1062 bank->regs->irqenable_inv);
1063 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1064 !bank->regs->irqenable_inv);
1065 if (bank->regs->debounce_en)
1066 writel_relaxed(0, base + bank->regs->debounce_en);
1068 /* Save OE default value (0xffffffff) in the context */
1069 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1070 /* Initialize interface clk ungated, module enabled */
1071 if (bank->regs->ctrl)
1072 writel_relaxed(0, base + bank->regs->ctrl);
1075 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1082 * REVISIT eventually switch from OMAP-specific gpio structs
1083 * over to the generic ones
1085 bank->chip.request = omap_gpio_request;
1086 bank->chip.free = omap_gpio_free;
1087 bank->chip.get_direction = omap_gpio_get_direction;
1088 bank->chip.direction_input = omap_gpio_input;
1089 bank->chip.get = omap_gpio_get;
1090 bank->chip.direction_output = omap_gpio_output;
1091 bank->chip.set_debounce = omap_gpio_debounce;
1092 bank->chip.set = omap_gpio_set;
1093 if (bank->is_mpuio) {
1094 bank->chip.label = "mpuio";
1095 if (bank->regs->wkup_en)
1096 bank->chip.dev = &omap_mpuio_device.dev;
1097 bank->chip.base = OMAP_MPUIO(0);
1099 bank->chip.label = "gpio";
1100 bank->chip.base = gpio;
1101 gpio += bank->width;
1103 bank->chip.ngpio = bank->width;
1105 ret = gpiochip_add(&bank->chip);
1107 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1111 #ifdef CONFIG_ARCH_OMAP1
1113 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1114 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1116 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1118 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1123 /* MPUIO is a bit different, reading IRQ status clears it */
1124 if (bank->is_mpuio) {
1125 irqc->irq_ack = dummy_irq_chip.irq_ack;
1126 irqc->irq_mask = irq_gc_mask_set_bit;
1127 irqc->irq_unmask = irq_gc_mask_clr_bit;
1128 if (!bank->regs->wkup_en)
1129 irqc->irq_set_wake = NULL;
1132 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1133 irq_base, omap_gpio_irq_handler,
1137 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1138 gpiochip_remove(&bank->chip);
1142 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1143 bank->irq, omap_gpio_irq_handler);
1148 static const struct of_device_id omap_gpio_match[];
1150 static int omap_gpio_probe(struct platform_device *pdev)
1152 struct device *dev = &pdev->dev;
1153 struct device_node *node = dev->of_node;
1154 const struct of_device_id *match;
1155 const struct omap_gpio_platform_data *pdata;
1156 struct resource *res;
1157 struct gpio_bank *bank;
1158 struct irq_chip *irqc;
1161 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1163 pdata = match ? match->data : dev_get_platdata(dev);
1167 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1169 dev_err(dev, "Memory alloc failed\n");
1173 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1177 irqc->irq_startup = omap_gpio_irq_startup,
1178 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1179 irqc->irq_ack = omap_gpio_ack_irq,
1180 irqc->irq_mask = omap_gpio_mask_irq,
1181 irqc->irq_unmask = omap_gpio_unmask_irq,
1182 irqc->irq_set_type = omap_gpio_irq_type,
1183 irqc->irq_set_wake = omap_gpio_wake_enable,
1184 irqc->name = dev_name(&pdev->dev);
1186 bank->irq = platform_get_irq(pdev, 0);
1187 if (bank->irq <= 0) {
1190 if (bank->irq != -EPROBE_DEFER)
1192 "can't get irq resource ret=%d\n", bank->irq);
1197 bank->chip.dev = dev;
1198 bank->chip.owner = THIS_MODULE;
1199 bank->dbck_flag = pdata->dbck_flag;
1200 bank->stride = pdata->bank_stride;
1201 bank->width = pdata->bank_width;
1202 bank->is_mpuio = pdata->is_mpuio;
1203 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1204 bank->regs = pdata->regs;
1205 #ifdef CONFIG_OF_GPIO
1206 bank->chip.of_node = of_node_get(node);
1209 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1210 bank->loses_context = true;
1212 bank->loses_context = pdata->loses_context;
1214 if (bank->loses_context)
1215 bank->get_context_loss_count =
1216 pdata->get_context_loss_count;
1219 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1220 bank->set_dataout = omap_set_gpio_dataout_reg;
1222 bank->set_dataout = omap_set_gpio_dataout_mask;
1224 raw_spin_lock_init(&bank->lock);
1226 /* Static mapping, never released */
1227 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228 bank->base = devm_ioremap_resource(dev, res);
1229 if (IS_ERR(bank->base)) {
1230 return PTR_ERR(bank->base);
1233 if (bank->dbck_flag) {
1234 bank->dbck = devm_clk_get(bank->dev, "dbclk");
1235 if (IS_ERR(bank->dbck)) {
1237 "Could not get gpio dbck. Disable debounce\n");
1238 bank->dbck_flag = false;
1240 clk_prepare(bank->dbck);
1244 platform_set_drvdata(pdev, bank);
1246 pm_runtime_enable(bank->dev);
1247 pm_runtime_irq_safe(bank->dev);
1248 pm_runtime_get_sync(bank->dev);
1251 omap_mpuio_init(bank);
1253 omap_gpio_mod_init(bank);
1255 ret = omap_gpio_chip_init(bank, irqc);
1257 pm_runtime_put_sync(bank->dev);
1258 pm_runtime_disable(bank->dev);
1262 omap_gpio_show_rev(bank);
1264 pm_runtime_put(bank->dev);
1266 list_add_tail(&bank->node, &omap_gpio_list);
1271 static int omap_gpio_remove(struct platform_device *pdev)
1273 struct gpio_bank *bank = platform_get_drvdata(pdev);
1275 list_del(&bank->node);
1276 gpiochip_remove(&bank->chip);
1277 pm_runtime_disable(bank->dev);
1278 if (bank->dbck_flag)
1279 clk_unprepare(bank->dbck);
1284 #ifdef CONFIG_ARCH_OMAP2PLUS
1286 #if defined(CONFIG_PM)
1287 static void omap_gpio_restore_context(struct gpio_bank *bank);
1289 static int omap_gpio_runtime_suspend(struct device *dev)
1291 struct platform_device *pdev = to_platform_device(dev);
1292 struct gpio_bank *bank = platform_get_drvdata(pdev);
1294 unsigned long flags;
1295 u32 wake_low, wake_hi;
1297 raw_spin_lock_irqsave(&bank->lock, flags);
1300 * Only edges can generate a wakeup event to the PRCM.
1302 * Therefore, ensure any wake-up capable GPIOs have
1303 * edge-detection enabled before going idle to ensure a wakeup
1304 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1307 * The normal values will be restored upon ->runtime_resume()
1308 * by writing back the values saved in bank->context.
1310 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1312 writel_relaxed(wake_low | bank->context.fallingdetect,
1313 bank->base + bank->regs->fallingdetect);
1314 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1316 writel_relaxed(wake_hi | bank->context.risingdetect,
1317 bank->base + bank->regs->risingdetect);
1319 if (!bank->enabled_non_wakeup_gpios)
1320 goto update_gpio_context_count;
1322 if (bank->power_mode != OFF_MODE) {
1323 bank->power_mode = 0;
1324 goto update_gpio_context_count;
1327 * If going to OFF, remove triggering for all
1328 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1329 * generated. See OMAP2420 Errata item 1.101.
1331 bank->saved_datain = readl_relaxed(bank->base +
1332 bank->regs->datain);
1333 l1 = bank->context.fallingdetect;
1334 l2 = bank->context.risingdetect;
1336 l1 &= ~bank->enabled_non_wakeup_gpios;
1337 l2 &= ~bank->enabled_non_wakeup_gpios;
1339 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1340 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1342 bank->workaround_enabled = true;
1344 update_gpio_context_count:
1345 if (bank->get_context_loss_count)
1346 bank->context_loss_count =
1347 bank->get_context_loss_count(bank->dev);
1349 omap_gpio_dbck_disable(bank);
1350 raw_spin_unlock_irqrestore(&bank->lock, flags);
1355 static void omap_gpio_init_context(struct gpio_bank *p);
1357 static int omap_gpio_runtime_resume(struct device *dev)
1359 struct platform_device *pdev = to_platform_device(dev);
1360 struct gpio_bank *bank = platform_get_drvdata(pdev);
1361 u32 l = 0, gen, gen0, gen1;
1362 unsigned long flags;
1365 raw_spin_lock_irqsave(&bank->lock, flags);
1368 * On the first resume during the probe, the context has not
1369 * been initialised and so initialise it now. Also initialise
1370 * the context loss count.
1372 if (bank->loses_context && !bank->context_valid) {
1373 omap_gpio_init_context(bank);
1375 if (bank->get_context_loss_count)
1376 bank->context_loss_count =
1377 bank->get_context_loss_count(bank->dev);
1380 omap_gpio_dbck_enable(bank);
1383 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1384 * GPIOs were set to edge trigger also in order to be able to
1385 * generate a PRCM wakeup. Here we restore the
1386 * pre-runtime_suspend() values for edge triggering.
1388 writel_relaxed(bank->context.fallingdetect,
1389 bank->base + bank->regs->fallingdetect);
1390 writel_relaxed(bank->context.risingdetect,
1391 bank->base + bank->regs->risingdetect);
1393 if (bank->loses_context) {
1394 if (!bank->get_context_loss_count) {
1395 omap_gpio_restore_context(bank);
1397 c = bank->get_context_loss_count(bank->dev);
1398 if (c != bank->context_loss_count) {
1399 omap_gpio_restore_context(bank);
1401 raw_spin_unlock_irqrestore(&bank->lock, flags);
1407 if (!bank->workaround_enabled) {
1408 raw_spin_unlock_irqrestore(&bank->lock, flags);
1412 l = readl_relaxed(bank->base + bank->regs->datain);
1415 * Check if any of the non-wakeup interrupt GPIOs have changed
1416 * state. If so, generate an IRQ by software. This is
1417 * horribly racy, but it's the best we can do to work around
1420 l ^= bank->saved_datain;
1421 l &= bank->enabled_non_wakeup_gpios;
1424 * No need to generate IRQs for the rising edge for gpio IRQs
1425 * configured with falling edge only; and vice versa.
1427 gen0 = l & bank->context.fallingdetect;
1428 gen0 &= bank->saved_datain;
1430 gen1 = l & bank->context.risingdetect;
1431 gen1 &= ~(bank->saved_datain);
1433 /* FIXME: Consider GPIO IRQs with level detections properly! */
1434 gen = l & (~(bank->context.fallingdetect) &
1435 ~(bank->context.risingdetect));
1436 /* Consider all GPIO IRQs needed to be updated */
1442 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1443 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1445 if (!bank->regs->irqstatus_raw0) {
1446 writel_relaxed(old0 | gen, bank->base +
1447 bank->regs->leveldetect0);
1448 writel_relaxed(old1 | gen, bank->base +
1449 bank->regs->leveldetect1);
1452 if (bank->regs->irqstatus_raw0) {
1453 writel_relaxed(old0 | l, bank->base +
1454 bank->regs->leveldetect0);
1455 writel_relaxed(old1 | l, bank->base +
1456 bank->regs->leveldetect1);
1458 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1459 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1462 bank->workaround_enabled = false;
1463 raw_spin_unlock_irqrestore(&bank->lock, flags);
1467 #endif /* CONFIG_PM */
1469 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1470 void omap2_gpio_prepare_for_idle(int pwr_mode)
1472 struct gpio_bank *bank;
1474 list_for_each_entry(bank, &omap_gpio_list, node) {
1475 if (!BANK_USED(bank) || !bank->loses_context)
1478 bank->power_mode = pwr_mode;
1480 pm_runtime_put_sync_suspend(bank->dev);
1484 void omap2_gpio_resume_after_idle(void)
1486 struct gpio_bank *bank;
1488 list_for_each_entry(bank, &omap_gpio_list, node) {
1489 if (!BANK_USED(bank) || !bank->loses_context)
1492 pm_runtime_get_sync(bank->dev);
1497 #if defined(CONFIG_PM)
1498 static void omap_gpio_init_context(struct gpio_bank *p)
1500 struct omap_gpio_reg_offs *regs = p->regs;
1501 void __iomem *base = p->base;
1503 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1504 p->context.oe = readl_relaxed(base + regs->direction);
1505 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1506 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1507 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1508 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1509 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1510 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1511 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1513 if (regs->set_dataout && p->regs->clr_dataout)
1514 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1516 p->context.dataout = readl_relaxed(base + regs->dataout);
1518 p->context_valid = true;
1521 static void omap_gpio_restore_context(struct gpio_bank *bank)
1523 writel_relaxed(bank->context.wake_en,
1524 bank->base + bank->regs->wkup_en);
1525 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1526 writel_relaxed(bank->context.leveldetect0,
1527 bank->base + bank->regs->leveldetect0);
1528 writel_relaxed(bank->context.leveldetect1,
1529 bank->base + bank->regs->leveldetect1);
1530 writel_relaxed(bank->context.risingdetect,
1531 bank->base + bank->regs->risingdetect);
1532 writel_relaxed(bank->context.fallingdetect,
1533 bank->base + bank->regs->fallingdetect);
1534 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1535 writel_relaxed(bank->context.dataout,
1536 bank->base + bank->regs->set_dataout);
1538 writel_relaxed(bank->context.dataout,
1539 bank->base + bank->regs->dataout);
1540 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1542 if (bank->dbck_enable_mask) {
1543 writel_relaxed(bank->context.debounce, bank->base +
1544 bank->regs->debounce);
1545 writel_relaxed(bank->context.debounce_en,
1546 bank->base + bank->regs->debounce_en);
1549 writel_relaxed(bank->context.irqenable1,
1550 bank->base + bank->regs->irqenable);
1551 writel_relaxed(bank->context.irqenable2,
1552 bank->base + bank->regs->irqenable2);
1554 #endif /* CONFIG_PM */
1556 #define omap_gpio_runtime_suspend NULL
1557 #define omap_gpio_runtime_resume NULL
1558 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1561 static const struct dev_pm_ops gpio_pm_ops = {
1562 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1566 #if defined(CONFIG_OF)
1567 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1568 .revision = OMAP24XX_GPIO_REVISION,
1569 .direction = OMAP24XX_GPIO_OE,
1570 .datain = OMAP24XX_GPIO_DATAIN,
1571 .dataout = OMAP24XX_GPIO_DATAOUT,
1572 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1573 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1574 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1575 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1576 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1577 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1578 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1579 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1580 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1581 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1582 .ctrl = OMAP24XX_GPIO_CTRL,
1583 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1584 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1585 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1586 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1587 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1590 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1591 .revision = OMAP4_GPIO_REVISION,
1592 .direction = OMAP4_GPIO_OE,
1593 .datain = OMAP4_GPIO_DATAIN,
1594 .dataout = OMAP4_GPIO_DATAOUT,
1595 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1596 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1597 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1598 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1599 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1600 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1601 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1602 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1603 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1604 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1605 .ctrl = OMAP4_GPIO_CTRL,
1606 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1607 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1608 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1609 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1610 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1613 static const struct omap_gpio_platform_data omap2_pdata = {
1614 .regs = &omap2_gpio_regs,
1619 static const struct omap_gpio_platform_data omap3_pdata = {
1620 .regs = &omap2_gpio_regs,
1625 static const struct omap_gpio_platform_data omap4_pdata = {
1626 .regs = &omap4_gpio_regs,
1631 static const struct of_device_id omap_gpio_match[] = {
1633 .compatible = "ti,omap4-gpio",
1634 .data = &omap4_pdata,
1637 .compatible = "ti,omap3-gpio",
1638 .data = &omap3_pdata,
1641 .compatible = "ti,omap2-gpio",
1642 .data = &omap2_pdata,
1646 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1649 static struct platform_driver omap_gpio_driver = {
1650 .probe = omap_gpio_probe,
1651 .remove = omap_gpio_remove,
1653 .name = "omap_gpio",
1655 .of_match_table = of_match_ptr(omap_gpio_match),
1660 * gpio driver register needs to be done before
1661 * machine_init functions access gpio APIs.
1662 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1664 static int __init omap_gpio_drv_reg(void)
1666 return platform_driver_register(&omap_gpio_driver);
1668 postcore_initcall(omap_gpio_drv_reg);
1670 static void __exit omap_gpio_exit(void)
1672 platform_driver_unregister(&omap_gpio_driver);
1674 module_exit(omap_gpio_exit);
1676 MODULE_DESCRIPTION("omap gpio driver");
1677 MODULE_ALIAS("platform:gpio-omap");
1678 MODULE_LICENSE("GPL v2");