2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
31 #include <asm/mach/irq.h>
35 static LIST_HEAD(omap_gpio_list);
53 struct list_head node;
57 struct irq_domain *domain;
59 u32 enabled_non_wakeup_gpios;
60 struct gpio_regs context;
65 struct gpio_chip chip;
76 int context_loss_count;
78 bool workaround_enabled;
80 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
81 int (*get_context_loss_count)(struct device *dev);
83 struct omap_gpio_reg_offs *regs;
86 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
87 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
88 #define GPIO_MOD_CTRL_BIT BIT(0)
90 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
92 return gpio_irq - bank->irq_base + bank->chip.base;
95 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
97 void __iomem *reg = bank->base;
100 reg += bank->regs->direction;
101 l = __raw_readl(reg);
106 __raw_writel(l, reg);
107 bank->context.oe = l;
111 /* set data out value using dedicate set/clear register */
112 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
114 void __iomem *reg = bank->base;
115 u32 l = GPIO_BIT(bank, gpio);
118 reg += bank->regs->set_dataout;
119 bank->context.dataout |= l;
121 reg += bank->regs->clr_dataout;
122 bank->context.dataout &= ~l;
125 __raw_writel(l, reg);
128 /* set data out value using mask register */
129 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
131 void __iomem *reg = bank->base + bank->regs->dataout;
132 u32 gpio_bit = GPIO_BIT(bank, gpio);
135 l = __raw_readl(reg);
140 __raw_writel(l, reg);
141 bank->context.dataout = l;
144 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
146 void __iomem *reg = bank->base + bank->regs->datain;
148 return (__raw_readl(reg) & (1 << offset)) != 0;
151 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
153 void __iomem *reg = bank->base + bank->regs->dataout;
155 return (__raw_readl(reg) & (1 << offset)) != 0;
158 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
160 int l = __raw_readl(base + reg);
167 __raw_writel(l, base + reg);
170 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
172 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
173 clk_enable(bank->dbck);
174 bank->dbck_enabled = true;
176 __raw_writel(bank->dbck_enable_mask,
177 bank->base + bank->regs->debounce_en);
181 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
183 if (bank->dbck_enable_mask && bank->dbck_enabled) {
185 * Disable debounce before cutting it's clock. If debounce is
186 * enabled but the clock is not, GPIO module seems to be unable
187 * to detect events and generate interrupts at least on OMAP3.
189 __raw_writel(0, bank->base + bank->regs->debounce_en);
191 clk_disable(bank->dbck);
192 bank->dbck_enabled = false;
197 * _set_gpio_debounce - low level gpio debounce time
198 * @bank: the gpio bank we're acting upon
199 * @gpio: the gpio number on this @gpio
200 * @debounce: debounce time to use
202 * OMAP's debounce time is in 31us steps so we need
203 * to convert and round up to the closest unit.
205 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
212 if (!bank->dbck_flag)
217 else if (debounce > 7936)
220 debounce = (debounce / 0x1f) - 1;
222 l = GPIO_BIT(bank, gpio);
224 clk_enable(bank->dbck);
225 reg = bank->base + bank->regs->debounce;
226 __raw_writel(debounce, reg);
228 reg = bank->base + bank->regs->debounce_en;
229 val = __raw_readl(reg);
235 bank->dbck_enable_mask = val;
237 __raw_writel(val, reg);
238 clk_disable(bank->dbck);
240 * Enable debounce clock per module.
241 * This call is mandatory because in omap_gpio_request() when
242 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
243 * runtime callbck fails to turn on dbck because dbck_enable_mask
244 * used within _gpio_dbck_enable() is still not initialized at
245 * that point. Therefore we have to enable dbck here.
247 _gpio_dbck_enable(bank);
248 if (bank->dbck_enable_mask) {
249 bank->context.debounce = debounce;
250 bank->context.debounce_en = val;
254 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
257 void __iomem *base = bank->base;
258 u32 gpio_bit = 1 << gpio;
260 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
261 trigger & IRQ_TYPE_LEVEL_LOW);
262 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
263 trigger & IRQ_TYPE_LEVEL_HIGH);
264 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
265 trigger & IRQ_TYPE_EDGE_RISING);
266 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
267 trigger & IRQ_TYPE_EDGE_FALLING);
269 bank->context.leveldetect0 =
270 __raw_readl(bank->base + bank->regs->leveldetect0);
271 bank->context.leveldetect1 =
272 __raw_readl(bank->base + bank->regs->leveldetect1);
273 bank->context.risingdetect =
274 __raw_readl(bank->base + bank->regs->risingdetect);
275 bank->context.fallingdetect =
276 __raw_readl(bank->base + bank->regs->fallingdetect);
278 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
279 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
280 bank->context.wake_en =
281 __raw_readl(bank->base + bank->regs->wkup_en);
284 /* This part needs to be executed always for OMAP{34xx, 44xx} */
285 if (!bank->regs->irqctrl) {
286 /* On omap24xx proceed only when valid GPIO bit is set */
287 if (bank->non_wakeup_gpios) {
288 if (!(bank->non_wakeup_gpios & gpio_bit))
293 * Log the edge gpio and manually trigger the IRQ
294 * after resume if the input level changes
295 * to avoid irq lost during PER RET/OFF mode
296 * Applies for omap2 non-wakeup gpio and all omap3 gpios
298 if (trigger & IRQ_TYPE_EDGE_BOTH)
299 bank->enabled_non_wakeup_gpios |= gpio_bit;
301 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
306 __raw_readl(bank->base + bank->regs->leveldetect0) |
307 __raw_readl(bank->base + bank->regs->leveldetect1);
310 #ifdef CONFIG_ARCH_OMAP1
312 * This only applies to chips that can't do both rising and falling edge
313 * detection at once. For all other chips, this function is a noop.
315 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
317 void __iomem *reg = bank->base;
320 if (!bank->regs->irqctrl)
323 reg += bank->regs->irqctrl;
325 l = __raw_readl(reg);
331 __raw_writel(l, reg);
334 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
337 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
340 void __iomem *reg = bank->base;
341 void __iomem *base = bank->base;
344 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
345 set_gpio_trigger(bank, gpio, trigger);
346 } else if (bank->regs->irqctrl) {
347 reg += bank->regs->irqctrl;
349 l = __raw_readl(reg);
350 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
351 bank->toggle_mask |= 1 << gpio;
352 if (trigger & IRQ_TYPE_EDGE_RISING)
354 else if (trigger & IRQ_TYPE_EDGE_FALLING)
359 __raw_writel(l, reg);
360 } else if (bank->regs->edgectrl1) {
362 reg += bank->regs->edgectrl2;
364 reg += bank->regs->edgectrl1;
367 l = __raw_readl(reg);
368 l &= ~(3 << (gpio << 1));
369 if (trigger & IRQ_TYPE_EDGE_RISING)
370 l |= 2 << (gpio << 1);
371 if (trigger & IRQ_TYPE_EDGE_FALLING)
372 l |= 1 << (gpio << 1);
374 /* Enable wake-up during idle for dynamic tick */
375 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
376 bank->context.wake_en =
377 __raw_readl(bank->base + bank->regs->wkup_en);
378 __raw_writel(l, reg);
383 static int gpio_irq_type(struct irq_data *d, unsigned type)
385 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
390 #ifdef CONFIG_ARCH_OMAP1
391 if (d->irq > IH_MPUIO_BASE)
392 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
396 gpio = irq_to_gpio(bank, d->irq);
398 if (type & ~IRQ_TYPE_SENSE_MASK)
401 if (!bank->regs->leveldetect0 &&
402 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
405 spin_lock_irqsave(&bank->lock, flags);
406 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
407 spin_unlock_irqrestore(&bank->lock, flags);
409 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
410 __irq_set_handler_locked(d->irq, handle_level_irq);
411 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
412 __irq_set_handler_locked(d->irq, handle_edge_irq);
417 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
419 void __iomem *reg = bank->base;
421 reg += bank->regs->irqstatus;
422 __raw_writel(gpio_mask, reg);
424 /* Workaround for clearing DSP GPIO interrupts to allow retention */
425 if (bank->regs->irqstatus2) {
426 reg = bank->base + bank->regs->irqstatus2;
427 __raw_writel(gpio_mask, reg);
430 /* Flush posted write for the irq status to avoid spurious interrupts */
434 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
436 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
439 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
441 void __iomem *reg = bank->base;
443 u32 mask = (1 << bank->width) - 1;
445 reg += bank->regs->irqenable;
446 l = __raw_readl(reg);
447 if (bank->regs->irqenable_inv)
453 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
455 void __iomem *reg = bank->base;
458 if (bank->regs->set_irqenable) {
459 reg += bank->regs->set_irqenable;
461 bank->context.irqenable1 |= gpio_mask;
463 reg += bank->regs->irqenable;
464 l = __raw_readl(reg);
465 if (bank->regs->irqenable_inv)
469 bank->context.irqenable1 = l;
472 __raw_writel(l, reg);
475 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
477 void __iomem *reg = bank->base;
480 if (bank->regs->clr_irqenable) {
481 reg += bank->regs->clr_irqenable;
483 bank->context.irqenable1 &= ~gpio_mask;
485 reg += bank->regs->irqenable;
486 l = __raw_readl(reg);
487 if (bank->regs->irqenable_inv)
491 bank->context.irqenable1 = l;
494 __raw_writel(l, reg);
497 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
500 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
502 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
506 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
507 * 1510 does not seem to have a wake-up register. If JTAG is connected
508 * to the target, system will wake up always on GPIO events. While
509 * system is running all registered GPIO interrupts need to have wake-up
510 * enabled. When system is suspended, only selected GPIO interrupts need
511 * to have wake-up enabled.
513 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
515 u32 gpio_bit = GPIO_BIT(bank, gpio);
518 if (bank->non_wakeup_gpios & gpio_bit) {
520 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
524 spin_lock_irqsave(&bank->lock, flags);
526 bank->context.wake_en |= gpio_bit;
528 bank->context.wake_en &= ~gpio_bit;
530 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
531 spin_unlock_irqrestore(&bank->lock, flags);
536 static void _reset_gpio(struct gpio_bank *bank, int gpio)
538 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
539 _set_gpio_irqenable(bank, gpio, 0);
540 _clear_gpio_irqstatus(bank, gpio);
541 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
544 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
545 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
547 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
548 unsigned int gpio = irq_to_gpio(bank, d->irq);
550 return _set_gpio_wakeup(bank, gpio, enable);
553 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
555 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
559 * If this is the first gpio_request for the bank,
560 * enable the bank module.
562 if (!bank->mod_usage)
563 pm_runtime_get_sync(bank->dev);
565 spin_lock_irqsave(&bank->lock, flags);
566 /* Set trigger to none. You need to enable the desired trigger with
567 * request_irq() or set_irq_type().
569 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
571 if (bank->regs->pinctrl) {
572 void __iomem *reg = bank->base + bank->regs->pinctrl;
574 /* Claim the pin for MPU */
575 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
578 if (bank->regs->ctrl && !bank->mod_usage) {
579 void __iomem *reg = bank->base + bank->regs->ctrl;
582 ctrl = __raw_readl(reg);
583 /* Module is enabled, clocks are not gated */
584 ctrl &= ~GPIO_MOD_CTRL_BIT;
585 __raw_writel(ctrl, reg);
586 bank->context.ctrl = ctrl;
589 bank->mod_usage |= 1 << offset;
591 spin_unlock_irqrestore(&bank->lock, flags);
596 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
598 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
599 void __iomem *base = bank->base;
602 spin_lock_irqsave(&bank->lock, flags);
604 if (bank->regs->wkup_en) {
605 /* Disable wake-up during idle for dynamic tick */
606 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
607 bank->context.wake_en =
608 __raw_readl(bank->base + bank->regs->wkup_en);
611 bank->mod_usage &= ~(1 << offset);
613 if (bank->regs->ctrl && !bank->mod_usage) {
614 void __iomem *reg = bank->base + bank->regs->ctrl;
617 ctrl = __raw_readl(reg);
618 /* Module is disabled, clocks are gated */
619 ctrl |= GPIO_MOD_CTRL_BIT;
620 __raw_writel(ctrl, reg);
621 bank->context.ctrl = ctrl;
624 _reset_gpio(bank, bank->chip.base + offset);
625 spin_unlock_irqrestore(&bank->lock, flags);
628 * If this is the last gpio to be freed in the bank,
629 * disable the bank module.
631 if (!bank->mod_usage)
632 pm_runtime_put(bank->dev);
636 * We need to unmask the GPIO bank interrupt as soon as possible to
637 * avoid missing GPIO interrupts for other lines in the bank.
638 * Then we need to mask-read-clear-unmask the triggered GPIO lines
639 * in the bank to avoid missing nested interrupts for a GPIO line.
640 * If we wait to unmask individual GPIO lines in the bank after the
641 * line's interrupt handler has been run, we may miss some nested
644 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
646 void __iomem *isr_reg = NULL;
648 unsigned int gpio_irq, gpio_index;
649 struct gpio_bank *bank;
651 struct irq_chip *chip = irq_desc_get_chip(desc);
653 chained_irq_enter(chip, desc);
655 bank = irq_get_handler_data(irq);
656 isr_reg = bank->base + bank->regs->irqstatus;
657 pm_runtime_get_sync(bank->dev);
659 if (WARN_ON(!isr_reg))
663 u32 isr_saved, level_mask = 0;
666 enabled = _get_gpio_irqbank_mask(bank);
667 isr_saved = isr = __raw_readl(isr_reg) & enabled;
669 if (bank->level_mask)
670 level_mask = bank->level_mask & enabled;
672 /* clear edge sensitive interrupts before handler(s) are
673 called so that we don't miss any interrupt occurred while
675 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
676 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
677 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
679 /* if there is only edge sensitive GPIO pin interrupts
680 configured, we could unmask GPIO bank interrupt immediately */
681 if (!level_mask && !unmasked) {
683 chained_irq_exit(chip, desc);
689 gpio_irq = bank->irq_base;
690 for (; isr != 0; isr >>= 1, gpio_irq++) {
691 int gpio = irq_to_gpio(bank, gpio_irq);
696 gpio_index = GPIO_INDEX(bank, gpio);
699 * Some chips can't respond to both rising and falling
700 * at the same time. If this irq was requested with
701 * both flags, we need to flip the ICR data for the IRQ
702 * to respond to the IRQ for the opposite direction.
703 * This will be indicated in the bank toggle_mask.
705 if (bank->toggle_mask & (1 << gpio_index))
706 _toggle_gpio_edge_triggering(bank, gpio_index);
708 generic_handle_irq(gpio_irq);
711 /* if bank has any level sensitive GPIO pin interrupt
712 configured, we must unmask the bank interrupt only after
713 handler(s) are executed in order to avoid spurious bank
717 chained_irq_exit(chip, desc);
718 pm_runtime_put(bank->dev);
721 static void gpio_irq_shutdown(struct irq_data *d)
723 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
724 unsigned int gpio = irq_to_gpio(bank, d->irq);
727 spin_lock_irqsave(&bank->lock, flags);
728 _reset_gpio(bank, gpio);
729 spin_unlock_irqrestore(&bank->lock, flags);
732 static void gpio_ack_irq(struct irq_data *d)
734 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
735 unsigned int gpio = irq_to_gpio(bank, d->irq);
737 _clear_gpio_irqstatus(bank, gpio);
740 static void gpio_mask_irq(struct irq_data *d)
742 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
743 unsigned int gpio = irq_to_gpio(bank, d->irq);
746 spin_lock_irqsave(&bank->lock, flags);
747 _set_gpio_irqenable(bank, gpio, 0);
748 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
749 spin_unlock_irqrestore(&bank->lock, flags);
752 static void gpio_unmask_irq(struct irq_data *d)
754 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
755 unsigned int gpio = irq_to_gpio(bank, d->irq);
756 unsigned int irq_mask = GPIO_BIT(bank, gpio);
757 u32 trigger = irqd_get_trigger_type(d);
760 spin_lock_irqsave(&bank->lock, flags);
762 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
764 /* For level-triggered GPIOs, the clearing must be done after
765 * the HW source is cleared, thus after the handler has run */
766 if (bank->level_mask & irq_mask) {
767 _set_gpio_irqenable(bank, gpio, 0);
768 _clear_gpio_irqstatus(bank, gpio);
771 _set_gpio_irqenable(bank, gpio, 1);
772 spin_unlock_irqrestore(&bank->lock, flags);
775 static struct irq_chip gpio_irq_chip = {
777 .irq_shutdown = gpio_irq_shutdown,
778 .irq_ack = gpio_ack_irq,
779 .irq_mask = gpio_mask_irq,
780 .irq_unmask = gpio_unmask_irq,
781 .irq_set_type = gpio_irq_type,
782 .irq_set_wake = gpio_wake_enable,
785 /*---------------------------------------------------------------------*/
787 static int omap_mpuio_suspend_noirq(struct device *dev)
789 struct platform_device *pdev = to_platform_device(dev);
790 struct gpio_bank *bank = platform_get_drvdata(pdev);
791 void __iomem *mask_reg = bank->base +
792 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
795 spin_lock_irqsave(&bank->lock, flags);
796 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
797 spin_unlock_irqrestore(&bank->lock, flags);
802 static int omap_mpuio_resume_noirq(struct device *dev)
804 struct platform_device *pdev = to_platform_device(dev);
805 struct gpio_bank *bank = platform_get_drvdata(pdev);
806 void __iomem *mask_reg = bank->base +
807 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
810 spin_lock_irqsave(&bank->lock, flags);
811 __raw_writel(bank->context.wake_en, mask_reg);
812 spin_unlock_irqrestore(&bank->lock, flags);
817 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
818 .suspend_noirq = omap_mpuio_suspend_noirq,
819 .resume_noirq = omap_mpuio_resume_noirq,
822 /* use platform_driver for this. */
823 static struct platform_driver omap_mpuio_driver = {
826 .pm = &omap_mpuio_dev_pm_ops,
830 static struct platform_device omap_mpuio_device = {
834 .driver = &omap_mpuio_driver.driver,
836 /* could list the /proc/iomem resources */
839 static inline void mpuio_init(struct gpio_bank *bank)
841 platform_set_drvdata(&omap_mpuio_device, bank);
843 if (platform_driver_register(&omap_mpuio_driver) == 0)
844 (void) platform_device_register(&omap_mpuio_device);
847 /*---------------------------------------------------------------------*/
849 static int gpio_input(struct gpio_chip *chip, unsigned offset)
851 struct gpio_bank *bank;
854 bank = container_of(chip, struct gpio_bank, chip);
855 spin_lock_irqsave(&bank->lock, flags);
856 _set_gpio_direction(bank, offset, 1);
857 spin_unlock_irqrestore(&bank->lock, flags);
861 static int gpio_is_input(struct gpio_bank *bank, int mask)
863 void __iomem *reg = bank->base + bank->regs->direction;
865 return __raw_readl(reg) & mask;
868 static int gpio_get(struct gpio_chip *chip, unsigned offset)
870 struct gpio_bank *bank;
873 bank = container_of(chip, struct gpio_bank, chip);
874 mask = (1 << offset);
876 if (gpio_is_input(bank, mask))
877 return _get_gpio_datain(bank, offset);
879 return _get_gpio_dataout(bank, offset);
882 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
884 struct gpio_bank *bank;
887 bank = container_of(chip, struct gpio_bank, chip);
888 spin_lock_irqsave(&bank->lock, flags);
889 bank->set_dataout(bank, offset, value);
890 _set_gpio_direction(bank, offset, 0);
891 spin_unlock_irqrestore(&bank->lock, flags);
895 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
898 struct gpio_bank *bank;
901 bank = container_of(chip, struct gpio_bank, chip);
903 spin_lock_irqsave(&bank->lock, flags);
904 _set_gpio_debounce(bank, offset, debounce);
905 spin_unlock_irqrestore(&bank->lock, flags);
910 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
912 struct gpio_bank *bank;
915 bank = container_of(chip, struct gpio_bank, chip);
916 spin_lock_irqsave(&bank->lock, flags);
917 bank->set_dataout(bank, offset, value);
918 spin_unlock_irqrestore(&bank->lock, flags);
921 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
923 struct gpio_bank *bank;
925 bank = container_of(chip, struct gpio_bank, chip);
926 return bank->irq_base + offset;
929 /*---------------------------------------------------------------------*/
931 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
936 if (called || bank->regs->revision == USHRT_MAX)
939 rev = __raw_readw(bank->base + bank->regs->revision);
940 pr_info("OMAP GPIO hardware version %d.%d\n",
941 (rev >> 4) & 0x0f, rev & 0x0f);
946 /* This lock class tells lockdep that GPIO irqs are in a different
947 * category than their parents, so it won't report false recursion.
949 static struct lock_class_key gpio_lock_class;
951 static void omap_gpio_mod_init(struct gpio_bank *bank)
953 void __iomem *base = bank->base;
956 if (bank->width == 16)
959 if (bank->is_mpuio) {
960 __raw_writel(l, bank->base + bank->regs->irqenable);
964 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
965 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
966 if (bank->regs->debounce_en)
967 __raw_writel(0, base + bank->regs->debounce_en);
969 /* Save OE default value (0xffffffff) in the context */
970 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
971 /* Initialize interface clk ungated, module enabled */
972 if (bank->regs->ctrl)
973 __raw_writel(0, base + bank->regs->ctrl);
975 bank->dbck = clk_get(bank->dev, "dbclk");
976 if (IS_ERR(bank->dbck))
977 dev_err(bank->dev, "Could not get gpio dbck\n");
980 static __devinit void
981 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
984 struct irq_chip_generic *gc;
985 struct irq_chip_type *ct;
987 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
990 dev_err(bank->dev, "Memory alloc failed for gc\n");
996 /* NOTE: No ack required, reading IRQ status clears it. */
997 ct->chip.irq_mask = irq_gc_mask_set_bit;
998 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
999 ct->chip.irq_set_type = gpio_irq_type;
1001 if (bank->regs->wkup_en)
1002 ct->chip.irq_set_wake = gpio_wake_enable,
1004 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1005 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1006 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1009 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1015 * REVISIT eventually switch from OMAP-specific gpio structs
1016 * over to the generic ones
1018 bank->chip.request = omap_gpio_request;
1019 bank->chip.free = omap_gpio_free;
1020 bank->chip.direction_input = gpio_input;
1021 bank->chip.get = gpio_get;
1022 bank->chip.direction_output = gpio_output;
1023 bank->chip.set_debounce = gpio_debounce;
1024 bank->chip.set = gpio_set;
1025 bank->chip.to_irq = gpio_2irq;
1026 if (bank->is_mpuio) {
1027 bank->chip.label = "mpuio";
1028 if (bank->regs->wkup_en)
1029 bank->chip.dev = &omap_mpuio_device.dev;
1030 bank->chip.base = OMAP_MPUIO(0);
1032 bank->chip.label = "gpio";
1033 bank->chip.base = gpio;
1034 gpio += bank->width;
1036 bank->chip.ngpio = bank->width;
1038 gpiochip_add(&bank->chip);
1040 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1041 irq_set_lockdep_class(j, &gpio_lock_class);
1042 irq_set_chip_data(j, bank);
1043 if (bank->is_mpuio) {
1044 omap_mpuio_alloc_gc(bank, j, bank->width);
1046 irq_set_chip(j, &gpio_irq_chip);
1047 irq_set_handler(j, handle_simple_irq);
1048 set_irq_flags(j, IRQF_VALID);
1051 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1052 irq_set_handler_data(bank->irq, bank);
1055 static const struct of_device_id omap_gpio_match[];
1057 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1059 struct device *dev = &pdev->dev;
1060 struct device_node *node = dev->of_node;
1061 const struct of_device_id *match;
1062 struct omap_gpio_platform_data *pdata;
1063 struct resource *res;
1064 struct gpio_bank *bank;
1067 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1069 pdata = match ? match->data : dev->platform_data;
1073 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1075 dev_err(dev, "Memory alloc failed\n");
1079 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1080 if (unlikely(!res)) {
1081 dev_err(dev, "Invalid IRQ resource\n");
1085 bank->irq = res->start;
1087 bank->dbck_flag = pdata->dbck_flag;
1088 bank->stride = pdata->bank_stride;
1089 bank->width = pdata->bank_width;
1090 bank->is_mpuio = pdata->is_mpuio;
1091 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1092 bank->loses_context = pdata->loses_context;
1093 bank->regs = pdata->regs;
1094 #ifdef CONFIG_OF_GPIO
1095 bank->chip.of_node = of_node_get(node);
1098 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1099 if (bank->irq_base < 0) {
1100 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1104 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1105 0, &irq_domain_simple_ops, NULL);
1107 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1108 bank->set_dataout = _set_gpio_dataout_reg;
1110 bank->set_dataout = _set_gpio_dataout_mask;
1112 spin_lock_init(&bank->lock);
1114 /* Static mapping, never released */
1115 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1116 if (unlikely(!res)) {
1117 dev_err(dev, "Invalid mem resource\n");
1121 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1123 dev_err(dev, "Region already claimed\n");
1127 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1129 dev_err(dev, "Could not ioremap\n");
1133 platform_set_drvdata(pdev, bank);
1135 pm_runtime_enable(bank->dev);
1136 pm_runtime_irq_safe(bank->dev);
1137 pm_runtime_get_sync(bank->dev);
1142 omap_gpio_mod_init(bank);
1143 omap_gpio_chip_init(bank);
1144 omap_gpio_show_rev(bank);
1146 if (bank->loses_context)
1147 bank->get_context_loss_count = pdata->get_context_loss_count;
1149 pm_runtime_put(bank->dev);
1151 list_add_tail(&bank->node, &omap_gpio_list);
1156 #ifdef CONFIG_ARCH_OMAP2PLUS
1158 #if defined(CONFIG_PM_RUNTIME)
1159 static void omap_gpio_restore_context(struct gpio_bank *bank);
1161 static int omap_gpio_runtime_suspend(struct device *dev)
1163 struct platform_device *pdev = to_platform_device(dev);
1164 struct gpio_bank *bank = platform_get_drvdata(pdev);
1166 unsigned long flags;
1167 u32 wake_low, wake_hi;
1169 spin_lock_irqsave(&bank->lock, flags);
1172 * Only edges can generate a wakeup event to the PRCM.
1174 * Therefore, ensure any wake-up capable GPIOs have
1175 * edge-detection enabled before going idle to ensure a wakeup
1176 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1179 * The normal values will be restored upon ->runtime_resume()
1180 * by writing back the values saved in bank->context.
1182 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1184 __raw_writel(wake_low | bank->context.fallingdetect,
1185 bank->base + bank->regs->fallingdetect);
1186 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1188 __raw_writel(wake_hi | bank->context.risingdetect,
1189 bank->base + bank->regs->risingdetect);
1191 if (!bank->enabled_non_wakeup_gpios)
1192 goto update_gpio_context_count;
1194 if (bank->power_mode != OFF_MODE) {
1195 bank->power_mode = 0;
1196 goto update_gpio_context_count;
1199 * If going to OFF, remove triggering for all
1200 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1201 * generated. See OMAP2420 Errata item 1.101.
1203 bank->saved_datain = __raw_readl(bank->base +
1204 bank->regs->datain);
1205 l1 = bank->context.fallingdetect;
1206 l2 = bank->context.risingdetect;
1208 l1 &= ~bank->enabled_non_wakeup_gpios;
1209 l2 &= ~bank->enabled_non_wakeup_gpios;
1211 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1212 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1214 bank->workaround_enabled = true;
1216 update_gpio_context_count:
1217 if (bank->get_context_loss_count)
1218 bank->context_loss_count =
1219 bank->get_context_loss_count(bank->dev);
1221 _gpio_dbck_disable(bank);
1222 spin_unlock_irqrestore(&bank->lock, flags);
1227 static int omap_gpio_runtime_resume(struct device *dev)
1229 struct platform_device *pdev = to_platform_device(dev);
1230 struct gpio_bank *bank = platform_get_drvdata(pdev);
1231 int context_lost_cnt_after;
1232 u32 l = 0, gen, gen0, gen1;
1233 unsigned long flags;
1235 spin_lock_irqsave(&bank->lock, flags);
1236 _gpio_dbck_enable(bank);
1239 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1240 * GPIOs were set to edge trigger also in order to be able to
1241 * generate a PRCM wakeup. Here we restore the
1242 * pre-runtime_suspend() values for edge triggering.
1244 __raw_writel(bank->context.fallingdetect,
1245 bank->base + bank->regs->fallingdetect);
1246 __raw_writel(bank->context.risingdetect,
1247 bank->base + bank->regs->risingdetect);
1249 if (bank->get_context_loss_count) {
1250 context_lost_cnt_after =
1251 bank->get_context_loss_count(bank->dev);
1252 if (context_lost_cnt_after != bank->context_loss_count) {
1253 omap_gpio_restore_context(bank);
1255 spin_unlock_irqrestore(&bank->lock, flags);
1260 if (!bank->workaround_enabled) {
1261 spin_unlock_irqrestore(&bank->lock, flags);
1265 __raw_writel(bank->context.fallingdetect,
1266 bank->base + bank->regs->fallingdetect);
1267 __raw_writel(bank->context.risingdetect,
1268 bank->base + bank->regs->risingdetect);
1269 l = __raw_readl(bank->base + bank->regs->datain);
1272 * Check if any of the non-wakeup interrupt GPIOs have changed
1273 * state. If so, generate an IRQ by software. This is
1274 * horribly racy, but it's the best we can do to work around
1277 l ^= bank->saved_datain;
1278 l &= bank->enabled_non_wakeup_gpios;
1281 * No need to generate IRQs for the rising edge for gpio IRQs
1282 * configured with falling edge only; and vice versa.
1284 gen0 = l & bank->context.fallingdetect;
1285 gen0 &= bank->saved_datain;
1287 gen1 = l & bank->context.risingdetect;
1288 gen1 &= ~(bank->saved_datain);
1290 /* FIXME: Consider GPIO IRQs with level detections properly! */
1291 gen = l & (~(bank->context.fallingdetect) &
1292 ~(bank->context.risingdetect));
1293 /* Consider all GPIO IRQs needed to be updated */
1299 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1300 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1302 if (!bank->regs->irqstatus_raw0) {
1303 __raw_writel(old0 | gen, bank->base +
1304 bank->regs->leveldetect0);
1305 __raw_writel(old1 | gen, bank->base +
1306 bank->regs->leveldetect1);
1309 if (bank->regs->irqstatus_raw0) {
1310 __raw_writel(old0 | l, bank->base +
1311 bank->regs->leveldetect0);
1312 __raw_writel(old1 | l, bank->base +
1313 bank->regs->leveldetect1);
1315 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1316 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1319 bank->workaround_enabled = false;
1320 spin_unlock_irqrestore(&bank->lock, flags);
1324 #endif /* CONFIG_PM_RUNTIME */
1326 void omap2_gpio_prepare_for_idle(int pwr_mode)
1328 struct gpio_bank *bank;
1330 list_for_each_entry(bank, &omap_gpio_list, node) {
1331 if (!bank->mod_usage || !bank->loses_context)
1334 bank->power_mode = pwr_mode;
1336 pm_runtime_put_sync_suspend(bank->dev);
1340 void omap2_gpio_resume_after_idle(void)
1342 struct gpio_bank *bank;
1344 list_for_each_entry(bank, &omap_gpio_list, node) {
1345 if (!bank->mod_usage || !bank->loses_context)
1348 pm_runtime_get_sync(bank->dev);
1352 #if defined(CONFIG_PM_RUNTIME)
1353 static void omap_gpio_restore_context(struct gpio_bank *bank)
1355 __raw_writel(bank->context.wake_en,
1356 bank->base + bank->regs->wkup_en);
1357 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1358 __raw_writel(bank->context.leveldetect0,
1359 bank->base + bank->regs->leveldetect0);
1360 __raw_writel(bank->context.leveldetect1,
1361 bank->base + bank->regs->leveldetect1);
1362 __raw_writel(bank->context.risingdetect,
1363 bank->base + bank->regs->risingdetect);
1364 __raw_writel(bank->context.fallingdetect,
1365 bank->base + bank->regs->fallingdetect);
1366 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1367 __raw_writel(bank->context.dataout,
1368 bank->base + bank->regs->set_dataout);
1370 __raw_writel(bank->context.dataout,
1371 bank->base + bank->regs->dataout);
1372 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1374 if (bank->dbck_enable_mask) {
1375 __raw_writel(bank->context.debounce, bank->base +
1376 bank->regs->debounce);
1377 __raw_writel(bank->context.debounce_en,
1378 bank->base + bank->regs->debounce_en);
1381 __raw_writel(bank->context.irqenable1,
1382 bank->base + bank->regs->irqenable);
1383 __raw_writel(bank->context.irqenable2,
1384 bank->base + bank->regs->irqenable2);
1386 #endif /* CONFIG_PM_RUNTIME */
1388 #define omap_gpio_runtime_suspend NULL
1389 #define omap_gpio_runtime_resume NULL
1392 static const struct dev_pm_ops gpio_pm_ops = {
1393 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1397 #if defined(CONFIG_OF)
1398 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1399 .revision = OMAP24XX_GPIO_REVISION,
1400 .direction = OMAP24XX_GPIO_OE,
1401 .datain = OMAP24XX_GPIO_DATAIN,
1402 .dataout = OMAP24XX_GPIO_DATAOUT,
1403 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1404 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1405 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1406 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1407 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1408 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1409 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1410 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1411 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1412 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1413 .ctrl = OMAP24XX_GPIO_CTRL,
1414 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1415 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1416 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1417 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1418 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1421 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1422 .revision = OMAP4_GPIO_REVISION,
1423 .direction = OMAP4_GPIO_OE,
1424 .datain = OMAP4_GPIO_DATAIN,
1425 .dataout = OMAP4_GPIO_DATAOUT,
1426 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1427 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1428 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1429 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1430 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1431 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1432 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1433 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1434 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1435 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1436 .ctrl = OMAP4_GPIO_CTRL,
1437 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1438 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1439 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1440 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1441 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1444 static struct omap_gpio_platform_data omap2_pdata = {
1445 .regs = &omap2_gpio_regs,
1450 static struct omap_gpio_platform_data omap3_pdata = {
1451 .regs = &omap2_gpio_regs,
1456 static struct omap_gpio_platform_data omap4_pdata = {
1457 .regs = &omap4_gpio_regs,
1462 static const struct of_device_id omap_gpio_match[] = {
1464 .compatible = "ti,omap4-gpio",
1465 .data = &omap4_pdata,
1468 .compatible = "ti,omap3-gpio",
1469 .data = &omap3_pdata,
1472 .compatible = "ti,omap2-gpio",
1473 .data = &omap2_pdata,
1477 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1480 static struct platform_driver omap_gpio_driver = {
1481 .probe = omap_gpio_probe,
1483 .name = "omap_gpio",
1485 .of_match_table = of_match_ptr(omap_gpio_match),
1490 * gpio driver register needs to be done before
1491 * machine_init functions access gpio APIs.
1492 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1494 static int __init omap_gpio_drv_reg(void)
1496 return platform_driver_register(&omap_gpio_driver);
1498 postcore_initcall(omap_gpio_drv_reg);