2 * Copyright (C) 2008, 2009 Provigent Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
10 * Data sheet: ARM DDI 0190B, September 2000
12 #include <linux/spinlock.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/bitops.h>
20 #include <linux/workqueue.h>
21 #include <linux/gpio.h>
22 #include <linux/device.h>
23 #include <linux/amba/bus.h>
24 #include <linux/amba/pl061.h>
25 #include <linux/slab.h>
26 #include <linux/pinctrl/consumer.h>
38 #define PL061_GPIO_NR 8
41 struct pl061_context_save_regs {
58 struct pl061_context_save_regs csave_regs;
62 static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
65 * Map back to global GPIO space and request muxing, the direction
66 * parameter does not matter for this controller.
68 int gpio = chip->base + offset;
70 return pinctrl_request_gpio(gpio);
73 static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
75 int gpio = chip->base + offset;
77 pinctrl_free_gpio(gpio);
80 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
82 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
84 unsigned char gpiodir;
86 if (offset >= gc->ngpio)
89 spin_lock_irqsave(&chip->lock, flags);
90 gpiodir = readb(chip->base + GPIODIR);
91 gpiodir &= ~(1 << offset);
92 writeb(gpiodir, chip->base + GPIODIR);
93 spin_unlock_irqrestore(&chip->lock, flags);
98 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
101 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
103 unsigned char gpiodir;
105 if (offset >= gc->ngpio)
108 spin_lock_irqsave(&chip->lock, flags);
109 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
110 gpiodir = readb(chip->base + GPIODIR);
111 gpiodir |= 1 << offset;
112 writeb(gpiodir, chip->base + GPIODIR);
115 * gpio value is set again, because pl061 doesn't allow to set value of
116 * a gpio pin before configuring it in OUT mode.
118 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
119 spin_unlock_irqrestore(&chip->lock, flags);
124 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
126 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
128 return !!readb(chip->base + (1 << (offset + 2)));
131 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
133 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
135 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
138 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
142 int offset = irqd_to_hwirq(d);
144 u8 gpiois, gpioibe, gpioiev;
145 u8 bit = BIT(offset);
147 if (offset < 0 || offset >= PL061_GPIO_NR)
150 spin_lock_irqsave(&chip->lock, flags);
152 gpioiev = readb(chip->base + GPIOIEV);
153 gpiois = readb(chip->base + GPIOIS);
154 gpioibe = readb(chip->base + GPIOIBE);
156 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
158 if (trigger & IRQ_TYPE_LEVEL_HIGH)
165 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
166 /* Setting this makes GPIOEV be ignored */
170 if (trigger & IRQ_TYPE_EDGE_RISING)
172 else if (trigger & IRQ_TYPE_EDGE_FALLING)
176 writeb(gpiois, chip->base + GPIOIS);
177 writeb(gpioibe, chip->base + GPIOIBE);
178 writeb(gpioiev, chip->base + GPIOIEV);
180 spin_unlock_irqrestore(&chip->lock, flags);
185 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
187 unsigned long pending;
189 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
190 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
191 struct irq_chip *irqchip = irq_desc_get_chip(desc);
193 chained_irq_enter(irqchip, desc);
195 pending = readb(chip->base + GPIOMIS);
196 writeb(pending, chip->base + GPIOIC);
198 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
199 generic_handle_irq(irq_find_mapping(gc->irqdomain,
203 chained_irq_exit(irqchip, desc);
206 static void pl061_irq_mask(struct irq_data *d)
208 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
209 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
210 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
213 spin_lock(&chip->lock);
214 gpioie = readb(chip->base + GPIOIE) & ~mask;
215 writeb(gpioie, chip->base + GPIOIE);
216 spin_unlock(&chip->lock);
219 static void pl061_irq_unmask(struct irq_data *d)
221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
222 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
223 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
226 spin_lock(&chip->lock);
227 gpioie = readb(chip->base + GPIOIE) | mask;
228 writeb(gpioie, chip->base + GPIOIE);
229 spin_unlock(&chip->lock);
232 static struct irq_chip pl061_irqchip = {
234 .irq_mask = pl061_irq_mask,
235 .irq_unmask = pl061_irq_unmask,
236 .irq_set_type = pl061_irq_type,
239 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
241 struct device *dev = &adev->dev;
242 struct pl061_platform_data *pdata = dev_get_platdata(dev);
243 struct pl061_gpio *chip;
244 int ret, irq, i, irq_base;
246 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
251 chip->gc.base = pdata->gpio_base;
252 irq_base = pdata->irq_base;
254 dev_err(&adev->dev, "invalid IRQ base in pdata\n");
262 chip->base = devm_ioremap_resource(dev, &adev->res);
263 if (IS_ERR(chip->base))
264 return PTR_ERR(chip->base);
266 spin_lock_init(&chip->lock);
268 chip->gc.request = pl061_gpio_request;
269 chip->gc.free = pl061_gpio_free;
270 chip->gc.direction_input = pl061_direction_input;
271 chip->gc.direction_output = pl061_direction_output;
272 chip->gc.get = pl061_get_value;
273 chip->gc.set = pl061_set_value;
274 chip->gc.ngpio = PL061_GPIO_NR;
275 chip->gc.label = dev_name(dev);
277 chip->gc.owner = THIS_MODULE;
279 ret = gpiochip_add(&chip->gc);
286 writeb(0, chip->base + GPIOIE); /* disable irqs */
289 dev_err(&adev->dev, "invalid IRQ\n");
293 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
294 irq_base, handle_simple_irq,
297 dev_info(&adev->dev, "could not add irqchip\n");
300 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
301 irq, pl061_irq_handler);
303 for (i = 0; i < PL061_GPIO_NR; i++) {
305 if (pdata->directions & (1 << i))
306 pl061_direction_output(&chip->gc, i,
307 pdata->values & (1 << i));
309 pl061_direction_input(&chip->gc, i);
313 amba_set_drvdata(adev, chip);
314 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
321 static int pl061_suspend(struct device *dev)
323 struct pl061_gpio *chip = dev_get_drvdata(dev);
326 chip->csave_regs.gpio_data = 0;
327 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
328 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
329 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
330 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
331 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
333 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
334 if (chip->csave_regs.gpio_dir & (1 << offset))
335 chip->csave_regs.gpio_data |=
336 pl061_get_value(&chip->gc, offset) << offset;
342 static int pl061_resume(struct device *dev)
344 struct pl061_gpio *chip = dev_get_drvdata(dev);
347 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
348 if (chip->csave_regs.gpio_dir & (1 << offset))
349 pl061_direction_output(&chip->gc, offset,
350 chip->csave_regs.gpio_data &
353 pl061_direction_input(&chip->gc, offset);
356 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
357 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
358 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
359 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
364 static const struct dev_pm_ops pl061_dev_pm_ops = {
365 .suspend = pl061_suspend,
366 .resume = pl061_resume,
367 .freeze = pl061_suspend,
368 .restore = pl061_resume,
372 static struct amba_id pl061_ids[] = {
380 MODULE_DEVICE_TABLE(amba, pl061_ids);
382 static struct amba_driver pl061_gpio_driver = {
384 .name = "pl061_gpio",
386 .pm = &pl061_dev_pm_ops,
389 .id_table = pl061_ids,
390 .probe = pl061_probe,
393 static int __init pl061_gpio_init(void)
395 return amba_driver_register(&pl061_gpio_driver);
397 module_init(pl061_gpio_init);
399 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
400 MODULE_DESCRIPTION("PL061 GPIO driver");
401 MODULE_LICENSE("GPL");