2 * Copyright (C) 2008, 2009 Provigent Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
10 * Data sheet: ARM DDI 0190B, September 2000
12 #include <linux/spinlock.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/bitops.h>
19 #include <linux/workqueue.h>
20 #include <linux/gpio.h>
21 #include <linux/device.h>
22 #include <linux/amba/bus.h>
23 #include <linux/amba/pl061.h>
24 #include <linux/slab.h>
26 #include <asm/mach/irq.h>
37 #define PL061_GPIO_NR 8
40 struct pl061_context_save_regs {
51 /* Each of the two spinlocks protects a different set of hardware
52 * regiters and data structurs. This decouples the code of the IRQ from
53 * the GPIO code. This also makes the case of a GPIO routine call from
54 * the IRQ code simpler.
56 spinlock_t lock; /* GPIO registers */
60 struct irq_chip_generic *irq_gc;
64 struct pl061_context_save_regs csave_regs;
68 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
70 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
72 unsigned char gpiodir;
74 if (offset >= gc->ngpio)
77 spin_lock_irqsave(&chip->lock, flags);
78 gpiodir = readb(chip->base + GPIODIR);
79 gpiodir &= ~(1 << offset);
80 writeb(gpiodir, chip->base + GPIODIR);
81 spin_unlock_irqrestore(&chip->lock, flags);
86 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
89 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
91 unsigned char gpiodir;
93 if (offset >= gc->ngpio)
96 spin_lock_irqsave(&chip->lock, flags);
97 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
98 gpiodir = readb(chip->base + GPIODIR);
99 gpiodir |= 1 << offset;
100 writeb(gpiodir, chip->base + GPIODIR);
103 * gpio value is set again, because pl061 doesn't allow to set value of
104 * a gpio pin before configuring it in OUT mode.
106 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
107 spin_unlock_irqrestore(&chip->lock, flags);
112 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
114 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
116 return !!readb(chip->base + (1 << (offset + 2)));
119 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
121 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
123 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
126 static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
128 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
130 if (chip->irq_base <= 0)
133 return chip->irq_base + offset;
136 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
138 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
139 struct pl061_gpio *chip = gc->private;
140 int offset = d->irq - chip->irq_base;
142 u8 gpiois, gpioibe, gpioiev;
144 if (offset < 0 || offset >= PL061_GPIO_NR)
147 raw_spin_lock_irqsave(&gc->lock, flags);
149 gpioiev = readb(chip->base + GPIOIEV);
151 gpiois = readb(chip->base + GPIOIS);
152 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
153 gpiois |= 1 << offset;
154 if (trigger & IRQ_TYPE_LEVEL_HIGH)
155 gpioiev |= 1 << offset;
157 gpioiev &= ~(1 << offset);
159 gpiois &= ~(1 << offset);
160 writeb(gpiois, chip->base + GPIOIS);
162 gpioibe = readb(chip->base + GPIOIBE);
163 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
164 gpioibe |= 1 << offset;
166 gpioibe &= ~(1 << offset);
167 if (trigger & IRQ_TYPE_EDGE_RISING)
168 gpioiev |= 1 << offset;
169 else if (trigger & IRQ_TYPE_EDGE_FALLING)
170 gpioiev &= ~(1 << offset);
172 writeb(gpioibe, chip->base + GPIOIBE);
174 writeb(gpioiev, chip->base + GPIOIEV);
176 raw_spin_unlock_irqrestore(&gc->lock, flags);
181 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
183 unsigned long pending;
185 struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
186 struct irq_chip *irqchip = irq_desc_get_chip(desc);
188 chained_irq_enter(irqchip, desc);
190 pending = readb(chip->base + GPIOMIS);
191 writeb(pending, chip->base + GPIOIC);
193 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
194 generic_handle_irq(pl061_to_irq(&chip->gc, offset));
197 chained_irq_exit(irqchip, desc);
200 static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
202 struct irq_chip_type *ct;
204 chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
205 chip->base, handle_simple_irq);
206 chip->irq_gc->private = chip;
208 ct = chip->irq_gc->chip_types;
209 ct->chip.irq_mask = irq_gc_mask_clr_bit;
210 ct->chip.irq_unmask = irq_gc_mask_set_bit;
211 ct->chip.irq_set_type = pl061_irq_type;
212 ct->chip.irq_set_wake = irq_gc_set_wake;
213 ct->regs.mask = GPIOIE;
215 irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
216 IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
219 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
221 struct device *dev = &adev->dev;
222 struct pl061_platform_data *pdata = dev->platform_data;
223 struct pl061_gpio *chip;
226 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
231 chip->gc.base = pdata->gpio_base;
232 chip->irq_base = pdata->irq_base;
233 } else if (adev->dev.of_node) {
239 if (!devm_request_mem_region(dev, adev->res.start,
240 resource_size(&adev->res), "pl061"))
243 chip->base = devm_ioremap(dev, adev->res.start,
244 resource_size(&adev->res));
245 if (chip->base == NULL)
248 spin_lock_init(&chip->lock);
250 chip->gc.direction_input = pl061_direction_input;
251 chip->gc.direction_output = pl061_direction_output;
252 chip->gc.get = pl061_get_value;
253 chip->gc.set = pl061_set_value;
254 chip->gc.to_irq = pl061_to_irq;
255 chip->gc.ngpio = PL061_GPIO_NR;
256 chip->gc.label = dev_name(dev);
258 chip->gc.owner = THIS_MODULE;
260 ret = gpiochip_add(&chip->gc);
268 if (chip->irq_base <= 0)
271 pl061_init_gc(chip, chip->irq_base);
273 writeb(0, chip->base + GPIOIE); /* disable irqs */
278 irq_set_chained_handler(irq, pl061_irq_handler);
279 irq_set_handler_data(irq, chip);
281 for (i = 0; i < PL061_GPIO_NR; i++) {
283 if (pdata->directions & (1 << i))
284 pl061_direction_output(&chip->gc, i,
285 pdata->values & (1 << i));
287 pl061_direction_input(&chip->gc, i);
291 amba_set_drvdata(adev, chip);
297 static int pl061_suspend(struct device *dev)
299 struct pl061_gpio *chip = dev_get_drvdata(dev);
302 chip->csave_regs.gpio_data = 0;
303 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
304 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
305 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
306 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
307 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
309 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
310 if (chip->csave_regs.gpio_dir & (1 << offset))
311 chip->csave_regs.gpio_data |=
312 pl061_get_value(&chip->gc, offset) << offset;
318 static int pl061_resume(struct device *dev)
320 struct pl061_gpio *chip = dev_get_drvdata(dev);
323 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
324 if (chip->csave_regs.gpio_dir & (1 << offset))
325 pl061_direction_output(&chip->gc, offset,
326 chip->csave_regs.gpio_data &
329 pl061_direction_input(&chip->gc, offset);
332 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
333 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
334 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
335 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
340 static const struct dev_pm_ops pl061_dev_pm_ops = {
341 .suspend = pl061_suspend,
342 .resume = pl061_resume,
343 .freeze = pl061_suspend,
344 .restore = pl061_resume,
348 static struct amba_id pl061_ids[] = {
356 MODULE_DEVICE_TABLE(amba, pl061_ids);
358 static struct amba_driver pl061_gpio_driver = {
360 .name = "pl061_gpio",
362 .pm = &pl061_dev_pm_ops,
365 .id_table = pl061_ids,
366 .probe = pl061_probe,
369 static int __init pl061_gpio_init(void)
371 return amba_driver_register(&pl061_gpio_driver);
373 subsys_initcall(pl061_gpio_init);
375 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
376 MODULE_DESCRIPTION("PL061 GPIO driver");
377 MODULE_LICENSE("GPL");