1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/syscore_ops.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
31 #include <mach/iomux.h>
33 #include <asm/mach/irq.h>
35 #define MAX_PIN RK30_PIN6_PB7
37 #define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
39 struct rk30_gpio_bank {
40 struct gpio_chip chip;
43 void __iomem *regbase; /* Base of register bank */
50 static struct lock_class_key gpio_lock_class;
52 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
53 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
54 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset);
55 static int rk30_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
56 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
57 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable);
58 static int rk30_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
60 #define RK30_GPIO_BANK(ID) \
63 .label = "gpio" #ID, \
64 .direction_input = rk30_gpiolib_direction_input, \
65 .direction_output = rk30_gpiolib_direction_output, \
66 .get = rk30_gpiolib_get, \
67 .set = rk30_gpiolib_set, \
68 .pull_updown = rk30_gpiolib_pull_updown, \
69 .dbg_show = rk30_gpiolib_dbg_show, \
70 .to_irq = rk30_gpiolib_to_irq, \
71 .base = ID < 6 ? PIN_BASE + ID*NUM_GROUP : PIN_BASE + 5*NUM_GROUP, \
72 .ngpio = ID < 6 ? NUM_GROUP : 16, \
75 .irq = IRQ_GPIO##ID, \
76 .regbase = (unsigned char __iomem *) RK30_GPIO##ID##_BASE, \
79 static struct rk30_gpio_bank rk30_gpio_banks[] = {
88 static inline void rk30_gpio_bit_op(void __iomem *regbase, unsigned int offset, u32 bit, unsigned char flag)
90 u32 val = __raw_readl(regbase + offset);
95 __raw_writel(val, regbase + offset);
98 static inline struct gpio_chip *pin_to_gpio_chip(unsigned pin)
100 if (pin < PIN_BASE || pin > MAX_PIN)
105 if (likely(pin < ARRAY_SIZE(rk30_gpio_banks)))
106 return &(rk30_gpio_banks[pin].chip);
110 static inline unsigned gpio_to_bit(unsigned gpio)
113 return 1u << (gpio % NUM_GROUP);
116 static inline unsigned offset_to_bit(unsigned offset)
121 static void GPIOSetPinLevel(void __iomem *regbase, unsigned int bit, eGPIOPinLevel_t level)
123 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, 1);
124 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DR, bit, level);
127 static int GPIOGetPinLevel(void __iomem *regbase, unsigned int bit)
129 return ((__raw_readl(regbase + GPIO_EXT_PORT) & bit) != 0);
132 static void GPIOSetPinDirection(void __iomem *regbase, unsigned int bit, eGPIOPinDirection_t direction)
134 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, direction);
135 /* Enable debounce may halt cpu on wfi, disable it by default */
136 //rk30_gpio_bit_op(regbase, GPIO_DEBOUNCE, bit, 1);
139 static void GPIOEnableIntr(void __iomem *regbase, unsigned int bit)
141 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 1);
144 static void GPIODisableIntr(void __iomem *regbase, unsigned int bit)
146 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 0);
149 static void GPIOAckIntr(void __iomem *regbase, unsigned int bit)
151 rk30_gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);
154 static void GPIOSetIntrType(void __iomem *regbase, unsigned int bit, eGPIOIntType_t type)
158 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
159 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
162 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
163 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
165 case GPIOEdgelFalling:
166 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
167 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
169 case GPIOEdgelRising:
170 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
171 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
176 static int rk30_gpio_irq_set_type(struct irq_data *d, unsigned int type)
178 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
179 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
180 eGPIOIntType_t int_type;
184 case IRQ_TYPE_EDGE_RISING:
185 int_type = GPIOEdgelRising;
187 case IRQ_TYPE_EDGE_FALLING:
188 int_type = GPIOEdgelFalling;
190 case IRQ_TYPE_LEVEL_HIGH:
191 int_type = GPIOLevelHigh;
193 case IRQ_TYPE_LEVEL_LOW:
194 int_type = GPIOLevelLow;
200 spin_lock_irqsave(&bank->lock, flags);
201 //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
202 GPIOSetPinDirection(bank->regbase, bit, GPIO_IN);
203 GPIOSetIntrType(bank->regbase, bit, int_type);
204 spin_unlock_irqrestore(&bank->lock, flags);
206 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
207 __irq_set_handler_locked(d->irq, handle_level_irq);
208 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
209 __irq_set_handler_locked(d->irq, handle_edge_irq);
214 static int rk30_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
216 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
217 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
220 spin_lock_irqsave(&bank->lock, flags);
222 bank->suspend_wakeup |= bit;
224 bank->suspend_wakeup &= ~bit;
225 spin_unlock_irqrestore(&bank->lock, flags);
230 static void rk30_gpio_irq_unmask(struct irq_data *d)
232 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
233 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
236 spin_lock_irqsave(&bank->lock, flags);
237 GPIOEnableIntr(bank->regbase, bit);
238 spin_unlock_irqrestore(&bank->lock, flags);
241 static void rk30_gpio_irq_mask(struct irq_data *d)
243 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
244 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
247 spin_lock_irqsave(&bank->lock, flags);
248 GPIODisableIntr(bank->regbase, bit);
249 spin_unlock_irqrestore(&bank->lock, flags);
252 static void rk30_gpio_irq_ack(struct irq_data *d)
254 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
255 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
257 GPIOAckIntr(bank->regbase, bit);
260 static int rk30_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)
262 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
263 u32 bit = offset_to_bit(offset);
266 spin_lock_irqsave(&bank->lock, flags);
267 GPIOSetPinDirection(bank->regbase, bit, GPIO_OUT);
268 GPIOSetPinLevel(bank->regbase, bit, val);
269 spin_unlock_irqrestore(&bank->lock, flags);
273 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
275 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
278 spin_lock_irqsave(&bank->lock, flags);
279 GPIOSetPinDirection(bank->regbase, offset_to_bit(offset), GPIO_IN);
280 spin_unlock_irqrestore(&bank->lock, flags);
285 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset)
287 return GPIOGetPinLevel(to_rk30_gpio_bank(chip)->regbase, offset_to_bit(offset));
290 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
292 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
295 spin_lock_irqsave(&bank->lock, flags);
296 GPIOSetPinLevel(bank->regbase, offset_to_bit(offset), val);
297 spin_unlock_irqrestore(&bank->lock, flags);
300 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable)
302 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
305 spin_lock_irqsave(&bank->lock, flags);
307 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0H_PULL + bank->id * 8, (1<<offset) | offset_to_bit(offset-16), !enable);
309 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0L_PULL + bank->id * 8, (1<<(offset+16)) | offset_to_bit(offset), !enable);
310 spin_unlock_irqrestore(&bank->lock, flags);
315 static int rk30_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
317 return chip->base + offset;
320 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
325 for (i = 0; i < chip->ngpio; i++) {
326 unsigned pin = chip->base + i;
327 struct gpio_chip *chip = pin_to_gpioChip(pin);
328 u32 bit = pin_to_bit(pin);
329 const char *gpio_label;
334 gpio_label = gpiochip_is_requested(chip, i);
336 seq_printf(s, "[%s] GPIO%s%d: ",
337 gpio_label, chip->label, i);
341 seq_printf(s, "!chip || !bit\t");
345 GPIOSetPinDirection(chip,bit,GPIO_IN);
346 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,bit));
353 static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
355 struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
356 struct irq_chip *chip = irq_desc_get_chip(desc);
360 unsigned unmasked = 0;
362 chained_irq_enter(chip, desc);
364 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
365 ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
367 gpio_irq = gpio_to_irq(bank->chip.base);
371 /* if gpio is edge triggered, clear condition
372 * before executing the hander so that we don't
375 if (ilr & (1 << pin)) {
377 chained_irq_exit(chip, desc);
380 generic_handle_irq(gpio_irq + pin);
385 chained_irq_exit(chip, desc);
388 static struct irq_chip rk30_gpio_irq_chip = {
390 .irq_ack = rk30_gpio_irq_ack,
391 .irq_disable = rk30_gpio_irq_mask,
392 .irq_mask = rk30_gpio_irq_mask,
393 .irq_unmask = rk30_gpio_irq_unmask,
394 .irq_set_type = rk30_gpio_irq_set_type,
395 .irq_set_wake = rk30_gpio_irq_set_wake,
398 void __init rk30_gpio_init(void)
400 unsigned int i, j, pin;
401 struct rk30_gpio_bank *bank;
403 bank = rk30_gpio_banks;
406 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
407 spin_lock_init(&bank->lock);
408 bank->clk = clk_get(NULL, bank->chip.label);
409 clk_enable(bank->clk);
410 gpiochip_add(&bank->chip);
412 __raw_writel(0, bank->regbase + GPIO_INTEN);
413 for (j = 0; j < 32; j++) {
414 unsigned int irq = gpio_to_irq(pin);
417 irq_set_lockdep_class(irq, &gpio_lock_class);
418 irq_set_chip_data(irq, bank);
419 irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
420 set_irq_flags(irq, IRQF_VALID);
424 irq_set_handler_data(bank->irq, bank);
425 irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
427 printk("%s: %d gpio irqs in %d banks\n", __func__, pin - PIN_BASE, ARRAY_SIZE(rk30_gpio_banks));
431 __weak void rk30_setgpio_suspend_board(void)
435 __weak void rk30_setgpio_resume_board(void)
439 static int rk30_gpio_suspend(void)
443 rk30_setgpio_suspend_board();
445 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
446 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
448 bank->saved_wakeup = __raw_readl(bank->regbase + GPIO_INTEN);
449 __raw_writel(bank->suspend_wakeup, bank->regbase + GPIO_INTEN);
451 if (!bank->suspend_wakeup)
452 clk_disable(bank->clk);
458 static void rk30_gpio_resume(void)
462 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
463 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
466 if (!bank->suspend_wakeup)
467 clk_enable(bank->clk);
469 /* keep enable for resume irq */
470 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
471 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->regbase + GPIO_INTEN);
474 rk30_setgpio_resume_board();
477 static struct syscore_ops rk30_gpio_syscore_ops = {
478 .suspend = rk30_gpio_suspend,
479 .resume = rk30_gpio_resume,
482 static int __init rk30_gpio_sysinit(void)
484 register_syscore_ops(&rk30_gpio_syscore_ops);
488 arch_initcall(rk30_gpio_sysinit);