1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/syscore_ops.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
31 #include <mach/iomux.h>
33 #include <asm/mach/irq.h>
35 #if defined(CONFIG_ARCH_RK3066B)
36 #define MAX_PIN RK30_PIN3_PD7
37 #elif defined(CONFIG_ARCH_RK30)
38 #define MAX_PIN RK30_PIN6_PB7
39 #elif defined(CONFIG_ARCH_RK2928)
40 #define MAX_PIN RK2928_PIN3_PD7
41 #define RK30_GPIO0_PHYS RK2928_GPIO0_PHYS
42 #define RK30_GPIO0_BASE RK2928_GPIO0_BASE
43 #define RK30_GPIO0_SIZE RK2928_GPIO0_SIZE
44 #define RK30_GPIO1_PHYS RK2928_GPIO1_PHYS
45 #define RK30_GPIO1_BASE RK2928_GPIO1_BASE
46 #define RK30_GPIO1_SIZE RK2928_GPIO1_SIZE
47 #define RK30_GPIO2_PHYS RK2928_GPIO2_PHYS
48 #define RK30_GPIO2_BASE RK2928_GPIO2_BASE
49 #define RK30_GPIO2_SIZE RK2928_GPIO2_SIZE
50 #define RK30_GPIO3_PHYS RK2928_GPIO3_PHYS
51 #define RK30_GPIO3_BASE RK2928_GPIO3_BASE
52 #define RK30_GPIO3_SIZE RK2928_GPIO3_SIZE
53 #define RK30_GRF_BASE RK2928_GRF_BASE
56 #define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
58 struct rk30_gpio_bank {
59 struct gpio_chip chip;
62 void __iomem *regbase; /* Base of register bank */
69 static struct lock_class_key gpio_lock_class;
71 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
72 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
73 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset);
74 static int rk30_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
75 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
76 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable);
77 static int rk30_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
78 static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset);
80 #define RK30_GPIO_BANK(ID) \
83 .label = "gpio" #ID, \
84 .direction_input = rk30_gpiolib_direction_input, \
85 .direction_output = rk30_gpiolib_direction_output, \
86 .get = rk30_gpiolib_get, \
87 .set = rk30_gpiolib_set, \
88 .request = rk30_gpiolib_request, \
89 .pull_updown = rk30_gpiolib_pull_updown, \
90 .dbg_show = rk30_gpiolib_dbg_show, \
91 .to_irq = rk30_gpiolib_to_irq, \
92 .base = ID < 6 ? PIN_BASE + ID*NUM_GROUP : PIN_BASE + 5*NUM_GROUP, \
93 .ngpio = ID < 6 ? NUM_GROUP : 16, \
96 .irq = IRQ_GPIO##ID, \
97 .regbase = (unsigned char __iomem *) RK30_GPIO##ID##_BASE, \
100 static struct rk30_gpio_bank rk30_gpio_banks[] = {
105 #if defined(CONFIG_ARCH_RK30) && !defined(CONFIG_ARCH_RK3066B)
111 static inline void rk30_gpio_bit_op(void __iomem *regbase, unsigned int offset, u32 bit, unsigned char flag)
113 u32 val = __raw_readl(regbase + offset);
118 __raw_writel(val, regbase + offset);
121 static inline struct gpio_chip *pin_to_gpio_chip(unsigned pin)
123 if (pin < PIN_BASE || pin > MAX_PIN)
128 if (likely(pin < ARRAY_SIZE(rk30_gpio_banks)))
129 return &(rk30_gpio_banks[pin].chip);
133 static inline unsigned gpio_to_bit(unsigned gpio)
136 return 1u << (gpio % NUM_GROUP);
139 static inline unsigned offset_to_bit(unsigned offset)
144 static void GPIOSetPinLevel(void __iomem *regbase, unsigned int bit, eGPIOPinLevel_t level)
146 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, 1);
147 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DR, bit, level);
150 static int GPIOGetPinLevel(void __iomem *regbase, unsigned int bit)
152 return ((__raw_readl(regbase + GPIO_EXT_PORT) & bit) != 0);
155 static void GPIOSetPinDirection(void __iomem *regbase, unsigned int bit, eGPIOPinDirection_t direction)
157 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, direction);
158 /* Enable debounce may halt cpu on wfi, disable it by default */
159 //rk30_gpio_bit_op(regbase, GPIO_DEBOUNCE, bit, 1);
162 static void GPIOEnableIntr(void __iomem *regbase, unsigned int bit)
164 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 1);
167 static void GPIODisableIntr(void __iomem *regbase, unsigned int bit)
169 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 0);
172 static void GPIOAckIntr(void __iomem *regbase, unsigned int bit)
174 rk30_gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);
177 static void GPIOSetIntrType(void __iomem *regbase, unsigned int bit, eGPIOIntType_t type)
181 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
182 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
185 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
186 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
188 case GPIOEdgelFalling:
189 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
190 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
192 case GPIOEdgelRising:
193 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
194 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
199 static int rk30_gpio_irq_set_type(struct irq_data *d, unsigned int type)
201 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
202 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
203 eGPIOIntType_t int_type;
207 case IRQ_TYPE_EDGE_RISING:
208 int_type = GPIOEdgelRising;
210 case IRQ_TYPE_EDGE_FALLING:
211 int_type = GPIOEdgelFalling;
213 case IRQ_TYPE_LEVEL_HIGH:
214 int_type = GPIOLevelHigh;
216 case IRQ_TYPE_LEVEL_LOW:
217 int_type = GPIOLevelLow;
223 spin_lock_irqsave(&bank->lock, flags);
224 //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
225 GPIOSetPinDirection(bank->regbase, bit, GPIO_IN);
226 GPIOSetIntrType(bank->regbase, bit, int_type);
227 spin_unlock_irqrestore(&bank->lock, flags);
229 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
230 __irq_set_handler_locked(d->irq, handle_level_irq);
231 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
232 __irq_set_handler_locked(d->irq, handle_edge_irq);
237 static int rk30_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
239 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
240 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
243 spin_lock_irqsave(&bank->lock, flags);
245 bank->suspend_wakeup |= bit;
247 bank->suspend_wakeup &= ~bit;
248 spin_unlock_irqrestore(&bank->lock, flags);
253 static void rk30_gpio_irq_unmask(struct irq_data *d)
255 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
256 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
259 spin_lock_irqsave(&bank->lock, flags);
260 GPIOEnableIntr(bank->regbase, bit);
261 spin_unlock_irqrestore(&bank->lock, flags);
264 static void rk30_gpio_irq_mask(struct irq_data *d)
266 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
267 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
270 spin_lock_irqsave(&bank->lock, flags);
271 GPIODisableIntr(bank->regbase, bit);
272 spin_unlock_irqrestore(&bank->lock, flags);
275 static void rk30_gpio_irq_ack(struct irq_data *d)
277 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
278 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
280 GPIOAckIntr(bank->regbase, bit);
283 static int rk30_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)
285 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
286 u32 bit = offset_to_bit(offset);
289 spin_lock_irqsave(&bank->lock, flags);
290 GPIOSetPinDirection(bank->regbase, bit, GPIO_OUT);
291 GPIOSetPinLevel(bank->regbase, bit, val);
292 spin_unlock_irqrestore(&bank->lock, flags);
296 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
298 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
301 spin_lock_irqsave(&bank->lock, flags);
302 GPIOSetPinDirection(bank->regbase, offset_to_bit(offset), GPIO_IN);
303 spin_unlock_irqrestore(&bank->lock, flags);
306 static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset)
308 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
309 int gpio = offset + PIN_BASE + bank->id * 32;
311 #ifdef CONFIG_ARCH_RK2928
312 gpio_set_iomux(gpio);
317 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset)
319 return GPIOGetPinLevel(to_rk30_gpio_bank(chip)->regbase, offset_to_bit(offset));
322 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
324 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
327 spin_lock_irqsave(&bank->lock, flags);
328 GPIOSetPinLevel(bank->regbase, offset_to_bit(offset), val);
329 spin_unlock_irqrestore(&bank->lock, flags);
332 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable)
334 #if !defined(CONFIG_ARCH_RK3066B)
335 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
338 spin_lock_irqsave(&bank->lock, flags);
340 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0H_PULL + bank->id * 8, (1<<offset) | offset_to_bit(offset-16), !enable);
342 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0L_PULL + bank->id * 8, (1<<(offset+16)) | offset_to_bit(offset), !enable);
343 spin_unlock_irqrestore(&bank->lock, flags);
348 static int rk30_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
350 return chip->base + offset;
353 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
358 for (i = 0; i < chip->ngpio; i++) {
359 unsigned pin = chip->base + i;
360 struct gpio_chip *chip = pin_to_gpioChip(pin);
361 u32 bit = pin_to_bit(pin);
362 const char *gpio_label;
367 gpio_label = gpiochip_is_requested(chip, i);
369 seq_printf(s, "[%s] GPIO%s%d: ",
370 gpio_label, chip->label, i);
374 seq_printf(s, "!chip || !bit\t");
378 GPIOSetPinDirection(chip,bit,GPIO_IN);
379 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,bit));
386 static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
388 struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
389 struct irq_chip *chip = irq_desc_get_chip(desc);
393 unsigned unmasked = 0;
395 chained_irq_enter(chip, desc);
397 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
398 ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
400 gpio_irq = gpio_to_irq(bank->chip.base);
404 /* if gpio is edge triggered, clear condition
405 * before executing the hander so that we don't
408 if (ilr & (1 << pin)) {
410 chained_irq_exit(chip, desc);
413 generic_handle_irq(gpio_irq + pin);
418 chained_irq_exit(chip, desc);
421 static struct irq_chip rk30_gpio_irq_chip = {
423 .irq_ack = rk30_gpio_irq_ack,
424 .irq_disable = rk30_gpio_irq_mask,
425 .irq_mask = rk30_gpio_irq_mask,
426 .irq_unmask = rk30_gpio_irq_unmask,
427 .irq_set_type = rk30_gpio_irq_set_type,
428 .irq_set_wake = rk30_gpio_irq_set_wake,
431 void __init rk30_gpio_init(void)
433 unsigned int i, j, pin;
434 struct rk30_gpio_bank *bank;
436 bank = rk30_gpio_banks;
439 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
440 spin_lock_init(&bank->lock);
441 bank->clk = clk_get(NULL, bank->chip.label);
442 clk_enable(bank->clk);
443 gpiochip_add(&bank->chip);
445 __raw_writel(0, bank->regbase + GPIO_INTEN);
446 for (j = 0; j < 32; j++) {
447 unsigned int irq = gpio_to_irq(pin);
450 irq_set_lockdep_class(irq, &gpio_lock_class);
451 irq_set_chip_data(irq, bank);
452 irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
453 set_irq_flags(irq, IRQF_VALID);
457 irq_set_handler_data(bank->irq, bank);
458 irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
460 printk("%s: %d gpio irqs in %d banks\n", __func__, pin - PIN_BASE, ARRAY_SIZE(rk30_gpio_banks));
464 __weak void rk30_setgpio_suspend_board(void)
468 __weak void rk30_setgpio_resume_board(void)
472 static int rk30_gpio_suspend(void)
476 rk30_setgpio_suspend_board();
478 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
479 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
481 bank->saved_wakeup = __raw_readl(bank->regbase + GPIO_INTEN);
482 __raw_writel(bank->suspend_wakeup, bank->regbase + GPIO_INTEN);
484 if (!bank->suspend_wakeup)
485 clk_disable(bank->clk);
491 static void rk30_gpio_resume(void)
495 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
496 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
499 if (!bank->suspend_wakeup)
500 clk_enable(bank->clk);
502 /* keep enable for resume irq */
503 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
504 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->regbase + GPIO_INTEN);
507 rk30_setgpio_resume_board();
510 static struct syscore_ops rk30_gpio_syscore_ops = {
511 .suspend = rk30_gpio_suspend,
512 .resume = rk30_gpio_resume,
515 static int __init rk30_gpio_sysinit(void)
517 register_syscore_ops(&rk30_gpio_syscore_ops);
521 arch_initcall(rk30_gpio_sysinit);