1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/syscore_ops.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
31 #include <mach/iomux.h>
34 #include <asm/mach/irq.h>
36 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
37 #define MAX_PIN RK30_PIN3_PD7
38 #elif defined(CONFIG_ARCH_RK319X)
39 #define MAX_PIN RK30_PIN4_PD7
40 #elif defined(CONFIG_ARCH_RK30)
41 #define MAX_PIN RK30_PIN6_PB7
42 #elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
43 #define MAX_PIN RK2928_PIN3_PD7
44 #define RK30_GPIO0_PHYS RK2928_GPIO0_PHYS
45 #define RK30_GPIO0_BASE RK2928_GPIO0_BASE
46 #define RK30_GPIO0_SIZE RK2928_GPIO0_SIZE
47 #define RK30_GPIO1_PHYS RK2928_GPIO1_PHYS
48 #define RK30_GPIO1_BASE RK2928_GPIO1_BASE
49 #define RK30_GPIO1_SIZE RK2928_GPIO1_SIZE
50 #define RK30_GPIO2_PHYS RK2928_GPIO2_PHYS
51 #define RK30_GPIO2_BASE RK2928_GPIO2_BASE
52 #define RK30_GPIO2_SIZE RK2928_GPIO2_SIZE
53 #define RK30_GPIO3_PHYS RK2928_GPIO3_PHYS
54 #define RK30_GPIO3_BASE RK2928_GPIO3_BASE
55 #define RK30_GPIO3_SIZE RK2928_GPIO3_SIZE
56 #define RK30_GRF_BASE RK2928_GRF_BASE
59 #define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
61 struct rk30_gpio_bank {
62 struct gpio_chip chip;
65 void __iomem *regbase; /* Base of register bank */
72 static struct lock_class_key gpio_lock_class;
74 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
75 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
76 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset);
77 static int rk30_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
78 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
79 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable);
80 static int rk30_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
81 static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset);
83 #define RK30_GPIO_BANK(ID) \
86 .label = "gpio" #ID, \
87 .direction_input = rk30_gpiolib_direction_input, \
88 .direction_output = rk30_gpiolib_direction_output, \
89 .get = rk30_gpiolib_get, \
90 .set = rk30_gpiolib_set, \
91 .request = rk30_gpiolib_request, \
92 .pull_updown = rk30_gpiolib_pull_updown, \
93 .dbg_show = rk30_gpiolib_dbg_show, \
94 .to_irq = rk30_gpiolib_to_irq, \
95 .base = PIN_BASE + ID*NUM_GROUP, \
96 .ngpio = ID < 6 ? NUM_GROUP : 16, \
99 .irq = IRQ_GPIO##ID, \
100 .regbase = (unsigned char __iomem *) RK30_GPIO##ID##_BASE, \
103 static struct rk30_gpio_bank rk30_gpio_banks[] = {
116 static inline void rk30_gpio_bit_op(void __iomem *regbase, unsigned int offset, u32 bit, unsigned char flag)
118 u32 val = __raw_readl(regbase + offset);
123 __raw_writel(val, regbase + offset);
126 static inline struct gpio_chip *pin_to_gpio_chip(unsigned pin)
128 if (pin < PIN_BASE || pin > MAX_PIN)
133 if (likely(pin < ARRAY_SIZE(rk30_gpio_banks)))
134 return &(rk30_gpio_banks[pin].chip);
138 static inline unsigned gpio_to_bit(unsigned gpio)
141 return 1u << (gpio % NUM_GROUP);
144 static inline unsigned offset_to_bit(unsigned offset)
149 static void GPIOSetPinLevel(void __iomem *regbase, unsigned int bit, eGPIOPinLevel_t level)
151 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, 1);
152 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DR, bit, level);
155 static int GPIOGetPinLevel(void __iomem *regbase, unsigned int bit)
157 return ((__raw_readl(regbase + GPIO_EXT_PORT) & bit) != 0);
160 static void GPIOSetPinDirection(void __iomem *regbase, unsigned int bit, eGPIOPinDirection_t direction)
162 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, direction);
163 /* Enable debounce may halt cpu on wfi, disable it by default */
164 //rk30_gpio_bit_op(regbase, GPIO_DEBOUNCE, bit, 1);
167 static void GPIOEnableIntr(void __iomem *regbase, unsigned int bit)
169 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 1);
172 static void GPIODisableIntr(void __iomem *regbase, unsigned int bit)
174 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 0);
177 static void GPIOAckIntr(void __iomem *regbase, unsigned int bit)
179 rk30_gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);
182 static void GPIOSetIntrType(void __iomem *regbase, unsigned int bit, eGPIOIntType_t type)
186 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
187 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
190 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
191 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
193 case GPIOEdgelFalling:
194 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
195 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
197 case GPIOEdgelRising:
198 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
199 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
204 static int rk30_gpio_irq_set_type(struct irq_data *d, unsigned int type)
206 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
207 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
208 eGPIOIntType_t int_type;
212 case IRQ_TYPE_EDGE_RISING:
213 int_type = GPIOEdgelRising;
215 case IRQ_TYPE_EDGE_FALLING:
216 int_type = GPIOEdgelFalling;
218 case IRQ_TYPE_LEVEL_HIGH:
219 int_type = GPIOLevelHigh;
221 case IRQ_TYPE_LEVEL_LOW:
222 int_type = GPIOLevelLow;
228 spin_lock_irqsave(&bank->lock, flags);
229 //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
230 GPIOSetPinDirection(bank->regbase, bit, GPIO_IN);
231 GPIOSetIntrType(bank->regbase, bit, int_type);
232 spin_unlock_irqrestore(&bank->lock, flags);
234 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
235 __irq_set_handler_locked(d->irq, handle_level_irq);
236 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
237 __irq_set_handler_locked(d->irq, handle_edge_irq);
242 static int rk30_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
244 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
245 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
248 spin_lock_irqsave(&bank->lock, flags);
250 bank->suspend_wakeup |= bit;
252 bank->suspend_wakeup &= ~bit;
253 spin_unlock_irqrestore(&bank->lock, flags);
258 static void rk30_gpio_irq_unmask(struct irq_data *d)
260 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
261 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
264 spin_lock_irqsave(&bank->lock, flags);
265 GPIOEnableIntr(bank->regbase, bit);
266 spin_unlock_irqrestore(&bank->lock, flags);
269 static void rk30_gpio_irq_mask(struct irq_data *d)
271 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
272 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
275 spin_lock_irqsave(&bank->lock, flags);
276 GPIODisableIntr(bank->regbase, bit);
277 spin_unlock_irqrestore(&bank->lock, flags);
280 static void rk30_gpio_irq_ack(struct irq_data *d)
282 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
283 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
285 GPIOAckIntr(bank->regbase, bit);
288 static int rk30_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)
290 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
291 u32 bit = offset_to_bit(offset);
294 spin_lock_irqsave(&bank->lock, flags);
295 GPIOSetPinDirection(bank->regbase, bit, GPIO_OUT);
296 GPIOSetPinLevel(bank->regbase, bit, val);
297 spin_unlock_irqrestore(&bank->lock, flags);
301 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
303 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
306 spin_lock_irqsave(&bank->lock, flags);
307 GPIOSetPinDirection(bank->regbase, offset_to_bit(offset), GPIO_IN);
308 spin_unlock_irqrestore(&bank->lock, flags);
312 static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset)
314 iomux_set_gpio_mode(chip->base + offset);
318 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset)
320 return GPIOGetPinLevel(to_rk30_gpio_bank(chip)->regbase, offset_to_bit(offset));
323 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
325 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
328 spin_lock_irqsave(&bank->lock, flags);
329 GPIOSetPinLevel(bank->regbase, offset_to_bit(offset), val);
330 spin_unlock_irqrestore(&bank->lock, flags);
333 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enum GPIOPullType type)
335 #if defined(CONFIG_ARCH_RK3066B)
337 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
341 #if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
344 * 2'b00: Z(Noraml operaton)
345 * 2'b01: weak 1(pull-up)
346 * 2'b10: weak 0(pull-down)
347 * 2'b11: Repeater(Bus keeper)
360 WARN(1, "%s: unsupported pull type %d\n", __func__, type);
364 #if defined(CONFIG_ARCH_RK319X)
366 base = RK319X_BB_GRF_BASE + BB_GRF_GPIO0A_PULL + ((offset / 8) * 4);
367 offset = (offset % 8) * 2;
368 __raw_writel((0x3 << (16 + offset)) | (val << offset), base);
370 base = RK319X_GRF_BASE + GRF_GPIO1A_PULL + (bank->id - 1) * 16 + ((offset / 8) * 4);
371 offset = (7 - (offset % 8)) * 2;
372 __raw_writel((0x3 << (16 + offset)) | (val << offset), base);
375 if (bank->id == 0 && offset < 12) {
376 base = RK30_PMU_BASE + PMU_GPIO0A_PULL + ((offset / 8) * 4);
377 offset = (offset % 8) * 2;
378 __raw_writel((0x3 << (16 + offset)) | (val << offset), base);
380 base = RK30_GRF_BASE + GRF_GPIO0B_PULL - 4 + bank->id * 16 + ((offset / 8) * 4);
381 offset = (7 - (offset % 8)) * 2;
382 __raw_writel((0x3 << (16 + offset)) | (val << offset), base);
386 /* RK30XX && RK292X */
388 * Values written to this register independently
389 * control Pullup/Pulldown or not for the
390 * corresponding data bit in GPIO.
391 * 0: pull up/down enable, PAD type will decide
392 * to be up or down, not related with this value
393 * 1: pull up/down disable
395 val = (type == PullDisable) ? 1 : 0;
396 base = RK30_GRF_BASE + GRF_GPIO0L_PULL + bank->id * 8 + ((offset / 16) * 4);
397 offset = offset % 16;
398 __raw_writel((1 << (16 + offset)) | (val << offset), base);
404 static int rk30_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
406 return chip->base + offset;
409 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
414 for (i = 0; i < chip->ngpio; i++) {
415 unsigned pin = chip->base + i;
416 struct gpio_chip *chip = pin_to_gpioChip(pin);
417 u32 bit = pin_to_bit(pin);
418 const char *gpio_label;
423 gpio_label = gpiochip_is_requested(chip, i);
425 seq_printf(s, "[%s] GPIO%s%d: ",
426 gpio_label, chip->label, i);
430 seq_printf(s, "!chip || !bit\t");
434 GPIOSetPinDirection(chip,bit,GPIO_IN);
435 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,bit));
442 static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
444 struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
445 struct irq_chip *chip = irq_desc_get_chip(desc);
449 unsigned unmasked = 0;
451 chained_irq_enter(chip, desc);
453 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
454 ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
456 gpio_irq = gpio_to_irq(bank->chip.base);
460 /* if gpio is edge triggered, clear condition
461 * before executing the hander so that we don't
464 if (ilr & (1 << pin)) {
466 chained_irq_exit(chip, desc);
469 generic_handle_irq(gpio_irq + pin);
474 chained_irq_exit(chip, desc);
477 static struct irq_chip rk30_gpio_irq_chip = {
479 .irq_ack = rk30_gpio_irq_ack,
480 .irq_disable = rk30_gpio_irq_mask,
481 .irq_mask = rk30_gpio_irq_mask,
482 .irq_unmask = rk30_gpio_irq_unmask,
483 .irq_set_type = rk30_gpio_irq_set_type,
484 .irq_set_wake = rk30_gpio_irq_set_wake,
487 void __init rk30_gpio_init(void)
489 unsigned int i, j, pin, irqs = 0;
490 struct rk30_gpio_bank *bank;
492 bank = rk30_gpio_banks;
494 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
495 spin_lock_init(&bank->lock);
496 bank->clk = clk_get(NULL, bank->chip.label);
497 clk_enable(bank->clk);
498 gpiochip_add(&bank->chip);
500 __raw_writel(0, bank->regbase + GPIO_INTEN);
501 pin = bank->chip.base;
502 for (j = 0; j < 32; j++) {
503 unsigned int irq = gpio_to_irq(pin);
506 irq_set_lockdep_class(irq, &gpio_lock_class);
507 irq_set_chip_data(irq, bank);
508 irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
509 set_irq_flags(irq, IRQF_VALID);
514 irq_set_handler_data(bank->irq, bank);
515 irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
517 printk("%s: %d gpio irqs in %d banks\n", __func__, irqs, ARRAY_SIZE(rk30_gpio_banks));
521 __weak void rk30_setgpio_suspend_board(void)
525 __weak void rk30_setgpio_resume_board(void)
529 static int rk30_gpio_suspend(void)
533 rk30_setgpio_suspend_board();
535 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
536 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
538 bank->saved_wakeup = __raw_readl(bank->regbase + GPIO_INTEN);
539 __raw_writel(bank->suspend_wakeup, bank->regbase + GPIO_INTEN);
541 if (!bank->suspend_wakeup)
542 clk_disable(bank->clk);
548 static void rk30_gpio_resume(void)
552 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
553 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
556 if (!bank->suspend_wakeup)
557 clk_enable(bank->clk);
559 /* keep enable for resume irq */
560 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
561 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->regbase + GPIO_INTEN);
564 rk30_setgpio_resume_board();
567 static struct syscore_ops rk30_gpio_syscore_ops = {
568 .suspend = rk30_gpio_suspend,
569 .resume = rk30_gpio_resume,
572 static int __init rk30_gpio_sysinit(void)
574 register_syscore_ops(&rk30_gpio_syscore_ops);
578 arch_initcall(rk30_gpio_sysinit);