1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/syscore_ops.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
31 #include <mach/iomux.h>
34 #include <asm/mach/irq.h>
36 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
37 #define MAX_PIN RK30_PIN3_PD7
38 #elif defined(CONFIG_ARCH_RK30)
39 #define MAX_PIN RK30_PIN6_PB7
40 #elif defined(CONFIG_ARCH_RK2928)
41 #define MAX_PIN RK2928_PIN3_PD7
42 #define RK30_GPIO0_PHYS RK2928_GPIO0_PHYS
43 #define RK30_GPIO0_BASE RK2928_GPIO0_BASE
44 #define RK30_GPIO0_SIZE RK2928_GPIO0_SIZE
45 #define RK30_GPIO1_PHYS RK2928_GPIO1_PHYS
46 #define RK30_GPIO1_BASE RK2928_GPIO1_BASE
47 #define RK30_GPIO1_SIZE RK2928_GPIO1_SIZE
48 #define RK30_GPIO2_PHYS RK2928_GPIO2_PHYS
49 #define RK30_GPIO2_BASE RK2928_GPIO2_BASE
50 #define RK30_GPIO2_SIZE RK2928_GPIO2_SIZE
51 #define RK30_GPIO3_PHYS RK2928_GPIO3_PHYS
52 #define RK30_GPIO3_BASE RK2928_GPIO3_BASE
53 #define RK30_GPIO3_SIZE RK2928_GPIO3_SIZE
54 #define RK30_GRF_BASE RK2928_GRF_BASE
57 #define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
59 struct rk30_gpio_bank {
60 struct gpio_chip chip;
63 void __iomem *regbase; /* Base of register bank */
70 static struct lock_class_key gpio_lock_class;
72 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
73 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
74 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset);
75 static int rk30_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
76 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
77 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable);
78 static int rk30_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
79 static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset);
81 #define RK30_GPIO_BANK(ID) \
84 .label = "gpio" #ID, \
85 .direction_input = rk30_gpiolib_direction_input, \
86 .direction_output = rk30_gpiolib_direction_output, \
87 .get = rk30_gpiolib_get, \
88 .set = rk30_gpiolib_set, \
89 .request = rk30_gpiolib_request, \
90 .pull_updown = rk30_gpiolib_pull_updown, \
91 .dbg_show = rk30_gpiolib_dbg_show, \
92 .to_irq = rk30_gpiolib_to_irq, \
93 .base = PIN_BASE + ID*NUM_GROUP, \
94 .ngpio = ID < 6 ? NUM_GROUP : 16, \
97 .irq = IRQ_GPIO##ID, \
98 .regbase = (unsigned char __iomem *) RK30_GPIO##ID##_BASE, \
101 static struct rk30_gpio_bank rk30_gpio_banks[] = {
106 #if defined(CONFIG_ARCH_RK30) && !defined(CONFIG_ARCH_RK3066B)
112 static inline void rk30_gpio_bit_op(void __iomem *regbase, unsigned int offset, u32 bit, unsigned char flag)
114 u32 val = __raw_readl(regbase + offset);
119 __raw_writel(val, regbase + offset);
122 static inline struct gpio_chip *pin_to_gpio_chip(unsigned pin)
124 if (pin < PIN_BASE || pin > MAX_PIN)
129 if (likely(pin < ARRAY_SIZE(rk30_gpio_banks)))
130 return &(rk30_gpio_banks[pin].chip);
134 static inline unsigned gpio_to_bit(unsigned gpio)
137 return 1u << (gpio % NUM_GROUP);
140 static inline unsigned offset_to_bit(unsigned offset)
145 static void GPIOSetPinLevel(void __iomem *regbase, unsigned int bit, eGPIOPinLevel_t level)
147 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, 1);
148 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DR, bit, level);
151 static int GPIOGetPinLevel(void __iomem *regbase, unsigned int bit)
153 return ((__raw_readl(regbase + GPIO_EXT_PORT) & bit) != 0);
156 static void GPIOSetPinDirection(void __iomem *regbase, unsigned int bit, eGPIOPinDirection_t direction)
158 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, direction);
159 /* Enable debounce may halt cpu on wfi, disable it by default */
160 //rk30_gpio_bit_op(regbase, GPIO_DEBOUNCE, bit, 1);
163 static void GPIOEnableIntr(void __iomem *regbase, unsigned int bit)
165 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 1);
168 static void GPIODisableIntr(void __iomem *regbase, unsigned int bit)
170 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 0);
173 static void GPIOAckIntr(void __iomem *regbase, unsigned int bit)
175 rk30_gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);
178 static void GPIOSetIntrType(void __iomem *regbase, unsigned int bit, eGPIOIntType_t type)
182 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
183 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
186 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
187 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
189 case GPIOEdgelFalling:
190 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
191 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
193 case GPIOEdgelRising:
194 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
195 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
200 static int rk30_gpio_irq_set_type(struct irq_data *d, unsigned int type)
202 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
203 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
204 eGPIOIntType_t int_type;
208 case IRQ_TYPE_EDGE_RISING:
209 int_type = GPIOEdgelRising;
211 case IRQ_TYPE_EDGE_FALLING:
212 int_type = GPIOEdgelFalling;
214 case IRQ_TYPE_LEVEL_HIGH:
215 int_type = GPIOLevelHigh;
217 case IRQ_TYPE_LEVEL_LOW:
218 int_type = GPIOLevelLow;
224 spin_lock_irqsave(&bank->lock, flags);
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226 GPIOSetPinDirection(bank->regbase, bit, GPIO_IN);
227 GPIOSetIntrType(bank->regbase, bit, int_type);
228 spin_unlock_irqrestore(&bank->lock, flags);
230 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
231 __irq_set_handler_locked(d->irq, handle_level_irq);
232 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
233 __irq_set_handler_locked(d->irq, handle_edge_irq);
238 static int rk30_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
240 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
241 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
244 spin_lock_irqsave(&bank->lock, flags);
246 bank->suspend_wakeup |= bit;
248 bank->suspend_wakeup &= ~bit;
249 spin_unlock_irqrestore(&bank->lock, flags);
254 static void rk30_gpio_irq_unmask(struct irq_data *d)
256 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
257 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
260 spin_lock_irqsave(&bank->lock, flags);
261 GPIOEnableIntr(bank->regbase, bit);
262 spin_unlock_irqrestore(&bank->lock, flags);
265 static void rk30_gpio_irq_mask(struct irq_data *d)
267 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
268 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
271 spin_lock_irqsave(&bank->lock, flags);
272 GPIODisableIntr(bank->regbase, bit);
273 spin_unlock_irqrestore(&bank->lock, flags);
276 static void rk30_gpio_irq_ack(struct irq_data *d)
278 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
279 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
281 GPIOAckIntr(bank->regbase, bit);
284 static int rk30_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)
286 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
287 u32 bit = offset_to_bit(offset);
290 spin_lock_irqsave(&bank->lock, flags);
291 GPIOSetPinDirection(bank->regbase, bit, GPIO_OUT);
292 GPIOSetPinLevel(bank->regbase, bit, val);
293 spin_unlock_irqrestore(&bank->lock, flags);
297 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
299 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
302 spin_lock_irqsave(&bank->lock, flags);
303 GPIOSetPinDirection(bank->regbase, offset_to_bit(offset), GPIO_IN);
304 spin_unlock_irqrestore(&bank->lock, flags);
308 static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset)
310 iomux_set_gpio_mode(chip->base + offset);
314 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset)
316 return GPIOGetPinLevel(to_rk30_gpio_bank(chip)->regbase, offset_to_bit(offset));
319 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
321 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
324 spin_lock_irqsave(&bank->lock, flags);
325 GPIOSetPinLevel(bank->regbase, offset_to_bit(offset), val);
326 spin_unlock_irqrestore(&bank->lock, flags);
329 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enum GPIOPullType type)
331 #if defined(CONFIG_ARCH_RK3066B)
333 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
337 #if defined(CONFIG_ARCH_RK3188)
340 * 2'b00: Z(Noraml operaton)
341 * 2'b01: weak 1(pull-up)
342 * 2'b10: weak 0(pull-down)
343 * 2'b11: Repeater(Bus keeper)
356 WARN(1, "%s: unsupported pull type %d\n", __func__, type);
360 if (bank->id == 0 && offset < 12) {
361 base = RK30_PMU_BASE + PMU_GPIO0A_PULL + ((offset / 8) * 4);
362 offset = (offset % 8) * 2;
363 __raw_writel((0x3 << (16 + offset)) | (val << offset), base);
365 base = RK30_GRF_BASE + GRF_GPIO0B_PULL - 4 + bank->id * 16 + ((offset / 8) * 4);
366 offset = (7 - (offset % 8)) * 2;
367 __raw_writel((0x3 << (16 + offset)) | (val << offset), base);
370 /* RK30XX && RK292X */
372 * Values written to this register independently
373 * control Pullup/Pulldown or not for the
374 * corresponding data bit in GPIO.
375 * 0: pull up/down enable, PAD type will decide
376 * to be up or down, not related with this value
377 * 1: pull up/down disable
379 val = (type == PullDisable) ? 1 : 0;
380 base = RK30_GRF_BASE + GRF_GPIO0L_PULL + bank->id * 8 + ((offset / 16) * 4);
381 offset = offset % 16;
382 __raw_writel((1 << (16 + offset)) | (val << offset), base);
388 static int rk30_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
390 return chip->base + offset;
393 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
398 for (i = 0; i < chip->ngpio; i++) {
399 unsigned pin = chip->base + i;
400 struct gpio_chip *chip = pin_to_gpioChip(pin);
401 u32 bit = pin_to_bit(pin);
402 const char *gpio_label;
407 gpio_label = gpiochip_is_requested(chip, i);
409 seq_printf(s, "[%s] GPIO%s%d: ",
410 gpio_label, chip->label, i);
414 seq_printf(s, "!chip || !bit\t");
418 GPIOSetPinDirection(chip,bit,GPIO_IN);
419 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,bit));
426 static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
428 struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
429 struct irq_chip *chip = irq_desc_get_chip(desc);
433 unsigned unmasked = 0;
435 chained_irq_enter(chip, desc);
437 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
438 ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
440 gpio_irq = gpio_to_irq(bank->chip.base);
444 /* if gpio is edge triggered, clear condition
445 * before executing the hander so that we don't
448 if (ilr & (1 << pin)) {
450 chained_irq_exit(chip, desc);
453 generic_handle_irq(gpio_irq + pin);
458 chained_irq_exit(chip, desc);
461 static struct irq_chip rk30_gpio_irq_chip = {
463 .irq_ack = rk30_gpio_irq_ack,
464 .irq_disable = rk30_gpio_irq_mask,
465 .irq_mask = rk30_gpio_irq_mask,
466 .irq_unmask = rk30_gpio_irq_unmask,
467 .irq_set_type = rk30_gpio_irq_set_type,
468 .irq_set_wake = rk30_gpio_irq_set_wake,
471 void __init rk30_gpio_init(void)
473 unsigned int i, j, pin, irqs = 0;
474 struct rk30_gpio_bank *bank;
476 bank = rk30_gpio_banks;
478 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
479 spin_lock_init(&bank->lock);
480 bank->clk = clk_get(NULL, bank->chip.label);
481 clk_enable(bank->clk);
482 gpiochip_add(&bank->chip);
484 __raw_writel(0, bank->regbase + GPIO_INTEN);
485 pin = bank->chip.base;
486 for (j = 0; j < 32; j++) {
487 unsigned int irq = gpio_to_irq(pin);
490 irq_set_lockdep_class(irq, &gpio_lock_class);
491 irq_set_chip_data(irq, bank);
492 irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
493 set_irq_flags(irq, IRQF_VALID);
498 irq_set_handler_data(bank->irq, bank);
499 irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
501 printk("%s: %d gpio irqs in %d banks\n", __func__, irqs, ARRAY_SIZE(rk30_gpio_banks));
505 __weak void rk30_setgpio_suspend_board(void)
509 __weak void rk30_setgpio_resume_board(void)
513 static int rk30_gpio_suspend(void)
517 rk30_setgpio_suspend_board();
519 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
520 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
522 bank->saved_wakeup = __raw_readl(bank->regbase + GPIO_INTEN);
523 __raw_writel(bank->suspend_wakeup, bank->regbase + GPIO_INTEN);
525 if (!bank->suspend_wakeup)
526 clk_disable(bank->clk);
532 static void rk30_gpio_resume(void)
536 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
537 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
540 if (!bank->suspend_wakeup)
541 clk_enable(bank->clk);
543 /* keep enable for resume irq */
544 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
545 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->regbase + GPIO_INTEN);
548 rk30_setgpio_resume_board();
551 static struct syscore_ops rk30_gpio_syscore_ops = {
552 .suspend = rk30_gpio_suspend,
553 .resume = rk30_gpio_resume,
556 static int __init rk30_gpio_sysinit(void)
558 register_syscore_ops(&rk30_gpio_syscore_ops);
562 arch_initcall(rk30_gpio_sysinit);