2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-gpio.h>
38 #include <plat/gpio-core.h>
39 #include <plat/gpio-cfg.h>
40 #include <plat/gpio-cfg-helpers.h>
43 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
44 unsigned int off, samsung_gpio_pull_t pull)
46 void __iomem *reg = chip->base + 0x08;
50 pup = __raw_readl(reg);
53 __raw_writel(pup, reg);
58 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
61 void __iomem *reg = chip->base + 0x08;
63 u32 pup = __raw_readl(reg);
68 return (__force samsung_gpio_pull_t)pup;
71 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
72 unsigned int off, samsung_gpio_pull_t pull)
75 case S3C_GPIO_PULL_NONE:
78 case S3C_GPIO_PULL_UP:
81 case S3C_GPIO_PULL_DOWN:
85 return samsung_gpio_setpull_updown(chip, off, pull);
88 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
91 samsung_gpio_pull_t pull;
93 pull = samsung_gpio_getpull_updown(chip, off);
97 pull = S3C_GPIO_PULL_UP;
101 pull = S3C_GPIO_PULL_NONE;
104 pull = S3C_GPIO_PULL_DOWN;
111 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
112 unsigned int off, samsung_gpio_pull_t pull,
113 samsung_gpio_pull_t updown)
115 void __iomem *reg = chip->base + 0x08;
116 u32 pup = __raw_readl(reg);
120 else if (pull == S3C_GPIO_PULL_NONE)
125 __raw_writel(pup, reg);
129 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
131 samsung_gpio_pull_t updown)
133 void __iomem *reg = chip->base + 0x08;
134 u32 pup = __raw_readl(reg);
137 return pup ? S3C_GPIO_PULL_NONE : updown;
140 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
143 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
146 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
147 unsigned int off, samsung_gpio_pull_t pull)
149 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
152 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
155 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
158 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
159 unsigned int off, samsung_gpio_pull_t pull)
161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
164 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
165 unsigned int off, samsung_gpio_pull_t pull)
167 if (pull == S3C_GPIO_PULL_UP)
170 return samsung_gpio_setpull_updown(chip, off, pull);
173 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
176 samsung_gpio_pull_t pull;
178 pull = samsung_gpio_getpull_updown(chip, off);
181 pull = S3C_GPIO_PULL_UP;
187 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
188 * @chip: The gpio chip that is being configured.
189 * @off: The offset for the GPIO being configured.
190 * @cfg: The configuration value to set.
192 * This helper deal with the GPIO cases where the control register
193 * has two bits of configuration per gpio, which have the following
197 * 1x = special function
200 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
201 unsigned int off, unsigned int cfg)
203 void __iomem *reg = chip->base;
204 unsigned int shift = off * 2;
207 if (samsung_gpio_is_cfg_special(cfg)) {
215 con = __raw_readl(reg);
216 con &= ~(0x3 << shift);
218 __raw_writel(con, reg);
224 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
225 * @chip: The gpio chip that is being configured.
226 * @off: The offset for the GPIO being configured.
228 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
229 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
230 * S3C_GPIO_SPECIAL() macro.
233 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
238 con = __raw_readl(chip->base);
242 /* this conversion works for IN and OUT as well as special mode */
243 return S3C_GPIO_SPECIAL(con);
247 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
248 * @chip: The gpio chip that is being configured.
249 * @off: The offset for the GPIO being configured.
250 * @cfg: The configuration value to set.
252 * This helper deal with the GPIO cases where the control register has 4 bits
253 * of control per GPIO, generally in the form of:
256 * others = Special functions (dependent on bank)
258 * Note, since the code to deal with the case where there are two control
259 * registers instead of one, we do not have a separate set of functions for
263 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
264 unsigned int off, unsigned int cfg)
266 void __iomem *reg = chip->base;
267 unsigned int shift = (off & 7) * 4;
270 if (off < 8 && chip->chip.ngpio > 8)
273 if (samsung_gpio_is_cfg_special(cfg)) {
278 con = __raw_readl(reg);
279 con &= ~(0xf << shift);
281 __raw_writel(con, reg);
287 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
288 * @chip: The gpio chip that is being configured.
289 * @off: The offset for the GPIO being configured.
291 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
292 * register setting into a value the software can use, such as could be passed
293 * to samsung_gpio_setcfg_4bit().
295 * @sa samsung_gpio_getcfg_2bit
298 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
301 void __iomem *reg = chip->base;
302 unsigned int shift = (off & 7) * 4;
305 if (off < 8 && chip->chip.ngpio > 8)
308 con = __raw_readl(reg);
312 /* this conversion works for IN and OUT as well as special mode */
313 return S3C_GPIO_SPECIAL(con);
316 #ifdef CONFIG_PLAT_S3C24XX
318 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
319 * @chip: The gpio chip that is being configured.
320 * @off: The offset for the GPIO being configured.
321 * @cfg: The configuration value to set.
323 * This helper deal with the GPIO cases where the control register
324 * has one bit of configuration for the gpio, where setting the bit
325 * means the pin is in special function mode and unset means output.
328 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
329 unsigned int off, unsigned int cfg)
331 void __iomem *reg = chip->base;
332 unsigned int shift = off;
335 if (samsung_gpio_is_cfg_special(cfg)) {
338 /* Map output to 0, and SFN2 to 1 */
346 con = __raw_readl(reg);
347 con &= ~(0x1 << shift);
349 __raw_writel(con, reg);
355 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
356 * @chip: The gpio chip that is being configured.
357 * @off: The offset for the GPIO being configured.
359 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
360 * GPIO configuration value.
362 * @sa samsung_gpio_getcfg_2bit
363 * @sa samsung_gpio_getcfg_4bit
366 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
371 con = __raw_readl(chip->base);
376 return S3C_GPIO_SFN(con);
380 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
381 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
382 unsigned int off, unsigned int cfg)
384 void __iomem *reg = chip->base;
395 shift = (off & 7) * 4;
399 shift = ((off + 1) & 7) * 4;
402 shift = ((off + 1) & 7) * 4;
406 if (samsung_gpio_is_cfg_special(cfg)) {
411 con = __raw_readl(reg);
412 con &= ~(0xf << shift);
414 __raw_writel(con, reg);
420 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
423 for (; nr_chips > 0; nr_chips--, chipcfg++) {
424 if (!chipcfg->set_config)
425 chipcfg->set_config = samsung_gpio_setcfg_4bit;
426 if (!chipcfg->get_config)
427 chipcfg->get_config = samsung_gpio_getcfg_4bit;
428 if (!chipcfg->set_pull)
429 chipcfg->set_pull = samsung_gpio_setpull_updown;
430 if (!chipcfg->get_pull)
431 chipcfg->get_pull = samsung_gpio_getpull_updown;
435 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
436 .set_config = samsung_gpio_setcfg_2bit,
437 .get_config = samsung_gpio_getcfg_2bit,
440 #ifdef CONFIG_PLAT_S3C24XX
441 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
442 .set_config = s3c24xx_gpio_setcfg_abank,
443 .get_config = s3c24xx_gpio_getcfg_abank,
447 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
448 static struct samsung_gpio_cfg exynos_gpio_cfg = {
449 .set_pull = exynos_gpio_setpull,
450 .get_pull = exynos_gpio_getpull,
451 .set_config = samsung_gpio_setcfg_4bit,
452 .get_config = samsung_gpio_getcfg_4bit,
456 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
457 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
459 .set_config = s5p64x0_gpio_setcfg_rbank,
460 .get_config = samsung_gpio_getcfg_4bit,
461 .set_pull = samsung_gpio_setpull_updown,
462 .get_pull = samsung_gpio_getpull_updown,
466 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
481 .set_config = samsung_gpio_setcfg_2bit,
482 .get_config = samsung_gpio_getcfg_2bit,
486 .set_config = samsung_gpio_setcfg_2bit,
487 .get_config = samsung_gpio_getcfg_2bit,
491 .set_config = samsung_gpio_setcfg_2bit,
492 .get_config = samsung_gpio_getcfg_2bit,
495 .set_config = samsung_gpio_setcfg_2bit,
496 .get_config = samsung_gpio_getcfg_2bit,
499 .set_pull = exynos_gpio_setpull,
500 .get_pull = exynos_gpio_getpull,
504 .set_pull = exynos_gpio_setpull,
505 .get_pull = exynos_gpio_getpull,
510 * Default routines for controlling GPIO, based on the original S3C24XX
511 * GPIO functions which deal with the case where each gpio bank of the
512 * chip is as following:
514 * base + 0x00: Control register, 2 bits per gpio
515 * gpio n: 2 bits starting at (2*n)
516 * 00 = input, 01 = output, others mean special-function
517 * base + 0x04: Data register, 1 bit per gpio
521 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
523 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
524 void __iomem *base = ourchip->base;
528 samsung_gpio_lock(ourchip, flags);
530 con = __raw_readl(base + 0x00);
531 con &= ~(3 << (offset * 2));
533 __raw_writel(con, base + 0x00);
535 samsung_gpio_unlock(ourchip, flags);
539 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
540 unsigned offset, int value)
542 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
543 void __iomem *base = ourchip->base;
548 samsung_gpio_lock(ourchip, flags);
550 dat = __raw_readl(base + 0x04);
551 dat &= ~(1 << offset);
554 __raw_writel(dat, base + 0x04);
556 con = __raw_readl(base + 0x00);
557 con &= ~(3 << (offset * 2));
558 con |= 1 << (offset * 2);
560 __raw_writel(con, base + 0x00);
561 __raw_writel(dat, base + 0x04);
563 samsung_gpio_unlock(ourchip, flags);
568 * The samsung_gpiolib_4bit routines are to control the gpio banks where
569 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
572 * base + 0x00: Control register, 4 bits per gpio
573 * gpio n: 4 bits starting at (4*n)
574 * 0000 = input, 0001 = output, others mean special-function
575 * base + 0x04: Data register, 1 bit per gpio
578 * Note, since the data register is one bit per gpio and is at base + 0x4
579 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
580 * state of the output.
583 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
586 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
587 void __iomem *base = ourchip->base;
590 con = __raw_readl(base + GPIOCON_OFF);
591 if (ourchip->bitmap_gpio_int & BIT(offset))
592 con |= 0xf << con_4bit_shift(offset);
594 con &= ~(0xf << con_4bit_shift(offset));
595 __raw_writel(con, base + GPIOCON_OFF);
597 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
602 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
603 unsigned int offset, int value)
605 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
606 void __iomem *base = ourchip->base;
610 con = __raw_readl(base + GPIOCON_OFF);
611 con &= ~(0xf << con_4bit_shift(offset));
612 con |= 0x1 << con_4bit_shift(offset);
614 dat = __raw_readl(base + GPIODAT_OFF);
619 dat &= ~(1 << offset);
621 __raw_writel(dat, base + GPIODAT_OFF);
622 __raw_writel(con, base + GPIOCON_OFF);
623 __raw_writel(dat, base + GPIODAT_OFF);
625 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
631 * The next set of routines are for the case where the GPIO configuration
632 * registers are 4 bits per GPIO but there is more than one register (the
633 * bank has more than 8 GPIOs.
635 * This case is the similar to the 4 bit case, but the registers are as
638 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
639 * gpio n: 4 bits starting at (4*n)
640 * 0000 = input, 0001 = output, others mean special-function
641 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
642 * gpio n: 4 bits starting at (4*n)
643 * 0000 = input, 0001 = output, others mean special-function
644 * base + 0x08: Data register, 1 bit per gpio
647 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
648 * routines we store the 'base + 0x4' address so that these routines see
649 * the data register at ourchip->base + 0x04.
652 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
655 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
656 void __iomem *base = ourchip->base;
657 void __iomem *regcon = base;
665 con = __raw_readl(regcon);
666 con &= ~(0xf << con_4bit_shift(offset));
667 __raw_writel(con, regcon);
669 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
674 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
675 unsigned int offset, int value)
677 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
678 void __iomem *base = ourchip->base;
679 void __iomem *regcon = base;
682 unsigned con_offset = offset;
689 con = __raw_readl(regcon);
690 con &= ~(0xf << con_4bit_shift(con_offset));
691 con |= 0x1 << con_4bit_shift(con_offset);
693 dat = __raw_readl(base + GPIODAT_OFF);
698 dat &= ~(1 << offset);
700 __raw_writel(dat, base + GPIODAT_OFF);
701 __raw_writel(con, regcon);
702 __raw_writel(dat, base + GPIODAT_OFF);
704 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
709 #ifdef CONFIG_PLAT_S3C24XX
710 /* The next set of routines are for the case of s3c24xx bank a */
712 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
717 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
718 unsigned offset, int value)
720 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
721 void __iomem *base = ourchip->base;
726 local_irq_save(flags);
728 con = __raw_readl(base + 0x00);
729 dat = __raw_readl(base + 0x04);
731 dat &= ~(1 << offset);
735 __raw_writel(dat, base + 0x04);
737 con &= ~(1 << offset);
739 __raw_writel(con, base + 0x00);
740 __raw_writel(dat, base + 0x04);
742 local_irq_restore(flags);
747 /* The next set of routines are for the case of s5p64x0 bank r */
749 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
774 samsung_gpio_lock(ourchip, flags);
776 con = __raw_readl(regcon);
777 con &= ~(0xf << con_4bit_shift(offset));
778 __raw_writel(con, regcon);
780 samsung_gpio_unlock(ourchip, flags);
785 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
786 unsigned int offset, int value)
788 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
789 void __iomem *base = ourchip->base;
790 void __iomem *regcon = base;
794 unsigned con_offset = offset;
796 switch (con_offset) {
812 samsung_gpio_lock(ourchip, flags);
814 con = __raw_readl(regcon);
815 con &= ~(0xf << con_4bit_shift(con_offset));
816 con |= 0x1 << con_4bit_shift(con_offset);
818 dat = __raw_readl(base + GPIODAT_OFF);
822 dat &= ~(1 << offset);
824 __raw_writel(con, regcon);
825 __raw_writel(dat, base + GPIODAT_OFF);
827 samsung_gpio_unlock(ourchip, flags);
832 static void samsung_gpiolib_set(struct gpio_chip *chip,
833 unsigned offset, int value)
835 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
836 void __iomem *base = ourchip->base;
840 samsung_gpio_lock(ourchip, flags);
842 dat = __raw_readl(base + 0x04);
843 dat &= ~(1 << offset);
846 __raw_writel(dat, base + 0x04);
848 samsung_gpio_unlock(ourchip, flags);
851 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
853 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
856 val = __raw_readl(ourchip->base + 0x04);
864 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
865 * for use with the configuration calls, and other parts of the s3c gpiolib
868 * Not all s3c support code will need this, as some configurations of cpu
869 * may only support one or two different configuration options and have an
870 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
871 * the machine support file should provide its own samsung_gpiolib_getchip()
872 * and any other necessary functions.
875 #ifdef CONFIG_S3C_GPIO_TRACK
876 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
878 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
883 gpn = chip->chip.base;
884 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
885 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
886 s3c_gpios[gpn] = chip;
889 #endif /* CONFIG_S3C_GPIO_TRACK */
892 * samsung_gpiolib_add() - add the Samsung gpio_chip.
893 * @chip: The chip to register
895 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
896 * information and makes the necessary alterations for the platform and
897 * notes the information for use with the configuration systems and any
898 * other parts of the system.
901 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
903 struct gpio_chip *gc = &chip->chip;
910 spin_lock_init(&chip->lock);
912 if (!gc->direction_input)
913 gc->direction_input = samsung_gpiolib_2bit_input;
914 if (!gc->direction_output)
915 gc->direction_output = samsung_gpiolib_2bit_output;
917 gc->set = samsung_gpiolib_set;
919 gc->get = samsung_gpiolib_get;
922 if (chip->pm != NULL) {
923 if (!chip->pm->save || !chip->pm->resume)
924 pr_err("gpio: %s has missing PM functions\n",
927 pr_err("gpio: %s has no PM function\n", gc->label);
930 /* gpiochip_add() prints own failure message on error. */
931 ret = gpiochip_add(gc);
933 s3c_gpiolib_track(chip);
936 #if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
937 static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
938 const struct of_phandle_args *gpiospec, u32 *flags)
942 if (WARN_ON(gc->of_gpio_n_cells < 3))
945 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
948 if (gpiospec->args[0] > gc->ngpio)
951 pin = gc->base + gpiospec->args[0];
953 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
954 pr_warn("gpio_xlate: failed to set pin function\n");
955 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
956 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
959 *flags = gpiospec->args[2] >> 16;
961 return gpiospec->args[0];
964 static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
965 { .compatible = "samsung,s3c24xx-gpio", },
969 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
970 u64 base, u64 offset)
972 struct gpio_chip *gc = &chip->chip;
975 if (!of_have_populated_dt())
978 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
979 gc->of_node = of_find_matching_node_by_address(NULL,
980 s3c24xx_gpio_dt_match, address);
982 pr_info("gpio: device tree node not found for gpio controller"
983 " with base address %08llx\n", address);
986 gc->of_gpio_n_cells = 3;
987 gc->of_xlate = s3c24xx_gpio_xlate;
990 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
991 u64 base, u64 offset)
995 #endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
997 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
998 int nr_chips, void __iomem *base)
1001 struct gpio_chip *gc = &chip->chip;
1003 for (i = 0 ; i < nr_chips; i++, chip++) {
1004 /* skip banks not present on SoC */
1005 if (chip->chip.base >= S3C_GPIO_END)
1009 chip->config = &s3c24xx_gpiocfg_default;
1011 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1012 if ((base != NULL) && (chip->base == NULL))
1013 chip->base = base + ((i) * 0x10);
1015 if (!gc->direction_input)
1016 gc->direction_input = samsung_gpiolib_2bit_input;
1017 if (!gc->direction_output)
1018 gc->direction_output = samsung_gpiolib_2bit_output;
1020 samsung_gpiolib_add(chip);
1022 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1026 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1027 int nr_chips, void __iomem *base,
1028 unsigned int offset)
1032 for (i = 0 ; i < nr_chips; i++, chip++) {
1033 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1034 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1037 chip->config = &samsung_gpio_cfgs[7];
1039 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1040 if ((base != NULL) && (chip->base == NULL))
1041 chip->base = base + ((i) * offset);
1043 samsung_gpiolib_add(chip);
1048 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1049 * @chip: The gpio chip that is being configured.
1050 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1052 * This helper deal with the GPIO cases where the control register has 4 bits
1053 * of control per GPIO, generally in the form of:
1056 * others = Special functions (dependent on bank)
1058 * Note, since the code to deal with the case where there are two control
1059 * registers instead of one, we do not have a separate set of function
1060 * (samsung_gpiolib_add_4bit2_chips)for each case.
1063 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1064 int nr_chips, void __iomem *base)
1068 for (i = 0 ; i < nr_chips; i++, chip++) {
1069 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1070 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1073 chip->config = &samsung_gpio_cfgs[2];
1075 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1076 if ((base != NULL) && (chip->base == NULL))
1077 chip->base = base + ((i) * 0x20);
1079 chip->bitmap_gpio_int = 0;
1081 samsung_gpiolib_add(chip);
1085 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1088 for (; nr_chips > 0; nr_chips--, chip++) {
1089 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1090 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1093 chip->config = &samsung_gpio_cfgs[2];
1095 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1097 samsung_gpiolib_add(chip);
1101 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1104 for (; nr_chips > 0; nr_chips--, chip++) {
1105 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1106 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1109 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1111 samsung_gpiolib_add(chip);
1115 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1117 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1119 return samsung_chip->irq_base + offset;
1122 #ifdef CONFIG_PLAT_S3C24XX
1123 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1126 return IRQ_EINT0 + offset;
1129 return IRQ_EINT4 + offset - 4;
1135 #ifdef CONFIG_PLAT_S3C64XX
1136 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1138 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1141 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1143 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1147 struct samsung_gpio_chip s3c24xx_gpios[] = {
1148 #ifdef CONFIG_PLAT_S3C24XX
1150 .config = &s3c24xx_gpiocfg_banka,
1152 .base = S3C2410_GPA(0),
1153 .owner = THIS_MODULE,
1156 .direction_input = s3c24xx_gpiolib_banka_input,
1157 .direction_output = s3c24xx_gpiolib_banka_output,
1161 .base = S3C2410_GPB(0),
1162 .owner = THIS_MODULE,
1168 .base = S3C2410_GPC(0),
1169 .owner = THIS_MODULE,
1175 .base = S3C2410_GPD(0),
1176 .owner = THIS_MODULE,
1182 .base = S3C2410_GPE(0),
1184 .owner = THIS_MODULE,
1189 .base = S3C2410_GPF(0),
1190 .owner = THIS_MODULE,
1193 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1196 .irq_base = IRQ_EINT8,
1198 .base = S3C2410_GPG(0),
1199 .owner = THIS_MODULE,
1202 .to_irq = samsung_gpiolib_to_irq,
1206 .base = S3C2410_GPH(0),
1207 .owner = THIS_MODULE,
1212 /* GPIOS for the S3C2443 and later devices. */
1214 .base = S3C2440_GPJCON,
1216 .base = S3C2410_GPJ(0),
1217 .owner = THIS_MODULE,
1222 .base = S3C2443_GPKCON,
1224 .base = S3C2410_GPK(0),
1225 .owner = THIS_MODULE,
1230 .base = S3C2443_GPLCON,
1232 .base = S3C2410_GPL(0),
1233 .owner = THIS_MODULE,
1238 .base = S3C2443_GPMCON,
1240 .base = S3C2410_GPM(0),
1241 .owner = THIS_MODULE,
1250 * GPIO bank summary:
1252 * Bank GPIOs Style SlpCon ExtInt Group
1258 * F 16 2Bit Yes 4 [1]
1260 * H 10 4Bit[2] Yes 6
1261 * I 16 2Bit Yes None
1262 * J 12 2Bit Yes None
1263 * K 16 4Bit[2] No None
1264 * L 15 4Bit[2] No None
1265 * M 6 4Bit No IRQ_EINT
1266 * N 16 2Bit No IRQ_EINT
1271 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1272 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1275 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1276 #ifdef CONFIG_PLAT_S3C64XX
1279 .base = S3C64XX_GPA(0),
1280 .ngpio = S3C64XX_GPIO_A_NR,
1285 .base = S3C64XX_GPB(0),
1286 .ngpio = S3C64XX_GPIO_B_NR,
1291 .base = S3C64XX_GPC(0),
1292 .ngpio = S3C64XX_GPIO_C_NR,
1297 .base = S3C64XX_GPD(0),
1298 .ngpio = S3C64XX_GPIO_D_NR,
1302 .config = &samsung_gpio_cfgs[0],
1304 .base = S3C64XX_GPE(0),
1305 .ngpio = S3C64XX_GPIO_E_NR,
1309 .base = S3C64XX_GPG_BASE,
1311 .base = S3C64XX_GPG(0),
1312 .ngpio = S3C64XX_GPIO_G_NR,
1316 .base = S3C64XX_GPM_BASE,
1317 .config = &samsung_gpio_cfgs[1],
1319 .base = S3C64XX_GPM(0),
1320 .ngpio = S3C64XX_GPIO_M_NR,
1322 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1328 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1329 #ifdef CONFIG_PLAT_S3C64XX
1331 .base = S3C64XX_GPH_BASE + 0x4,
1333 .base = S3C64XX_GPH(0),
1334 .ngpio = S3C64XX_GPIO_H_NR,
1338 .base = S3C64XX_GPK_BASE + 0x4,
1339 .config = &samsung_gpio_cfgs[0],
1341 .base = S3C64XX_GPK(0),
1342 .ngpio = S3C64XX_GPIO_K_NR,
1346 .base = S3C64XX_GPL_BASE + 0x4,
1347 .config = &samsung_gpio_cfgs[1],
1349 .base = S3C64XX_GPL(0),
1350 .ngpio = S3C64XX_GPIO_L_NR,
1352 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1358 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1359 #ifdef CONFIG_PLAT_S3C64XX
1361 .base = S3C64XX_GPF_BASE,
1362 .config = &samsung_gpio_cfgs[6],
1364 .base = S3C64XX_GPF(0),
1365 .ngpio = S3C64XX_GPIO_F_NR,
1369 .config = &samsung_gpio_cfgs[7],
1371 .base = S3C64XX_GPI(0),
1372 .ngpio = S3C64XX_GPIO_I_NR,
1376 .config = &samsung_gpio_cfgs[7],
1378 .base = S3C64XX_GPJ(0),
1379 .ngpio = S3C64XX_GPIO_J_NR,
1383 .config = &samsung_gpio_cfgs[6],
1385 .base = S3C64XX_GPO(0),
1386 .ngpio = S3C64XX_GPIO_O_NR,
1390 .config = &samsung_gpio_cfgs[6],
1392 .base = S3C64XX_GPP(0),
1393 .ngpio = S3C64XX_GPIO_P_NR,
1397 .config = &samsung_gpio_cfgs[6],
1399 .base = S3C64XX_GPQ(0),
1400 .ngpio = S3C64XX_GPIO_Q_NR,
1404 .base = S3C64XX_GPN_BASE,
1405 .irq_base = IRQ_EINT(0),
1406 .config = &samsung_gpio_cfgs[5],
1408 .base = S3C64XX_GPN(0),
1409 .ngpio = S3C64XX_GPIO_N_NR,
1411 .to_irq = samsung_gpiolib_to_irq,
1418 * S5P6440 GPIO bank summary:
1420 * Bank GPIOs Style SlpCon ExtInt Group
1424 * F 2 2Bit Yes 4 [1]
1426 * H 10 4Bit[2] Yes 6
1427 * I 16 2Bit Yes None
1428 * J 12 2Bit Yes None
1429 * N 16 2Bit No IRQ_EINT
1431 * R 15 4Bit[2] Yes 8
1434 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1435 #ifdef CONFIG_CPU_S5P6440
1438 .base = S5P6440_GPA(0),
1439 .ngpio = S5P6440_GPIO_A_NR,
1444 .base = S5P6440_GPB(0),
1445 .ngpio = S5P6440_GPIO_B_NR,
1450 .base = S5P6440_GPC(0),
1451 .ngpio = S5P6440_GPIO_C_NR,
1455 .base = S5P64X0_GPG_BASE,
1457 .base = S5P6440_GPG(0),
1458 .ngpio = S5P6440_GPIO_G_NR,
1465 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1466 #ifdef CONFIG_CPU_S5P6440
1468 .base = S5P64X0_GPH_BASE + 0x4,
1470 .base = S5P6440_GPH(0),
1471 .ngpio = S5P6440_GPIO_H_NR,
1478 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1479 #ifdef CONFIG_CPU_S5P6440
1481 .base = S5P64X0_GPR_BASE + 0x4,
1482 .config = &s5p64x0_gpio_cfg_rbank,
1484 .base = S5P6440_GPR(0),
1485 .ngpio = S5P6440_GPIO_R_NR,
1492 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1493 #ifdef CONFIG_CPU_S5P6440
1495 .base = S5P64X0_GPF_BASE,
1496 .config = &samsung_gpio_cfgs[6],
1498 .base = S5P6440_GPF(0),
1499 .ngpio = S5P6440_GPIO_F_NR,
1503 .base = S5P64X0_GPI_BASE,
1504 .config = &samsung_gpio_cfgs[4],
1506 .base = S5P6440_GPI(0),
1507 .ngpio = S5P6440_GPIO_I_NR,
1511 .base = S5P64X0_GPJ_BASE,
1512 .config = &samsung_gpio_cfgs[4],
1514 .base = S5P6440_GPJ(0),
1515 .ngpio = S5P6440_GPIO_J_NR,
1519 .base = S5P64X0_GPN_BASE,
1520 .config = &samsung_gpio_cfgs[5],
1522 .base = S5P6440_GPN(0),
1523 .ngpio = S5P6440_GPIO_N_NR,
1527 .base = S5P64X0_GPP_BASE,
1528 .config = &samsung_gpio_cfgs[6],
1530 .base = S5P6440_GPP(0),
1531 .ngpio = S5P6440_GPIO_P_NR,
1539 * S5P6450 GPIO bank summary:
1541 * Bank GPIOs Style SlpCon ExtInt Group
1547 * G 14 4Bit[2] Yes 5
1548 * H 10 4Bit[2] Yes 6
1549 * I 16 2Bit Yes None
1550 * J 12 2Bit Yes None
1552 * N 16 2Bit No IRQ_EINT
1554 * Q 14 2Bit Yes None
1555 * R 15 4Bit[2] Yes None
1558 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1559 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1562 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1563 #ifdef CONFIG_CPU_S5P6450
1566 .base = S5P6450_GPA(0),
1567 .ngpio = S5P6450_GPIO_A_NR,
1572 .base = S5P6450_GPB(0),
1573 .ngpio = S5P6450_GPIO_B_NR,
1578 .base = S5P6450_GPC(0),
1579 .ngpio = S5P6450_GPIO_C_NR,
1584 .base = S5P6450_GPD(0),
1585 .ngpio = S5P6450_GPIO_D_NR,
1589 .base = S5P6450_GPK_BASE,
1591 .base = S5P6450_GPK(0),
1592 .ngpio = S5P6450_GPIO_K_NR,
1599 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1600 #ifdef CONFIG_CPU_S5P6450
1602 .base = S5P64X0_GPG_BASE + 0x4,
1604 .base = S5P6450_GPG(0),
1605 .ngpio = S5P6450_GPIO_G_NR,
1609 .base = S5P64X0_GPH_BASE + 0x4,
1611 .base = S5P6450_GPH(0),
1612 .ngpio = S5P6450_GPIO_H_NR,
1619 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1620 #ifdef CONFIG_CPU_S5P6450
1622 .base = S5P64X0_GPR_BASE + 0x4,
1623 .config = &s5p64x0_gpio_cfg_rbank,
1625 .base = S5P6450_GPR(0),
1626 .ngpio = S5P6450_GPIO_R_NR,
1633 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1634 #ifdef CONFIG_CPU_S5P6450
1636 .base = S5P64X0_GPF_BASE,
1637 .config = &samsung_gpio_cfgs[6],
1639 .base = S5P6450_GPF(0),
1640 .ngpio = S5P6450_GPIO_F_NR,
1644 .base = S5P64X0_GPI_BASE,
1645 .config = &samsung_gpio_cfgs[4],
1647 .base = S5P6450_GPI(0),
1648 .ngpio = S5P6450_GPIO_I_NR,
1652 .base = S5P64X0_GPJ_BASE,
1653 .config = &samsung_gpio_cfgs[4],
1655 .base = S5P6450_GPJ(0),
1656 .ngpio = S5P6450_GPIO_J_NR,
1660 .base = S5P64X0_GPN_BASE,
1661 .config = &samsung_gpio_cfgs[5],
1663 .base = S5P6450_GPN(0),
1664 .ngpio = S5P6450_GPIO_N_NR,
1668 .base = S5P64X0_GPP_BASE,
1669 .config = &samsung_gpio_cfgs[6],
1671 .base = S5P6450_GPP(0),
1672 .ngpio = S5P6450_GPIO_P_NR,
1676 .base = S5P6450_GPQ_BASE,
1677 .config = &samsung_gpio_cfgs[5],
1679 .base = S5P6450_GPQ(0),
1680 .ngpio = S5P6450_GPIO_Q_NR,
1684 .base = S5P6450_GPS_BASE,
1685 .config = &samsung_gpio_cfgs[6],
1687 .base = S5P6450_GPS(0),
1688 .ngpio = S5P6450_GPIO_S_NR,
1696 * S5PC100 GPIO bank summary:
1698 * Bank GPIOs Style INT Type
1699 * A0 8 4Bit GPIO_INT0
1700 * A1 5 4Bit GPIO_INT1
1701 * B 8 4Bit GPIO_INT2
1702 * C 5 4Bit GPIO_INT3
1703 * D 7 4Bit GPIO_INT4
1704 * E0 8 4Bit GPIO_INT5
1705 * E1 6 4Bit GPIO_INT6
1706 * F0 8 4Bit GPIO_INT7
1707 * F1 8 4Bit GPIO_INT8
1708 * F2 8 4Bit GPIO_INT9
1709 * F3 4 4Bit GPIO_INT10
1710 * G0 8 4Bit GPIO_INT11
1711 * G1 3 4Bit GPIO_INT12
1712 * G2 7 4Bit GPIO_INT13
1713 * G3 7 4Bit GPIO_INT14
1714 * H0 8 4Bit WKUP_INT
1715 * H1 8 4Bit WKUP_INT
1716 * H2 8 4Bit WKUP_INT
1717 * H3 8 4Bit WKUP_INT
1718 * I 8 4Bit GPIO_INT15
1719 * J0 8 4Bit GPIO_INT16
1720 * J1 5 4Bit GPIO_INT17
1721 * J2 8 4Bit GPIO_INT18
1722 * J3 8 4Bit GPIO_INT19
1723 * J4 4 4Bit GPIO_INT20
1734 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1735 #ifdef CONFIG_CPU_S5PC100
1738 .base = S5PC100_GPA0(0),
1739 .ngpio = S5PC100_GPIO_A0_NR,
1744 .base = S5PC100_GPA1(0),
1745 .ngpio = S5PC100_GPIO_A1_NR,
1750 .base = S5PC100_GPB(0),
1751 .ngpio = S5PC100_GPIO_B_NR,
1756 .base = S5PC100_GPC(0),
1757 .ngpio = S5PC100_GPIO_C_NR,
1762 .base = S5PC100_GPD(0),
1763 .ngpio = S5PC100_GPIO_D_NR,
1768 .base = S5PC100_GPE0(0),
1769 .ngpio = S5PC100_GPIO_E0_NR,
1774 .base = S5PC100_GPE1(0),
1775 .ngpio = S5PC100_GPIO_E1_NR,
1780 .base = S5PC100_GPF0(0),
1781 .ngpio = S5PC100_GPIO_F0_NR,
1786 .base = S5PC100_GPF1(0),
1787 .ngpio = S5PC100_GPIO_F1_NR,
1792 .base = S5PC100_GPF2(0),
1793 .ngpio = S5PC100_GPIO_F2_NR,
1798 .base = S5PC100_GPF3(0),
1799 .ngpio = S5PC100_GPIO_F3_NR,
1804 .base = S5PC100_GPG0(0),
1805 .ngpio = S5PC100_GPIO_G0_NR,
1810 .base = S5PC100_GPG1(0),
1811 .ngpio = S5PC100_GPIO_G1_NR,
1816 .base = S5PC100_GPG2(0),
1817 .ngpio = S5PC100_GPIO_G2_NR,
1822 .base = S5PC100_GPG3(0),
1823 .ngpio = S5PC100_GPIO_G3_NR,
1828 .base = S5PC100_GPI(0),
1829 .ngpio = S5PC100_GPIO_I_NR,
1834 .base = S5PC100_GPJ0(0),
1835 .ngpio = S5PC100_GPIO_J0_NR,
1840 .base = S5PC100_GPJ1(0),
1841 .ngpio = S5PC100_GPIO_J1_NR,
1846 .base = S5PC100_GPJ2(0),
1847 .ngpio = S5PC100_GPIO_J2_NR,
1852 .base = S5PC100_GPJ3(0),
1853 .ngpio = S5PC100_GPIO_J3_NR,
1858 .base = S5PC100_GPJ4(0),
1859 .ngpio = S5PC100_GPIO_J4_NR,
1864 .base = S5PC100_GPK0(0),
1865 .ngpio = S5PC100_GPIO_K0_NR,
1870 .base = S5PC100_GPK1(0),
1871 .ngpio = S5PC100_GPIO_K1_NR,
1876 .base = S5PC100_GPK2(0),
1877 .ngpio = S5PC100_GPIO_K2_NR,
1882 .base = S5PC100_GPK3(0),
1883 .ngpio = S5PC100_GPIO_K3_NR,
1888 .base = S5PC100_GPL0(0),
1889 .ngpio = S5PC100_GPIO_L0_NR,
1894 .base = S5PC100_GPL1(0),
1895 .ngpio = S5PC100_GPIO_L1_NR,
1900 .base = S5PC100_GPL2(0),
1901 .ngpio = S5PC100_GPIO_L2_NR,
1906 .base = S5PC100_GPL3(0),
1907 .ngpio = S5PC100_GPIO_L3_NR,
1912 .base = S5PC100_GPL4(0),
1913 .ngpio = S5PC100_GPIO_L4_NR,
1917 .base = (S5P_VA_GPIO + 0xC00),
1918 .irq_base = IRQ_EINT(0),
1920 .base = S5PC100_GPH0(0),
1921 .ngpio = S5PC100_GPIO_H0_NR,
1923 .to_irq = samsung_gpiolib_to_irq,
1926 .base = (S5P_VA_GPIO + 0xC20),
1927 .irq_base = IRQ_EINT(8),
1929 .base = S5PC100_GPH1(0),
1930 .ngpio = S5PC100_GPIO_H1_NR,
1932 .to_irq = samsung_gpiolib_to_irq,
1935 .base = (S5P_VA_GPIO + 0xC40),
1936 .irq_base = IRQ_EINT(16),
1938 .base = S5PC100_GPH2(0),
1939 .ngpio = S5PC100_GPIO_H2_NR,
1941 .to_irq = samsung_gpiolib_to_irq,
1944 .base = (S5P_VA_GPIO + 0xC60),
1945 .irq_base = IRQ_EINT(24),
1947 .base = S5PC100_GPH3(0),
1948 .ngpio = S5PC100_GPIO_H3_NR,
1950 .to_irq = samsung_gpiolib_to_irq,
1957 * Followings are the gpio banks in S5PV210/S5PC110
1959 * The 'config' member when left to NULL, is initialized to the default
1960 * structure samsung_gpio_cfgs[3] in the init function below.
1962 * The 'base' member is also initialized in the init function below.
1963 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1964 * uses the above macro and depends on the banks being listed in order here.
1967 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1968 #ifdef CONFIG_CPU_S5PV210
1971 .base = S5PV210_GPA0(0),
1972 .ngpio = S5PV210_GPIO_A0_NR,
1977 .base = S5PV210_GPA1(0),
1978 .ngpio = S5PV210_GPIO_A1_NR,
1983 .base = S5PV210_GPB(0),
1984 .ngpio = S5PV210_GPIO_B_NR,
1989 .base = S5PV210_GPC0(0),
1990 .ngpio = S5PV210_GPIO_C0_NR,
1995 .base = S5PV210_GPC1(0),
1996 .ngpio = S5PV210_GPIO_C1_NR,
2001 .base = S5PV210_GPD0(0),
2002 .ngpio = S5PV210_GPIO_D0_NR,
2007 .base = S5PV210_GPD1(0),
2008 .ngpio = S5PV210_GPIO_D1_NR,
2013 .base = S5PV210_GPE0(0),
2014 .ngpio = S5PV210_GPIO_E0_NR,
2019 .base = S5PV210_GPE1(0),
2020 .ngpio = S5PV210_GPIO_E1_NR,
2025 .base = S5PV210_GPF0(0),
2026 .ngpio = S5PV210_GPIO_F0_NR,
2031 .base = S5PV210_GPF1(0),
2032 .ngpio = S5PV210_GPIO_F1_NR,
2037 .base = S5PV210_GPF2(0),
2038 .ngpio = S5PV210_GPIO_F2_NR,
2043 .base = S5PV210_GPF3(0),
2044 .ngpio = S5PV210_GPIO_F3_NR,
2049 .base = S5PV210_GPG0(0),
2050 .ngpio = S5PV210_GPIO_G0_NR,
2055 .base = S5PV210_GPG1(0),
2056 .ngpio = S5PV210_GPIO_G1_NR,
2061 .base = S5PV210_GPG2(0),
2062 .ngpio = S5PV210_GPIO_G2_NR,
2067 .base = S5PV210_GPG3(0),
2068 .ngpio = S5PV210_GPIO_G3_NR,
2073 .base = S5PV210_GPI(0),
2074 .ngpio = S5PV210_GPIO_I_NR,
2079 .base = S5PV210_GPJ0(0),
2080 .ngpio = S5PV210_GPIO_J0_NR,
2085 .base = S5PV210_GPJ1(0),
2086 .ngpio = S5PV210_GPIO_J1_NR,
2091 .base = S5PV210_GPJ2(0),
2092 .ngpio = S5PV210_GPIO_J2_NR,
2097 .base = S5PV210_GPJ3(0),
2098 .ngpio = S5PV210_GPIO_J3_NR,
2103 .base = S5PV210_GPJ4(0),
2104 .ngpio = S5PV210_GPIO_J4_NR,
2109 .base = S5PV210_MP01(0),
2110 .ngpio = S5PV210_GPIO_MP01_NR,
2115 .base = S5PV210_MP02(0),
2116 .ngpio = S5PV210_GPIO_MP02_NR,
2121 .base = S5PV210_MP03(0),
2122 .ngpio = S5PV210_GPIO_MP03_NR,
2127 .base = S5PV210_MP04(0),
2128 .ngpio = S5PV210_GPIO_MP04_NR,
2133 .base = S5PV210_MP05(0),
2134 .ngpio = S5PV210_GPIO_MP05_NR,
2138 .base = (S5P_VA_GPIO + 0xC00),
2139 .irq_base = IRQ_EINT(0),
2141 .base = S5PV210_GPH0(0),
2142 .ngpio = S5PV210_GPIO_H0_NR,
2144 .to_irq = samsung_gpiolib_to_irq,
2147 .base = (S5P_VA_GPIO + 0xC20),
2148 .irq_base = IRQ_EINT(8),
2150 .base = S5PV210_GPH1(0),
2151 .ngpio = S5PV210_GPIO_H1_NR,
2153 .to_irq = samsung_gpiolib_to_irq,
2156 .base = (S5P_VA_GPIO + 0xC40),
2157 .irq_base = IRQ_EINT(16),
2159 .base = S5PV210_GPH2(0),
2160 .ngpio = S5PV210_GPIO_H2_NR,
2162 .to_irq = samsung_gpiolib_to_irq,
2165 .base = (S5P_VA_GPIO + 0xC60),
2166 .irq_base = IRQ_EINT(24),
2168 .base = S5PV210_GPH3(0),
2169 .ngpio = S5PV210_GPIO_H3_NR,
2171 .to_irq = samsung_gpiolib_to_irq,
2178 * Followings are the gpio banks in EXYNOS SoCs
2180 * The 'config' member when left to NULL, is initialized to the default
2181 * structure exynos_gpio_cfg in the init function below.
2183 * The 'base' member is also initialized in the init function below.
2184 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2185 * uses the above macro and depends on the banks being listed in order here.
2188 #ifdef CONFIG_ARCH_EXYNOS4
2189 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2192 .base = EXYNOS4_GPA0(0),
2193 .ngpio = EXYNOS4_GPIO_A0_NR,
2198 .base = EXYNOS4_GPA1(0),
2199 .ngpio = EXYNOS4_GPIO_A1_NR,
2204 .base = EXYNOS4_GPB(0),
2205 .ngpio = EXYNOS4_GPIO_B_NR,
2210 .base = EXYNOS4_GPC0(0),
2211 .ngpio = EXYNOS4_GPIO_C0_NR,
2216 .base = EXYNOS4_GPC1(0),
2217 .ngpio = EXYNOS4_GPIO_C1_NR,
2222 .base = EXYNOS4_GPD0(0),
2223 .ngpio = EXYNOS4_GPIO_D0_NR,
2228 .base = EXYNOS4_GPD1(0),
2229 .ngpio = EXYNOS4_GPIO_D1_NR,
2234 .base = EXYNOS4_GPE0(0),
2235 .ngpio = EXYNOS4_GPIO_E0_NR,
2240 .base = EXYNOS4_GPE1(0),
2241 .ngpio = EXYNOS4_GPIO_E1_NR,
2246 .base = EXYNOS4_GPE2(0),
2247 .ngpio = EXYNOS4_GPIO_E2_NR,
2252 .base = EXYNOS4_GPE3(0),
2253 .ngpio = EXYNOS4_GPIO_E3_NR,
2258 .base = EXYNOS4_GPE4(0),
2259 .ngpio = EXYNOS4_GPIO_E4_NR,
2264 .base = EXYNOS4_GPF0(0),
2265 .ngpio = EXYNOS4_GPIO_F0_NR,
2270 .base = EXYNOS4_GPF1(0),
2271 .ngpio = EXYNOS4_GPIO_F1_NR,
2276 .base = EXYNOS4_GPF2(0),
2277 .ngpio = EXYNOS4_GPIO_F2_NR,
2282 .base = EXYNOS4_GPF3(0),
2283 .ngpio = EXYNOS4_GPIO_F3_NR,
2290 #ifdef CONFIG_ARCH_EXYNOS4
2291 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2294 .base = EXYNOS4_GPJ0(0),
2295 .ngpio = EXYNOS4_GPIO_J0_NR,
2300 .base = EXYNOS4_GPJ1(0),
2301 .ngpio = EXYNOS4_GPIO_J1_NR,
2306 .base = EXYNOS4_GPK0(0),
2307 .ngpio = EXYNOS4_GPIO_K0_NR,
2312 .base = EXYNOS4_GPK1(0),
2313 .ngpio = EXYNOS4_GPIO_K1_NR,
2318 .base = EXYNOS4_GPK2(0),
2319 .ngpio = EXYNOS4_GPIO_K2_NR,
2324 .base = EXYNOS4_GPK3(0),
2325 .ngpio = EXYNOS4_GPIO_K3_NR,
2330 .base = EXYNOS4_GPL0(0),
2331 .ngpio = EXYNOS4_GPIO_L0_NR,
2336 .base = EXYNOS4_GPL1(0),
2337 .ngpio = EXYNOS4_GPIO_L1_NR,
2342 .base = EXYNOS4_GPL2(0),
2343 .ngpio = EXYNOS4_GPIO_L2_NR,
2347 .config = &samsung_gpio_cfgs[8],
2349 .base = EXYNOS4_GPY0(0),
2350 .ngpio = EXYNOS4_GPIO_Y0_NR,
2354 .config = &samsung_gpio_cfgs[8],
2356 .base = EXYNOS4_GPY1(0),
2357 .ngpio = EXYNOS4_GPIO_Y1_NR,
2361 .config = &samsung_gpio_cfgs[8],
2363 .base = EXYNOS4_GPY2(0),
2364 .ngpio = EXYNOS4_GPIO_Y2_NR,
2368 .config = &samsung_gpio_cfgs[8],
2370 .base = EXYNOS4_GPY3(0),
2371 .ngpio = EXYNOS4_GPIO_Y3_NR,
2375 .config = &samsung_gpio_cfgs[8],
2377 .base = EXYNOS4_GPY4(0),
2378 .ngpio = EXYNOS4_GPIO_Y4_NR,
2382 .config = &samsung_gpio_cfgs[8],
2384 .base = EXYNOS4_GPY5(0),
2385 .ngpio = EXYNOS4_GPIO_Y5_NR,
2389 .config = &samsung_gpio_cfgs[8],
2391 .base = EXYNOS4_GPY6(0),
2392 .ngpio = EXYNOS4_GPIO_Y6_NR,
2396 .config = &samsung_gpio_cfgs[9],
2397 .irq_base = IRQ_EINT(0),
2399 .base = EXYNOS4_GPX0(0),
2400 .ngpio = EXYNOS4_GPIO_X0_NR,
2402 .to_irq = samsung_gpiolib_to_irq,
2405 .config = &samsung_gpio_cfgs[9],
2406 .irq_base = IRQ_EINT(8),
2408 .base = EXYNOS4_GPX1(0),
2409 .ngpio = EXYNOS4_GPIO_X1_NR,
2411 .to_irq = samsung_gpiolib_to_irq,
2414 .config = &samsung_gpio_cfgs[9],
2415 .irq_base = IRQ_EINT(16),
2417 .base = EXYNOS4_GPX2(0),
2418 .ngpio = EXYNOS4_GPIO_X2_NR,
2420 .to_irq = samsung_gpiolib_to_irq,
2423 .config = &samsung_gpio_cfgs[9],
2424 .irq_base = IRQ_EINT(24),
2426 .base = EXYNOS4_GPX3(0),
2427 .ngpio = EXYNOS4_GPIO_X3_NR,
2429 .to_irq = samsung_gpiolib_to_irq,
2435 #ifdef CONFIG_ARCH_EXYNOS4
2436 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2439 .base = EXYNOS4_GPZ(0),
2440 .ngpio = EXYNOS4_GPIO_Z_NR,
2447 #ifdef CONFIG_SOC_EXYNOS5250
2448 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2451 .base = EXYNOS5_GPA0(0),
2452 .ngpio = EXYNOS5_GPIO_A0_NR,
2457 .base = EXYNOS5_GPA1(0),
2458 .ngpio = EXYNOS5_GPIO_A1_NR,
2463 .base = EXYNOS5_GPA2(0),
2464 .ngpio = EXYNOS5_GPIO_A2_NR,
2469 .base = EXYNOS5_GPB0(0),
2470 .ngpio = EXYNOS5_GPIO_B0_NR,
2475 .base = EXYNOS5_GPB1(0),
2476 .ngpio = EXYNOS5_GPIO_B1_NR,
2481 .base = EXYNOS5_GPB2(0),
2482 .ngpio = EXYNOS5_GPIO_B2_NR,
2487 .base = EXYNOS5_GPB3(0),
2488 .ngpio = EXYNOS5_GPIO_B3_NR,
2493 .base = EXYNOS5_GPC0(0),
2494 .ngpio = EXYNOS5_GPIO_C0_NR,
2499 .base = EXYNOS5_GPC1(0),
2500 .ngpio = EXYNOS5_GPIO_C1_NR,
2505 .base = EXYNOS5_GPC2(0),
2506 .ngpio = EXYNOS5_GPIO_C2_NR,
2511 .base = EXYNOS5_GPC3(0),
2512 .ngpio = EXYNOS5_GPIO_C3_NR,
2517 .base = EXYNOS5_GPD0(0),
2518 .ngpio = EXYNOS5_GPIO_D0_NR,
2523 .base = EXYNOS5_GPD1(0),
2524 .ngpio = EXYNOS5_GPIO_D1_NR,
2529 .base = EXYNOS5_GPY0(0),
2530 .ngpio = EXYNOS5_GPIO_Y0_NR,
2535 .base = EXYNOS5_GPY1(0),
2536 .ngpio = EXYNOS5_GPIO_Y1_NR,
2541 .base = EXYNOS5_GPY2(0),
2542 .ngpio = EXYNOS5_GPIO_Y2_NR,
2547 .base = EXYNOS5_GPY3(0),
2548 .ngpio = EXYNOS5_GPIO_Y3_NR,
2553 .base = EXYNOS5_GPY4(0),
2554 .ngpio = EXYNOS5_GPIO_Y4_NR,
2559 .base = EXYNOS5_GPY5(0),
2560 .ngpio = EXYNOS5_GPIO_Y5_NR,
2565 .base = EXYNOS5_GPY6(0),
2566 .ngpio = EXYNOS5_GPIO_Y6_NR,
2571 .base = EXYNOS5_GPC4(0),
2572 .ngpio = EXYNOS5_GPIO_C4_NR,
2576 .config = &samsung_gpio_cfgs[9],
2577 .irq_base = IRQ_EINT(0),
2579 .base = EXYNOS5_GPX0(0),
2580 .ngpio = EXYNOS5_GPIO_X0_NR,
2582 .to_irq = samsung_gpiolib_to_irq,
2585 .config = &samsung_gpio_cfgs[9],
2586 .irq_base = IRQ_EINT(8),
2588 .base = EXYNOS5_GPX1(0),
2589 .ngpio = EXYNOS5_GPIO_X1_NR,
2591 .to_irq = samsung_gpiolib_to_irq,
2594 .config = &samsung_gpio_cfgs[9],
2595 .irq_base = IRQ_EINT(16),
2597 .base = EXYNOS5_GPX2(0),
2598 .ngpio = EXYNOS5_GPIO_X2_NR,
2600 .to_irq = samsung_gpiolib_to_irq,
2603 .config = &samsung_gpio_cfgs[9],
2604 .irq_base = IRQ_EINT(24),
2606 .base = EXYNOS5_GPX3(0),
2607 .ngpio = EXYNOS5_GPIO_X3_NR,
2609 .to_irq = samsung_gpiolib_to_irq,
2615 #ifdef CONFIG_SOC_EXYNOS5250
2616 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2619 .base = EXYNOS5_GPE0(0),
2620 .ngpio = EXYNOS5_GPIO_E0_NR,
2625 .base = EXYNOS5_GPE1(0),
2626 .ngpio = EXYNOS5_GPIO_E1_NR,
2631 .base = EXYNOS5_GPF0(0),
2632 .ngpio = EXYNOS5_GPIO_F0_NR,
2637 .base = EXYNOS5_GPF1(0),
2638 .ngpio = EXYNOS5_GPIO_F1_NR,
2643 .base = EXYNOS5_GPG0(0),
2644 .ngpio = EXYNOS5_GPIO_G0_NR,
2649 .base = EXYNOS5_GPG1(0),
2650 .ngpio = EXYNOS5_GPIO_G1_NR,
2655 .base = EXYNOS5_GPG2(0),
2656 .ngpio = EXYNOS5_GPIO_G2_NR,
2661 .base = EXYNOS5_GPH0(0),
2662 .ngpio = EXYNOS5_GPIO_H0_NR,
2667 .base = EXYNOS5_GPH1(0),
2668 .ngpio = EXYNOS5_GPIO_H1_NR,
2676 #ifdef CONFIG_SOC_EXYNOS5250
2677 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2680 .base = EXYNOS5_GPV0(0),
2681 .ngpio = EXYNOS5_GPIO_V0_NR,
2686 .base = EXYNOS5_GPV1(0),
2687 .ngpio = EXYNOS5_GPIO_V1_NR,
2692 .base = EXYNOS5_GPV2(0),
2693 .ngpio = EXYNOS5_GPIO_V2_NR,
2698 .base = EXYNOS5_GPV3(0),
2699 .ngpio = EXYNOS5_GPIO_V3_NR,
2704 .base = EXYNOS5_GPV4(0),
2705 .ngpio = EXYNOS5_GPIO_V4_NR,
2712 #ifdef CONFIG_SOC_EXYNOS5250
2713 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2716 .base = EXYNOS5_GPZ(0),
2717 .ngpio = EXYNOS5_GPIO_Z_NR,
2725 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2726 static int exynos_gpio_xlate(struct gpio_chip *gc,
2727 const struct of_phandle_args *gpiospec, u32 *flags)
2731 if (WARN_ON(gc->of_gpio_n_cells < 4))
2734 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2737 if (gpiospec->args[0] > gc->ngpio)
2740 pin = gc->base + gpiospec->args[0];
2742 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2743 pr_warn("gpio_xlate: failed to set pin function\n");
2744 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2745 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2746 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2747 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2750 *flags = gpiospec->args[2] >> 16;
2752 return gpiospec->args[0];
2755 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2756 { .compatible = "samsung,exynos4-gpio", },
2760 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2761 u64 base, u64 offset)
2763 struct gpio_chip *gc = &chip->chip;
2766 if (!of_have_populated_dt())
2769 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2770 gc->of_node = of_find_matching_node_by_address(NULL,
2771 exynos_gpio_dt_match, address);
2773 pr_info("gpio: device tree node not found for gpio controller"
2774 " with base address %08llx\n", address);
2777 gc->of_gpio_n_cells = 4;
2778 gc->of_xlate = exynos_gpio_xlate;
2780 #elif defined(CONFIG_ARCH_EXYNOS)
2781 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2782 u64 base, u64 offset)
2786 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2788 static __init void exynos4_gpiolib_init(void)
2790 #ifdef CONFIG_CPU_EXYNOS4210
2791 struct samsung_gpio_chip *chip;
2793 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2795 void __iomem *gpx_base;
2798 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2799 if (gpio_base1 == NULL) {
2800 pr_err("unable to ioremap for gpio_base1\n");
2804 chip = exynos4_gpios_1;
2805 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2807 for (i = 0; i < nr_chips; i++, chip++) {
2808 if (!chip->config) {
2809 chip->config = &exynos_gpio_cfg;
2810 chip->group = group++;
2812 exynos_gpiolib_attach_ofnode(chip,
2813 EXYNOS4_PA_GPIO1, i * 0x20);
2815 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2816 nr_chips, gpio_base1);
2819 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2820 if (gpio_base2 == NULL) {
2821 pr_err("unable to ioremap for gpio_base2\n");
2825 /* need to set base address for gpx */
2826 chip = &exynos4_gpios_2[16];
2827 gpx_base = gpio_base2 + 0xC00;
2828 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2829 chip->base = gpx_base;
2831 chip = exynos4_gpios_2;
2832 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2834 for (i = 0; i < nr_chips; i++, chip++) {
2835 if (!chip->config) {
2836 chip->config = &exynos_gpio_cfg;
2837 chip->group = group++;
2839 exynos_gpiolib_attach_ofnode(chip,
2840 EXYNOS4_PA_GPIO2, i * 0x20);
2842 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2843 nr_chips, gpio_base2);
2846 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2847 if (gpio_base3 == NULL) {
2848 pr_err("unable to ioremap for gpio_base3\n");
2852 chip = exynos4_gpios_3;
2853 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2855 for (i = 0; i < nr_chips; i++, chip++) {
2856 if (!chip->config) {
2857 chip->config = &exynos_gpio_cfg;
2858 chip->group = group++;
2860 exynos_gpiolib_attach_ofnode(chip,
2861 EXYNOS4_PA_GPIO3, i * 0x20);
2863 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2864 nr_chips, gpio_base3);
2866 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2867 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2868 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2874 iounmap(gpio_base2);
2876 iounmap(gpio_base1);
2879 #endif /* CONFIG_CPU_EXYNOS4210 */
2882 static __init void exynos5_gpiolib_init(void)
2884 #ifdef CONFIG_SOC_EXYNOS5250
2885 struct samsung_gpio_chip *chip;
2887 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2889 void __iomem *gpx_base;
2892 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2893 if (gpio_base1 == NULL) {
2894 pr_err("unable to ioremap for gpio_base1\n");
2898 /* need to set base address for gpc4 */
2899 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2901 /* need to set base address for gpx */
2902 chip = &exynos5_gpios_1[21];
2903 gpx_base = gpio_base1 + 0xC00;
2904 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2905 chip->base = gpx_base;
2907 chip = exynos5_gpios_1;
2908 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2910 for (i = 0; i < nr_chips; i++, chip++) {
2911 if (!chip->config) {
2912 chip->config = &exynos_gpio_cfg;
2913 chip->group = group++;
2915 exynos_gpiolib_attach_ofnode(chip,
2916 EXYNOS5_PA_GPIO1, i * 0x20);
2918 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2919 nr_chips, gpio_base1);
2922 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2923 if (gpio_base2 == NULL) {
2924 pr_err("unable to ioremap for gpio_base2\n");
2928 chip = exynos5_gpios_2;
2929 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2931 for (i = 0; i < nr_chips; i++, chip++) {
2932 if (!chip->config) {
2933 chip->config = &exynos_gpio_cfg;
2934 chip->group = group++;
2936 exynos_gpiolib_attach_ofnode(chip,
2937 EXYNOS5_PA_GPIO2, i * 0x20);
2939 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2940 nr_chips, gpio_base2);
2943 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2944 if (gpio_base3 == NULL) {
2945 pr_err("unable to ioremap for gpio_base3\n");
2949 /* need to set base address for gpv */
2950 exynos5_gpios_3[0].base = gpio_base3;
2951 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2952 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2953 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2954 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2956 chip = exynos5_gpios_3;
2957 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2959 for (i = 0; i < nr_chips; i++, chip++) {
2960 if (!chip->config) {
2961 chip->config = &exynos_gpio_cfg;
2962 chip->group = group++;
2964 exynos_gpiolib_attach_ofnode(chip,
2965 EXYNOS5_PA_GPIO3, i * 0x20);
2967 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2968 nr_chips, gpio_base3);
2971 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2972 if (gpio_base4 == NULL) {
2973 pr_err("unable to ioremap for gpio_base4\n");
2977 chip = exynos5_gpios_4;
2978 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2980 for (i = 0; i < nr_chips; i++, chip++) {
2981 if (!chip->config) {
2982 chip->config = &exynos_gpio_cfg;
2983 chip->group = group++;
2985 exynos_gpiolib_attach_ofnode(chip,
2986 EXYNOS5_PA_GPIO4, i * 0x20);
2988 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2989 nr_chips, gpio_base4);
2993 iounmap(gpio_base3);
2995 iounmap(gpio_base2);
2997 iounmap(gpio_base1);
3001 #endif /* CONFIG_SOC_EXYNOS5250 */
3004 /* TODO: cleanup soc_is_* */
3005 static __init int samsung_gpiolib_init(void)
3007 struct samsung_gpio_chip *chip;
3011 #if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
3013 * This gpio driver includes support for device tree support and there
3014 * are platforms using it. In order to maintain compatibility with those
3015 * platforms, and to allow non-dt Exynos4210 platforms to use this
3016 * gpiolib support, a check is added to find out if there is a active
3017 * pin-controller driver support available. If it is available, this
3018 * gpiolib support is ignored and the gpiolib support available in
3019 * pin-controller driver is used. This is a temporary check and will go
3020 * away when all of the Exynos4210 platforms have switched to using
3021 * device tree and the pin-ctrl driver.
3023 struct device_node *pctrl_np;
3024 static const struct of_device_id exynos_pinctrl_ids[] = {
3025 { .compatible = "samsung,exynos4210-pinctrl", },
3026 { .compatible = "samsung,exynos4x12-pinctrl", },
3027 { .compatible = "samsung,exynos5250-pinctrl", },
3028 { .compatible = "samsung,exynos5440-pinctrl", },
3030 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3031 if (pctrl_np && of_device_is_available(pctrl_np))
3035 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3037 if (soc_is_s3c24xx()) {
3038 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3039 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3040 } else if (soc_is_s3c64xx()) {
3041 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3042 ARRAY_SIZE(s3c64xx_gpios_2bit),
3043 S3C64XX_VA_GPIO + 0xE0, 0x20);
3044 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3045 ARRAY_SIZE(s3c64xx_gpios_4bit),
3047 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3048 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3049 } else if (soc_is_s5p6440()) {
3050 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3051 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3052 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3053 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3054 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3055 ARRAY_SIZE(s5p6440_gpios_4bit2));
3056 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3057 ARRAY_SIZE(s5p6440_gpios_rbank));
3058 } else if (soc_is_s5p6450()) {
3059 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3060 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3061 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3062 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3063 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3064 ARRAY_SIZE(s5p6450_gpios_4bit2));
3065 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3066 ARRAY_SIZE(s5p6450_gpios_rbank));
3067 } else if (soc_is_s5pc100()) {
3069 chip = s5pc100_gpios_4bit;
3070 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3072 for (i = 0; i < nr_chips; i++, chip++) {
3073 if (!chip->config) {
3074 chip->config = &samsung_gpio_cfgs[3];
3075 chip->group = group++;
3078 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3079 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3080 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3082 } else if (soc_is_s5pv210()) {
3084 chip = s5pv210_gpios_4bit;
3085 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3087 for (i = 0; i < nr_chips; i++, chip++) {
3088 if (!chip->config) {
3089 chip->config = &samsung_gpio_cfgs[3];
3090 chip->group = group++;
3093 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3094 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3095 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3097 } else if (soc_is_exynos4210()) {
3098 exynos4_gpiolib_init();
3099 } else if (soc_is_exynos5250()) {
3100 exynos5_gpiolib_init();
3102 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3108 core_initcall(samsung_gpiolib_init);
3110 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3112 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3113 unsigned long flags;
3120 offset = pin - chip->chip.base;
3122 samsung_gpio_lock(chip, flags);
3123 ret = samsung_gpio_do_setcfg(chip, offset, config);
3124 samsung_gpio_unlock(chip, flags);
3128 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3130 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3135 for (; nr > 0; nr--, start++) {
3136 ret = s3c_gpio_cfgpin(start, cfg);
3143 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3145 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3146 unsigned int cfg, samsung_gpio_pull_t pull)
3150 for (; nr > 0; nr--, start++) {
3151 s3c_gpio_setpull(start, pull);
3152 ret = s3c_gpio_cfgpin(start, cfg);
3159 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3161 unsigned s3c_gpio_getcfg(unsigned int pin)
3163 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3164 unsigned long flags;
3169 offset = pin - chip->chip.base;
3171 samsung_gpio_lock(chip, flags);
3172 ret = samsung_gpio_do_getcfg(chip, offset);
3173 samsung_gpio_unlock(chip, flags);
3178 EXPORT_SYMBOL(s3c_gpio_getcfg);
3180 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3182 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3183 unsigned long flags;
3189 offset = pin - chip->chip.base;
3191 samsung_gpio_lock(chip, flags);
3192 ret = samsung_gpio_do_setpull(chip, offset, pull);
3193 samsung_gpio_unlock(chip, flags);
3197 EXPORT_SYMBOL(s3c_gpio_setpull);
3199 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3201 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3202 unsigned long flags;
3207 offset = pin - chip->chip.base;
3209 samsung_gpio_lock(chip, flags);
3210 pup = samsung_gpio_do_getpull(chip, offset);
3211 samsung_gpio_unlock(chip, flags);
3214 return (__force samsung_gpio_pull_t)pup;
3216 EXPORT_SYMBOL(s3c_gpio_getpull);
3218 #ifdef CONFIG_S5P_GPIO_DRVSTR
3219 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3221 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3230 off = pin - chip->chip.base;
3232 reg = chip->base + 0x0C;
3234 drvstr = __raw_readl(reg);
3235 drvstr = drvstr >> shift;
3238 return (__force s5p_gpio_drvstr_t)drvstr;
3240 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3242 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3244 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3253 off = pin - chip->chip.base;
3255 reg = chip->base + 0x0C;
3257 tmp = __raw_readl(reg);
3258 tmp &= ~(0x3 << shift);
3259 tmp |= drvstr << shift;
3261 __raw_writel(tmp, reg);
3265 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3266 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3268 #ifdef CONFIG_PLAT_S3C24XX
3269 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3271 unsigned long flags;
3272 unsigned long misccr;
3274 local_irq_save(flags);
3275 misccr = __raw_readl(S3C24XX_MISCCR);
3278 __raw_writel(misccr, S3C24XX_MISCCR);
3279 local_irq_restore(flags);
3283 EXPORT_SYMBOL(s3c2410_modify_misccr);