2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
30 #include <mach/hardware.h>
32 #include <mach/regs-clock.h>
33 #include <mach/regs-gpio.h>
36 #include <plat/gpio-core.h>
37 #include <plat/gpio-cfg.h>
38 #include <plat/gpio-cfg-helpers.h>
39 #include <plat/gpio-fns.h>
43 #define gpio_dbg(x...) do { } while (0)
45 #define gpio_dbg(x...) printk(KERN_DEBUG x)
48 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
49 unsigned int off, samsung_gpio_pull_t pull)
51 void __iomem *reg = chip->base + 0x08;
55 pup = __raw_readl(reg);
58 __raw_writel(pup, reg);
63 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
66 void __iomem *reg = chip->base + 0x08;
68 u32 pup = __raw_readl(reg);
73 return (__force samsung_gpio_pull_t)pup;
76 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
77 unsigned int off, samsung_gpio_pull_t pull)
80 case S3C_GPIO_PULL_NONE:
83 case S3C_GPIO_PULL_UP:
86 case S3C_GPIO_PULL_DOWN:
90 return samsung_gpio_setpull_updown(chip, off, pull);
93 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
96 samsung_gpio_pull_t pull;
98 pull = samsung_gpio_getpull_updown(chip, off);
102 pull = S3C_GPIO_PULL_UP;
106 pull = S3C_GPIO_PULL_NONE;
109 pull = S3C_GPIO_PULL_DOWN;
116 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
117 unsigned int off, samsung_gpio_pull_t pull,
118 samsung_gpio_pull_t updown)
120 void __iomem *reg = chip->base + 0x08;
121 u32 pup = __raw_readl(reg);
125 else if (pull == S3C_GPIO_PULL_NONE)
130 __raw_writel(pup, reg);
134 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
136 samsung_gpio_pull_t updown)
138 void __iomem *reg = chip->base + 0x08;
139 u32 pup = __raw_readl(reg);
142 return pup ? S3C_GPIO_PULL_NONE : updown;
145 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
148 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
151 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
152 unsigned int off, samsung_gpio_pull_t pull)
154 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
157 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
160 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
163 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
164 unsigned int off, samsung_gpio_pull_t pull)
166 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
169 static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip,
170 unsigned int off, samsung_gpio_pull_t pull)
172 if (pull == S3C_GPIO_PULL_UP)
175 return samsung_gpio_setpull_updown(chip, off, pull);
178 static samsung_gpio_pull_t exynos4_gpio_getpull(struct samsung_gpio_chip *chip,
181 samsung_gpio_pull_t pull;
183 pull = samsung_gpio_getpull_updown(chip, off);
186 pull = S3C_GPIO_PULL_UP;
192 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
193 * @chip: The gpio chip that is being configured.
194 * @off: The offset for the GPIO being configured.
195 * @cfg: The configuration value to set.
197 * This helper deal with the GPIO cases where the control register
198 * has two bits of configuration per gpio, which have the following
202 * 1x = special function
205 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
206 unsigned int off, unsigned int cfg)
208 void __iomem *reg = chip->base;
209 unsigned int shift = off * 2;
212 if (samsung_gpio_is_cfg_special(cfg)) {
220 con = __raw_readl(reg);
221 con &= ~(0x3 << shift);
223 __raw_writel(con, reg);
229 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
230 * @chip: The gpio chip that is being configured.
231 * @off: The offset for the GPIO being configured.
233 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value whicg
234 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
235 * S3C_GPIO_SPECIAL() macro.
238 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
243 con = __raw_readl(chip->base);
247 /* this conversion works for IN and OUT as well as special mode */
248 return S3C_GPIO_SPECIAL(con);
252 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
253 * @chip: The gpio chip that is being configured.
254 * @off: The offset for the GPIO being configured.
255 * @cfg: The configuration value to set.
257 * This helper deal with the GPIO cases where the control register has 4 bits
258 * of control per GPIO, generally in the form of:
261 * others = Special functions (dependent on bank)
263 * Note, since the code to deal with the case where there are two control
264 * registers instead of one, we do not have a separate set of functions for
268 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
269 unsigned int off, unsigned int cfg)
271 void __iomem *reg = chip->base;
272 unsigned int shift = (off & 7) * 4;
275 if (off < 8 && chip->chip.ngpio > 8)
278 if (samsung_gpio_is_cfg_special(cfg)) {
283 con = __raw_readl(reg);
284 con &= ~(0xf << shift);
286 __raw_writel(con, reg);
292 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
293 * @chip: The gpio chip that is being configured.
294 * @off: The offset for the GPIO being configured.
296 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
297 * register setting into a value the software can use, such as could be passed
298 * to samsung_gpio_setcfg_4bit().
300 * @sa samsung_gpio_getcfg_2bit
303 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
306 void __iomem *reg = chip->base;
307 unsigned int shift = (off & 7) * 4;
310 if (off < 8 && chip->chip.ngpio > 8)
313 con = __raw_readl(reg);
317 /* this conversion works for IN and OUT as well as special mode */
318 return S3C_GPIO_SPECIAL(con);
322 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
323 * @chip: The gpio chip that is being configured.
324 * @off: The offset for the GPIO being configured.
325 * @cfg: The configuration value to set.
327 * This helper deal with the GPIO cases where the control register
328 * has one bit of configuration for the gpio, where setting the bit
329 * means the pin is in special function mode and unset means output.
332 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
333 unsigned int off, unsigned int cfg)
335 void __iomem *reg = chip->base;
336 unsigned int shift = off;
339 if (samsung_gpio_is_cfg_special(cfg)) {
342 /* Map output to 0, and SFN2 to 1 */
350 con = __raw_readl(reg);
351 con &= ~(0x1 << shift);
353 __raw_writel(con, reg);
359 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
360 * @chip: The gpio chip that is being configured.
361 * @off: The offset for the GPIO being configured.
363 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
364 * GPIO configuration value.
366 * @sa samsung_gpio_getcfg_2bit
367 * @sa samsung_gpio_getcfg_4bit
370 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
375 con = __raw_readl(chip->base);
380 return S3C_GPIO_SFN(con);
383 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
384 unsigned int off, unsigned int cfg)
386 void __iomem *reg = chip->base;
397 shift = (off & 7) * 4;
401 shift = ((off + 1) & 7) * 4;
404 shift = ((off + 1) & 7) * 4;
408 if (samsung_gpio_is_cfg_special(cfg)) {
413 con = __raw_readl(reg);
414 con &= ~(0xf << shift);
416 __raw_writel(con, reg);
421 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
424 for (; nr_chips > 0; nr_chips--, chipcfg++) {
425 if (!chipcfg->set_config)
426 chipcfg->set_config = samsung_gpio_setcfg_4bit;
427 if (!chipcfg->get_config)
428 chipcfg->get_config = samsung_gpio_getcfg_4bit;
429 if (!chipcfg->set_pull)
430 chipcfg->set_pull = samsung_gpio_setpull_updown;
431 if (!chipcfg->get_pull)
432 chipcfg->get_pull = samsung_gpio_getpull_updown;
436 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
437 .set_config = samsung_gpio_setcfg_2bit,
438 .get_config = samsung_gpio_getcfg_2bit,
441 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
442 .set_config = s3c24xx_gpio_setcfg_abank,
443 .get_config = s3c24xx_gpio_getcfg_abank,
446 static struct samsung_gpio_cfg exynos4_gpio_cfg = {
447 .set_pull = exynos4_gpio_setpull,
448 .get_pull = exynos4_gpio_getpull,
449 .set_config = samsung_gpio_setcfg_4bit,
450 .get_config = samsung_gpio_getcfg_4bit,
453 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
455 .set_config = s5p64x0_gpio_setcfg_rbank,
456 .get_config = samsung_gpio_getcfg_4bit,
457 .set_pull = samsung_gpio_setpull_updown,
458 .get_pull = samsung_gpio_getpull_updown,
461 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
472 .set_config = samsung_gpio_setcfg_2bit,
473 .get_config = samsung_gpio_getcfg_2bit,
476 .set_config = samsung_gpio_setcfg_2bit,
477 .get_config = samsung_gpio_getcfg_2bit,
480 .set_config = samsung_gpio_setcfg_2bit,
481 .get_config = samsung_gpio_getcfg_2bit,
483 .set_config = samsung_gpio_setcfg_2bit,
484 .get_config = samsung_gpio_getcfg_2bit,
489 * Default routines for controlling GPIO, based on the original S3C24XX
490 * GPIO functions which deal with the case where each gpio bank of the
491 * chip is as following:
493 * base + 0x00: Control register, 2 bits per gpio
494 * gpio n: 2 bits starting at (2*n)
495 * 00 = input, 01 = output, others mean special-function
496 * base + 0x04: Data register, 1 bit per gpio
500 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
502 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
503 void __iomem *base = ourchip->base;
507 samsung_gpio_lock(ourchip, flags);
509 con = __raw_readl(base + 0x00);
510 con &= ~(3 << (offset * 2));
512 __raw_writel(con, base + 0x00);
514 samsung_gpio_unlock(ourchip, flags);
518 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
519 unsigned offset, int value)
521 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
522 void __iomem *base = ourchip->base;
527 samsung_gpio_lock(ourchip, flags);
529 dat = __raw_readl(base + 0x04);
530 dat &= ~(1 << offset);
533 __raw_writel(dat, base + 0x04);
535 con = __raw_readl(base + 0x00);
536 con &= ~(3 << (offset * 2));
537 con |= 1 << (offset * 2);
539 __raw_writel(con, base + 0x00);
540 __raw_writel(dat, base + 0x04);
542 samsung_gpio_unlock(ourchip, flags);
547 * The samsung_gpiolib_4bit routines are to control the gpio banks where
548 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
551 * base + 0x00: Control register, 4 bits per gpio
552 * gpio n: 4 bits starting at (4*n)
553 * 0000 = input, 0001 = output, others mean special-function
554 * base + 0x04: Data register, 1 bit per gpio
557 * Note, since the data register is one bit per gpio and is at base + 0x4
558 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
559 * state of the output.
562 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
565 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
566 void __iomem *base = ourchip->base;
569 con = __raw_readl(base + GPIOCON_OFF);
570 con &= ~(0xf << con_4bit_shift(offset));
571 __raw_writel(con, base + GPIOCON_OFF);
573 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
578 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
579 unsigned int offset, int value)
581 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
582 void __iomem *base = ourchip->base;
586 con = __raw_readl(base + GPIOCON_OFF);
587 con &= ~(0xf << con_4bit_shift(offset));
588 con |= 0x1 << con_4bit_shift(offset);
590 dat = __raw_readl(base + GPIODAT_OFF);
595 dat &= ~(1 << offset);
597 __raw_writel(dat, base + GPIODAT_OFF);
598 __raw_writel(con, base + GPIOCON_OFF);
599 __raw_writel(dat, base + GPIODAT_OFF);
601 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
607 * The next set of routines are for the case where the GPIO configuration
608 * registers are 4 bits per GPIO but there is more than one register (the
609 * bank has more than 8 GPIOs.
611 * This case is the similar to the 4 bit case, but the registers are as
614 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
615 * gpio n: 4 bits starting at (4*n)
616 * 0000 = input, 0001 = output, others mean special-function
617 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
618 * gpio n: 4 bits starting at (4*n)
619 * 0000 = input, 0001 = output, others mean special-function
620 * base + 0x08: Data register, 1 bit per gpio
623 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
624 * routines we store the 'base + 0x4' address so that these routines see
625 * the data register at ourchip->base + 0x04.
628 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
631 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
632 void __iomem *base = ourchip->base;
633 void __iomem *regcon = base;
641 con = __raw_readl(regcon);
642 con &= ~(0xf << con_4bit_shift(offset));
643 __raw_writel(con, regcon);
645 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
650 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
651 unsigned int offset, int value)
653 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
654 void __iomem *base = ourchip->base;
655 void __iomem *regcon = base;
658 unsigned con_offset = offset;
665 con = __raw_readl(regcon);
666 con &= ~(0xf << con_4bit_shift(con_offset));
667 con |= 0x1 << con_4bit_shift(con_offset);
669 dat = __raw_readl(base + GPIODAT_OFF);
674 dat &= ~(1 << offset);
676 __raw_writel(dat, base + GPIODAT_OFF);
677 __raw_writel(con, regcon);
678 __raw_writel(dat, base + GPIODAT_OFF);
680 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
685 /* The next set of routines are for the case of s3c24xx bank a */
687 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
692 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
693 unsigned offset, int value)
695 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
696 void __iomem *base = ourchip->base;
701 local_irq_save(flags);
703 con = __raw_readl(base + 0x00);
704 dat = __raw_readl(base + 0x04);
706 dat &= ~(1 << offset);
710 __raw_writel(dat, base + 0x04);
712 con &= ~(1 << offset);
714 __raw_writel(con, base + 0x00);
715 __raw_writel(dat, base + 0x04);
717 local_irq_restore(flags);
721 /* The next set of routines are for the case of s5p64x0 bank r */
723 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
726 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
727 void __iomem *base = ourchip->base;
728 void __iomem *regcon = base;
748 samsung_gpio_lock(ourchip, flags);
750 con = __raw_readl(regcon);
751 con &= ~(0xf << con_4bit_shift(offset));
752 __raw_writel(con, regcon);
754 samsung_gpio_unlock(ourchip, flags);
759 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
760 unsigned int offset, int value)
762 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
763 void __iomem *base = ourchip->base;
764 void __iomem *regcon = base;
768 unsigned con_offset = offset;
770 switch (con_offset) {
786 samsung_gpio_lock(ourchip, flags);
788 con = __raw_readl(regcon);
789 con &= ~(0xf << con_4bit_shift(con_offset));
790 con |= 0x1 << con_4bit_shift(con_offset);
792 dat = __raw_readl(base + GPIODAT_OFF);
796 dat &= ~(1 << offset);
798 __raw_writel(con, regcon);
799 __raw_writel(dat, base + GPIODAT_OFF);
801 samsung_gpio_unlock(ourchip, flags);
806 static void samsung_gpiolib_set(struct gpio_chip *chip,
807 unsigned offset, int value)
809 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
810 void __iomem *base = ourchip->base;
814 samsung_gpio_lock(ourchip, flags);
816 dat = __raw_readl(base + 0x04);
817 dat &= ~(1 << offset);
820 __raw_writel(dat, base + 0x04);
822 samsung_gpio_unlock(ourchip, flags);
825 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
827 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
830 val = __raw_readl(ourchip->base + 0x04);
838 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
839 * for use with the configuration calls, and other parts of the s3c gpiolib
842 * Not all s3c support code will need this, as some configurations of cpu
843 * may only support one or two different configuration options and have an
844 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
845 * the machine support file should provide its own samsung_gpiolib_getchip()
846 * and any other necessary functions.
849 #ifdef CONFIG_S3C_GPIO_TRACK
850 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
852 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
857 gpn = chip->chip.base;
858 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
859 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
860 s3c_gpios[gpn] = chip;
863 #endif /* CONFIG_S3C_GPIO_TRACK */
866 * samsung_gpiolib_add() - add the Samsung gpio_chip.
867 * @chip: The chip to register
869 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
870 * information and makes the necessary alterations for the platform and
871 * notes the information for use with the configuration systems and any
872 * other parts of the system.
875 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
877 struct gpio_chip *gc = &chip->chip;
884 spin_lock_init(&chip->lock);
886 if (!gc->direction_input)
887 gc->direction_input = samsung_gpiolib_2bit_input;
888 if (!gc->direction_output)
889 gc->direction_output = samsung_gpiolib_2bit_output;
891 gc->set = samsung_gpiolib_set;
893 gc->get = samsung_gpiolib_get;
896 if (chip->pm != NULL) {
897 if (!chip->pm->save || !chip->pm->resume)
898 printk(KERN_ERR "gpio: %s has missing PM functions\n",
901 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
904 /* gpiochip_add() prints own failure message on error. */
905 ret = gpiochip_add(gc);
907 s3c_gpiolib_track(chip);
910 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
911 int nr_chips, void __iomem *base)
914 struct gpio_chip *gc = &chip->chip;
916 for (i = 0 ; i < nr_chips; i++, chip++) {
917 /* skip banks not present on SoC */
918 if (chip->chip.base >= S3C_GPIO_END)
922 chip->config = &s3c24xx_gpiocfg_default;
924 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
925 if ((base != NULL) && (chip->base == NULL))
926 chip->base = base + ((i) * 0x10);
928 if (!gc->direction_input)
929 gc->direction_input = samsung_gpiolib_2bit_input;
930 if (!gc->direction_output)
931 gc->direction_output = samsung_gpiolib_2bit_output;
933 samsung_gpiolib_add(chip);
937 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
938 int nr_chips, void __iomem *base,
943 for (i = 0 ; i < nr_chips; i++, chip++) {
944 chip->chip.direction_input = samsung_gpiolib_2bit_input;
945 chip->chip.direction_output = samsung_gpiolib_2bit_output;
948 chip->config = &samsung_gpio_cfgs[7];
950 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
951 if ((base != NULL) && (chip->base == NULL))
952 chip->base = base + ((i) * offset);
954 samsung_gpiolib_add(chip);
959 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
960 * @chip: The gpio chip that is being configured.
961 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
963 * This helper deal with the GPIO cases where the control register has 4 bits
964 * of control per GPIO, generally in the form of:
967 * others = Special functions (dependent on bank)
969 * Note, since the code to deal with the case where there are two control
970 * registers instead of one, we do not have a separate set of function
971 * (samsung_gpiolib_add_4bit2_chips)for each case.
974 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
975 int nr_chips, void __iomem *base)
979 for (i = 0 ; i < nr_chips; i++, chip++) {
980 chip->chip.direction_input = samsung_gpiolib_4bit_input;
981 chip->chip.direction_output = samsung_gpiolib_4bit_output;
984 chip->config = &samsung_gpio_cfgs[2];
986 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
987 if ((base != NULL) && (chip->base == NULL))
988 chip->base = base + ((i) * 0x20);
990 samsung_gpiolib_add(chip);
994 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
997 for (; nr_chips > 0; nr_chips--, chip++) {
998 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
999 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1002 chip->config = &samsung_gpio_cfgs[2];
1004 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1006 samsung_gpiolib_add(chip);
1010 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1013 for (; nr_chips > 0; nr_chips--, chip++) {
1014 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1015 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1018 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1020 samsung_gpiolib_add(chip);
1024 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1026 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1028 return samsung_chip->irq_base + offset;
1031 #ifdef CONFIG_PLAT_S3C24XX
1032 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1035 return IRQ_EINT0 + offset;
1038 return IRQ_EINT4 + offset - 4;
1044 #ifdef CONFIG_PLAT_S3C64XX
1045 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1047 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1050 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1052 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1056 struct samsung_gpio_chip s3c24xx_gpios[] = {
1057 #ifdef CONFIG_PLAT_S3C24XX
1059 .config = &s3c24xx_gpiocfg_banka,
1061 .base = S3C2410_GPA(0),
1062 .owner = THIS_MODULE,
1065 .direction_input = s3c24xx_gpiolib_banka_input,
1066 .direction_output = s3c24xx_gpiolib_banka_output,
1070 .base = S3C2410_GPB(0),
1071 .owner = THIS_MODULE,
1077 .base = S3C2410_GPC(0),
1078 .owner = THIS_MODULE,
1084 .base = S3C2410_GPD(0),
1085 .owner = THIS_MODULE,
1091 .base = S3C2410_GPE(0),
1093 .owner = THIS_MODULE,
1098 .base = S3C2410_GPF(0),
1099 .owner = THIS_MODULE,
1102 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1105 .irq_base = IRQ_EINT8,
1107 .base = S3C2410_GPG(0),
1108 .owner = THIS_MODULE,
1111 .to_irq = samsung_gpiolib_to_irq,
1115 .base = S3C2410_GPH(0),
1116 .owner = THIS_MODULE,
1121 /* GPIOS for the S3C2443 and later devices. */
1123 .base = S3C2440_GPJCON,
1125 .base = S3C2410_GPJ(0),
1126 .owner = THIS_MODULE,
1131 .base = S3C2443_GPKCON,
1133 .base = S3C2410_GPK(0),
1134 .owner = THIS_MODULE,
1139 .base = S3C2443_GPLCON,
1141 .base = S3C2410_GPL(0),
1142 .owner = THIS_MODULE,
1147 .base = S3C2443_GPMCON,
1149 .base = S3C2410_GPM(0),
1150 .owner = THIS_MODULE,
1159 * GPIO bank summary:
1161 * Bank GPIOs Style SlpCon ExtInt Group
1167 * F 16 2Bit Yes 4 [1]
1169 * H 10 4Bit[2] Yes 6
1170 * I 16 2Bit Yes None
1171 * J 12 2Bit Yes None
1172 * K 16 4Bit[2] No None
1173 * L 15 4Bit[2] No None
1174 * M 6 4Bit No IRQ_EINT
1175 * N 16 2Bit No IRQ_EINT
1180 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1181 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1184 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1185 #ifdef CONFIG_PLAT_S3C64XX
1188 .base = S3C64XX_GPA(0),
1189 .ngpio = S3C64XX_GPIO_A_NR,
1194 .base = S3C64XX_GPB(0),
1195 .ngpio = S3C64XX_GPIO_B_NR,
1200 .base = S3C64XX_GPC(0),
1201 .ngpio = S3C64XX_GPIO_C_NR,
1206 .base = S3C64XX_GPD(0),
1207 .ngpio = S3C64XX_GPIO_D_NR,
1211 .config = &samsung_gpio_cfgs[0],
1213 .base = S3C64XX_GPE(0),
1214 .ngpio = S3C64XX_GPIO_E_NR,
1218 .base = S3C64XX_GPG_BASE,
1220 .base = S3C64XX_GPG(0),
1221 .ngpio = S3C64XX_GPIO_G_NR,
1225 .base = S3C64XX_GPM_BASE,
1226 .config = &samsung_gpio_cfgs[1],
1228 .base = S3C64XX_GPM(0),
1229 .ngpio = S3C64XX_GPIO_M_NR,
1231 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1237 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1238 #ifdef CONFIG_PLAT_S3C64XX
1240 .base = S3C64XX_GPH_BASE + 0x4,
1242 .base = S3C64XX_GPH(0),
1243 .ngpio = S3C64XX_GPIO_H_NR,
1247 .base = S3C64XX_GPK_BASE + 0x4,
1248 .config = &samsung_gpio_cfgs[0],
1250 .base = S3C64XX_GPK(0),
1251 .ngpio = S3C64XX_GPIO_K_NR,
1255 .base = S3C64XX_GPL_BASE + 0x4,
1256 .config = &samsung_gpio_cfgs[1],
1258 .base = S3C64XX_GPL(0),
1259 .ngpio = S3C64XX_GPIO_L_NR,
1261 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1267 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1268 #ifdef CONFIG_PLAT_S3C64XX
1270 .base = S3C64XX_GPF_BASE,
1271 .config = &samsung_gpio_cfgs[6],
1273 .base = S3C64XX_GPF(0),
1274 .ngpio = S3C64XX_GPIO_F_NR,
1278 .config = &samsung_gpio_cfgs[7],
1280 .base = S3C64XX_GPI(0),
1281 .ngpio = S3C64XX_GPIO_I_NR,
1285 .config = &samsung_gpio_cfgs[7],
1287 .base = S3C64XX_GPJ(0),
1288 .ngpio = S3C64XX_GPIO_J_NR,
1292 .config = &samsung_gpio_cfgs[6],
1294 .base = S3C64XX_GPO(0),
1295 .ngpio = S3C64XX_GPIO_O_NR,
1299 .config = &samsung_gpio_cfgs[6],
1301 .base = S3C64XX_GPP(0),
1302 .ngpio = S3C64XX_GPIO_P_NR,
1306 .config = &samsung_gpio_cfgs[6],
1308 .base = S3C64XX_GPQ(0),
1309 .ngpio = S3C64XX_GPIO_Q_NR,
1313 .base = S3C64XX_GPN_BASE,
1314 .irq_base = IRQ_EINT(0),
1315 .config = &samsung_gpio_cfgs[5],
1317 .base = S3C64XX_GPN(0),
1318 .ngpio = S3C64XX_GPIO_N_NR,
1320 .to_irq = samsung_gpiolib_to_irq,
1327 * S5P6440 GPIO bank summary:
1329 * Bank GPIOs Style SlpCon ExtInt Group
1333 * F 2 2Bit Yes 4 [1]
1335 * H 10 4Bit[2] Yes 6
1336 * I 16 2Bit Yes None
1337 * J 12 2Bit Yes None
1338 * N 16 2Bit No IRQ_EINT
1340 * R 15 4Bit[2] Yes 8
1343 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1344 #ifdef CONFIG_CPU_S5P6440
1347 .base = S5P6440_GPA(0),
1348 .ngpio = S5P6440_GPIO_A_NR,
1353 .base = S5P6440_GPB(0),
1354 .ngpio = S5P6440_GPIO_B_NR,
1359 .base = S5P6440_GPC(0),
1360 .ngpio = S5P6440_GPIO_C_NR,
1364 .base = S5P64X0_GPG_BASE,
1366 .base = S5P6440_GPG(0),
1367 .ngpio = S5P6440_GPIO_G_NR,
1374 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1375 #ifdef CONFIG_CPU_S5P6440
1377 .base = S5P64X0_GPH_BASE + 0x4,
1379 .base = S5P6440_GPH(0),
1380 .ngpio = S5P6440_GPIO_H_NR,
1387 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1388 #ifdef CONFIG_CPU_S5P6440
1390 .base = S5P64X0_GPR_BASE + 0x4,
1391 .config = &s5p64x0_gpio_cfg_rbank,
1393 .base = S5P6440_GPR(0),
1394 .ngpio = S5P6440_GPIO_R_NR,
1401 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1402 #ifdef CONFIG_CPU_S5P6440
1404 .base = S5P64X0_GPF_BASE,
1405 .config = &samsung_gpio_cfgs[6],
1407 .base = S5P6440_GPF(0),
1408 .ngpio = S5P6440_GPIO_F_NR,
1412 .base = S5P64X0_GPI_BASE,
1413 .config = &samsung_gpio_cfgs[4],
1415 .base = S5P6440_GPI(0),
1416 .ngpio = S5P6440_GPIO_I_NR,
1420 .base = S5P64X0_GPJ_BASE,
1421 .config = &samsung_gpio_cfgs[4],
1423 .base = S5P6440_GPJ(0),
1424 .ngpio = S5P6440_GPIO_J_NR,
1428 .base = S5P64X0_GPN_BASE,
1429 .config = &samsung_gpio_cfgs[5],
1431 .base = S5P6440_GPN(0),
1432 .ngpio = S5P6440_GPIO_N_NR,
1436 .base = S5P64X0_GPP_BASE,
1437 .config = &samsung_gpio_cfgs[6],
1439 .base = S5P6440_GPP(0),
1440 .ngpio = S5P6440_GPIO_P_NR,
1448 * S5P6450 GPIO bank summary:
1450 * Bank GPIOs Style SlpCon ExtInt Group
1456 * G 14 4Bit[2] Yes 5
1457 * H 10 4Bit[2] Yes 6
1458 * I 16 2Bit Yes None
1459 * J 12 2Bit Yes None
1461 * N 16 2Bit No IRQ_EINT
1463 * Q 14 2Bit Yes None
1464 * R 15 4Bit[2] Yes None
1467 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1468 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1471 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1472 #ifdef CONFIG_CPU_S5P6450
1475 .base = S5P6450_GPA(0),
1476 .ngpio = S5P6450_GPIO_A_NR,
1481 .base = S5P6450_GPB(0),
1482 .ngpio = S5P6450_GPIO_B_NR,
1487 .base = S5P6450_GPC(0),
1488 .ngpio = S5P6450_GPIO_C_NR,
1493 .base = S5P6450_GPD(0),
1494 .ngpio = S5P6450_GPIO_D_NR,
1498 .base = S5P6450_GPK_BASE,
1500 .base = S5P6450_GPK(0),
1501 .ngpio = S5P6450_GPIO_K_NR,
1508 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1509 #ifdef CONFIG_CPU_S5P6450
1511 .base = S5P64X0_GPG_BASE + 0x4,
1513 .base = S5P6450_GPG(0),
1514 .ngpio = S5P6450_GPIO_G_NR,
1518 .base = S5P64X0_GPH_BASE + 0x4,
1520 .base = S5P6450_GPH(0),
1521 .ngpio = S5P6450_GPIO_H_NR,
1528 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1529 #ifdef CONFIG_CPU_S5P6450
1531 .base = S5P64X0_GPR_BASE + 0x4,
1532 .config = &s5p64x0_gpio_cfg_rbank,
1534 .base = S5P6450_GPR(0),
1535 .ngpio = S5P6450_GPIO_R_NR,
1542 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1543 #ifdef CONFIG_CPU_S5P6450
1545 .base = S5P64X0_GPF_BASE,
1546 .config = &samsung_gpio_cfgs[6],
1548 .base = S5P6450_GPF(0),
1549 .ngpio = S5P6450_GPIO_F_NR,
1553 .base = S5P64X0_GPI_BASE,
1554 .config = &samsung_gpio_cfgs[4],
1556 .base = S5P6450_GPI(0),
1557 .ngpio = S5P6450_GPIO_I_NR,
1561 .base = S5P64X0_GPJ_BASE,
1562 .config = &samsung_gpio_cfgs[4],
1564 .base = S5P6450_GPJ(0),
1565 .ngpio = S5P6450_GPIO_J_NR,
1569 .base = S5P64X0_GPN_BASE,
1570 .config = &samsung_gpio_cfgs[5],
1572 .base = S5P6450_GPN(0),
1573 .ngpio = S5P6450_GPIO_N_NR,
1577 .base = S5P64X0_GPP_BASE,
1578 .config = &samsung_gpio_cfgs[6],
1580 .base = S5P6450_GPP(0),
1581 .ngpio = S5P6450_GPIO_P_NR,
1585 .base = S5P6450_GPQ_BASE,
1586 .config = &samsung_gpio_cfgs[5],
1588 .base = S5P6450_GPQ(0),
1589 .ngpio = S5P6450_GPIO_Q_NR,
1593 .base = S5P6450_GPS_BASE,
1594 .config = &samsung_gpio_cfgs[6],
1596 .base = S5P6450_GPS(0),
1597 .ngpio = S5P6450_GPIO_S_NR,
1605 * S5PC100 GPIO bank summary:
1607 * Bank GPIOs Style INT Type
1608 * A0 8 4Bit GPIO_INT0
1609 * A1 5 4Bit GPIO_INT1
1610 * B 8 4Bit GPIO_INT2
1611 * C 5 4Bit GPIO_INT3
1612 * D 7 4Bit GPIO_INT4
1613 * E0 8 4Bit GPIO_INT5
1614 * E1 6 4Bit GPIO_INT6
1615 * F0 8 4Bit GPIO_INT7
1616 * F1 8 4Bit GPIO_INT8
1617 * F2 8 4Bit GPIO_INT9
1618 * F3 4 4Bit GPIO_INT10
1619 * G0 8 4Bit GPIO_INT11
1620 * G1 3 4Bit GPIO_INT12
1621 * G2 7 4Bit GPIO_INT13
1622 * G3 7 4Bit GPIO_INT14
1623 * H0 8 4Bit WKUP_INT
1624 * H1 8 4Bit WKUP_INT
1625 * H2 8 4Bit WKUP_INT
1626 * H3 8 4Bit WKUP_INT
1627 * I 8 4Bit GPIO_INT15
1628 * J0 8 4Bit GPIO_INT16
1629 * J1 5 4Bit GPIO_INT17
1630 * J2 8 4Bit GPIO_INT18
1631 * J3 8 4Bit GPIO_INT19
1632 * J4 4 4Bit GPIO_INT20
1643 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1644 #ifdef CONFIG_CPU_S5PC100
1647 .base = S5PC100_GPA0(0),
1648 .ngpio = S5PC100_GPIO_A0_NR,
1653 .base = S5PC100_GPA1(0),
1654 .ngpio = S5PC100_GPIO_A1_NR,
1659 .base = S5PC100_GPB(0),
1660 .ngpio = S5PC100_GPIO_B_NR,
1665 .base = S5PC100_GPC(0),
1666 .ngpio = S5PC100_GPIO_C_NR,
1671 .base = S5PC100_GPD(0),
1672 .ngpio = S5PC100_GPIO_D_NR,
1677 .base = S5PC100_GPE0(0),
1678 .ngpio = S5PC100_GPIO_E0_NR,
1683 .base = S5PC100_GPE1(0),
1684 .ngpio = S5PC100_GPIO_E1_NR,
1689 .base = S5PC100_GPF0(0),
1690 .ngpio = S5PC100_GPIO_F0_NR,
1695 .base = S5PC100_GPF1(0),
1696 .ngpio = S5PC100_GPIO_F1_NR,
1701 .base = S5PC100_GPF2(0),
1702 .ngpio = S5PC100_GPIO_F2_NR,
1707 .base = S5PC100_GPF3(0),
1708 .ngpio = S5PC100_GPIO_F3_NR,
1713 .base = S5PC100_GPG0(0),
1714 .ngpio = S5PC100_GPIO_G0_NR,
1719 .base = S5PC100_GPG1(0),
1720 .ngpio = S5PC100_GPIO_G1_NR,
1725 .base = S5PC100_GPG2(0),
1726 .ngpio = S5PC100_GPIO_G2_NR,
1731 .base = S5PC100_GPG3(0),
1732 .ngpio = S5PC100_GPIO_G3_NR,
1737 .base = S5PC100_GPI(0),
1738 .ngpio = S5PC100_GPIO_I_NR,
1743 .base = S5PC100_GPJ0(0),
1744 .ngpio = S5PC100_GPIO_J0_NR,
1749 .base = S5PC100_GPJ1(0),
1750 .ngpio = S5PC100_GPIO_J1_NR,
1755 .base = S5PC100_GPJ2(0),
1756 .ngpio = S5PC100_GPIO_J2_NR,
1761 .base = S5PC100_GPJ3(0),
1762 .ngpio = S5PC100_GPIO_J3_NR,
1767 .base = S5PC100_GPJ4(0),
1768 .ngpio = S5PC100_GPIO_J4_NR,
1773 .base = S5PC100_GPK0(0),
1774 .ngpio = S5PC100_GPIO_K0_NR,
1779 .base = S5PC100_GPK1(0),
1780 .ngpio = S5PC100_GPIO_K1_NR,
1785 .base = S5PC100_GPK2(0),
1786 .ngpio = S5PC100_GPIO_K2_NR,
1791 .base = S5PC100_GPK3(0),
1792 .ngpio = S5PC100_GPIO_K3_NR,
1797 .base = S5PC100_GPL0(0),
1798 .ngpio = S5PC100_GPIO_L0_NR,
1803 .base = S5PC100_GPL1(0),
1804 .ngpio = S5PC100_GPIO_L1_NR,
1809 .base = S5PC100_GPL2(0),
1810 .ngpio = S5PC100_GPIO_L2_NR,
1815 .base = S5PC100_GPL3(0),
1816 .ngpio = S5PC100_GPIO_L3_NR,
1821 .base = S5PC100_GPL4(0),
1822 .ngpio = S5PC100_GPIO_L4_NR,
1826 .base = (S5P_VA_GPIO + 0xC00),
1827 .irq_base = IRQ_EINT(0),
1829 .base = S5PC100_GPH0(0),
1830 .ngpio = S5PC100_GPIO_H0_NR,
1832 .to_irq = samsung_gpiolib_to_irq,
1835 .base = (S5P_VA_GPIO + 0xC20),
1836 .irq_base = IRQ_EINT(8),
1838 .base = S5PC100_GPH1(0),
1839 .ngpio = S5PC100_GPIO_H1_NR,
1841 .to_irq = samsung_gpiolib_to_irq,
1844 .base = (S5P_VA_GPIO + 0xC40),
1845 .irq_base = IRQ_EINT(16),
1847 .base = S5PC100_GPH2(0),
1848 .ngpio = S5PC100_GPIO_H2_NR,
1850 .to_irq = samsung_gpiolib_to_irq,
1853 .base = (S5P_VA_GPIO + 0xC60),
1854 .irq_base = IRQ_EINT(24),
1856 .base = S5PC100_GPH3(0),
1857 .ngpio = S5PC100_GPIO_H3_NR,
1859 .to_irq = samsung_gpiolib_to_irq,
1866 * Followings are the gpio banks in S5PV210/S5PC110
1868 * The 'config' member when left to NULL, is initialized to the default
1869 * structure samsung_gpio_cfgs[3] in the init function below.
1871 * The 'base' member is also initialized in the init function below.
1872 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1873 * uses the above macro and depends on the banks being listed in order here.
1876 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1877 #ifdef CONFIG_CPU_S5PV210
1880 .base = S5PV210_GPA0(0),
1881 .ngpio = S5PV210_GPIO_A0_NR,
1886 .base = S5PV210_GPA1(0),
1887 .ngpio = S5PV210_GPIO_A1_NR,
1892 .base = S5PV210_GPB(0),
1893 .ngpio = S5PV210_GPIO_B_NR,
1898 .base = S5PV210_GPC0(0),
1899 .ngpio = S5PV210_GPIO_C0_NR,
1904 .base = S5PV210_GPC1(0),
1905 .ngpio = S5PV210_GPIO_C1_NR,
1910 .base = S5PV210_GPD0(0),
1911 .ngpio = S5PV210_GPIO_D0_NR,
1916 .base = S5PV210_GPD1(0),
1917 .ngpio = S5PV210_GPIO_D1_NR,
1922 .base = S5PV210_GPE0(0),
1923 .ngpio = S5PV210_GPIO_E0_NR,
1928 .base = S5PV210_GPE1(0),
1929 .ngpio = S5PV210_GPIO_E1_NR,
1934 .base = S5PV210_GPF0(0),
1935 .ngpio = S5PV210_GPIO_F0_NR,
1940 .base = S5PV210_GPF1(0),
1941 .ngpio = S5PV210_GPIO_F1_NR,
1946 .base = S5PV210_GPF2(0),
1947 .ngpio = S5PV210_GPIO_F2_NR,
1952 .base = S5PV210_GPF3(0),
1953 .ngpio = S5PV210_GPIO_F3_NR,
1958 .base = S5PV210_GPG0(0),
1959 .ngpio = S5PV210_GPIO_G0_NR,
1964 .base = S5PV210_GPG1(0),
1965 .ngpio = S5PV210_GPIO_G1_NR,
1970 .base = S5PV210_GPG2(0),
1971 .ngpio = S5PV210_GPIO_G2_NR,
1976 .base = S5PV210_GPG3(0),
1977 .ngpio = S5PV210_GPIO_G3_NR,
1982 .base = S5PV210_GPI(0),
1983 .ngpio = S5PV210_GPIO_I_NR,
1988 .base = S5PV210_GPJ0(0),
1989 .ngpio = S5PV210_GPIO_J0_NR,
1994 .base = S5PV210_GPJ1(0),
1995 .ngpio = S5PV210_GPIO_J1_NR,
2000 .base = S5PV210_GPJ2(0),
2001 .ngpio = S5PV210_GPIO_J2_NR,
2006 .base = S5PV210_GPJ3(0),
2007 .ngpio = S5PV210_GPIO_J3_NR,
2012 .base = S5PV210_GPJ4(0),
2013 .ngpio = S5PV210_GPIO_J4_NR,
2018 .base = S5PV210_MP01(0),
2019 .ngpio = S5PV210_GPIO_MP01_NR,
2024 .base = S5PV210_MP02(0),
2025 .ngpio = S5PV210_GPIO_MP02_NR,
2030 .base = S5PV210_MP03(0),
2031 .ngpio = S5PV210_GPIO_MP03_NR,
2036 .base = S5PV210_MP04(0),
2037 .ngpio = S5PV210_GPIO_MP04_NR,
2042 .base = S5PV210_MP05(0),
2043 .ngpio = S5PV210_GPIO_MP05_NR,
2047 .base = (S5P_VA_GPIO + 0xC00),
2048 .irq_base = IRQ_EINT(0),
2050 .base = S5PV210_GPH0(0),
2051 .ngpio = S5PV210_GPIO_H0_NR,
2053 .to_irq = samsung_gpiolib_to_irq,
2056 .base = (S5P_VA_GPIO + 0xC20),
2057 .irq_base = IRQ_EINT(8),
2059 .base = S5PV210_GPH1(0),
2060 .ngpio = S5PV210_GPIO_H1_NR,
2062 .to_irq = samsung_gpiolib_to_irq,
2065 .base = (S5P_VA_GPIO + 0xC40),
2066 .irq_base = IRQ_EINT(16),
2068 .base = S5PV210_GPH2(0),
2069 .ngpio = S5PV210_GPIO_H2_NR,
2071 .to_irq = samsung_gpiolib_to_irq,
2074 .base = (S5P_VA_GPIO + 0xC60),
2075 .irq_base = IRQ_EINT(24),
2077 .base = S5PV210_GPH3(0),
2078 .ngpio = S5PV210_GPIO_H3_NR,
2080 .to_irq = samsung_gpiolib_to_irq,
2087 * Followings are the gpio banks in EXYNOS4210
2089 * The 'config' member when left to NULL, is initialized to the default
2090 * structure samsung_gpio_cfgs[3] in the init function below.
2092 * The 'base' member is also initialized in the init function below.
2093 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2094 * uses the above macro and depends on the banks being listed in order here.
2097 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2098 #ifdef CONFIG_ARCH_EXYNOS4
2101 .base = EXYNOS4_GPA0(0),
2102 .ngpio = EXYNOS4_GPIO_A0_NR,
2107 .base = EXYNOS4_GPA1(0),
2108 .ngpio = EXYNOS4_GPIO_A1_NR,
2113 .base = EXYNOS4_GPB(0),
2114 .ngpio = EXYNOS4_GPIO_B_NR,
2119 .base = EXYNOS4_GPC0(0),
2120 .ngpio = EXYNOS4_GPIO_C0_NR,
2125 .base = EXYNOS4_GPC1(0),
2126 .ngpio = EXYNOS4_GPIO_C1_NR,
2131 .base = EXYNOS4_GPD0(0),
2132 .ngpio = EXYNOS4_GPIO_D0_NR,
2137 .base = EXYNOS4_GPD1(0),
2138 .ngpio = EXYNOS4_GPIO_D1_NR,
2143 .base = EXYNOS4_GPE0(0),
2144 .ngpio = EXYNOS4_GPIO_E0_NR,
2149 .base = EXYNOS4_GPE1(0),
2150 .ngpio = EXYNOS4_GPIO_E1_NR,
2155 .base = EXYNOS4_GPE2(0),
2156 .ngpio = EXYNOS4_GPIO_E2_NR,
2161 .base = EXYNOS4_GPE3(0),
2162 .ngpio = EXYNOS4_GPIO_E3_NR,
2167 .base = EXYNOS4_GPE4(0),
2168 .ngpio = EXYNOS4_GPIO_E4_NR,
2173 .base = EXYNOS4_GPF0(0),
2174 .ngpio = EXYNOS4_GPIO_F0_NR,
2179 .base = EXYNOS4_GPF1(0),
2180 .ngpio = EXYNOS4_GPIO_F1_NR,
2185 .base = EXYNOS4_GPF2(0),
2186 .ngpio = EXYNOS4_GPIO_F2_NR,
2191 .base = EXYNOS4_GPF3(0),
2192 .ngpio = EXYNOS4_GPIO_F3_NR,
2199 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2200 #ifdef CONFIG_ARCH_EXYNOS4
2203 .base = EXYNOS4_GPJ0(0),
2204 .ngpio = EXYNOS4_GPIO_J0_NR,
2209 .base = EXYNOS4_GPJ1(0),
2210 .ngpio = EXYNOS4_GPIO_J1_NR,
2215 .base = EXYNOS4_GPK0(0),
2216 .ngpio = EXYNOS4_GPIO_K0_NR,
2221 .base = EXYNOS4_GPK1(0),
2222 .ngpio = EXYNOS4_GPIO_K1_NR,
2227 .base = EXYNOS4_GPK2(0),
2228 .ngpio = EXYNOS4_GPIO_K2_NR,
2233 .base = EXYNOS4_GPK3(0),
2234 .ngpio = EXYNOS4_GPIO_K3_NR,
2239 .base = EXYNOS4_GPL0(0),
2240 .ngpio = EXYNOS4_GPIO_L0_NR,
2245 .base = EXYNOS4_GPL1(0),
2246 .ngpio = EXYNOS4_GPIO_L1_NR,
2251 .base = EXYNOS4_GPL2(0),
2252 .ngpio = EXYNOS4_GPIO_L2_NR,
2256 .config = &samsung_gpio_cfgs[0],
2258 .base = EXYNOS4_GPY0(0),
2259 .ngpio = EXYNOS4_GPIO_Y0_NR,
2263 .config = &samsung_gpio_cfgs[0],
2265 .base = EXYNOS4_GPY1(0),
2266 .ngpio = EXYNOS4_GPIO_Y1_NR,
2270 .config = &samsung_gpio_cfgs[0],
2272 .base = EXYNOS4_GPY2(0),
2273 .ngpio = EXYNOS4_GPIO_Y2_NR,
2277 .config = &samsung_gpio_cfgs[0],
2279 .base = EXYNOS4_GPY3(0),
2280 .ngpio = EXYNOS4_GPIO_Y3_NR,
2284 .config = &samsung_gpio_cfgs[0],
2286 .base = EXYNOS4_GPY4(0),
2287 .ngpio = EXYNOS4_GPIO_Y4_NR,
2291 .config = &samsung_gpio_cfgs[0],
2293 .base = EXYNOS4_GPY5(0),
2294 .ngpio = EXYNOS4_GPIO_Y5_NR,
2298 .config = &samsung_gpio_cfgs[0],
2300 .base = EXYNOS4_GPY6(0),
2301 .ngpio = EXYNOS4_GPIO_Y6_NR,
2305 .base = (S5P_VA_GPIO2 + 0xC00),
2306 .config = &samsung_gpio_cfgs[3],
2307 .irq_base = IRQ_EINT(0),
2309 .base = EXYNOS4_GPX0(0),
2310 .ngpio = EXYNOS4_GPIO_X0_NR,
2312 .to_irq = samsung_gpiolib_to_irq,
2315 .base = (S5P_VA_GPIO2 + 0xC20),
2316 .config = &samsung_gpio_cfgs[3],
2317 .irq_base = IRQ_EINT(8),
2319 .base = EXYNOS4_GPX1(0),
2320 .ngpio = EXYNOS4_GPIO_X1_NR,
2322 .to_irq = samsung_gpiolib_to_irq,
2325 .base = (S5P_VA_GPIO2 + 0xC40),
2326 .config = &samsung_gpio_cfgs[3],
2327 .irq_base = IRQ_EINT(16),
2329 .base = EXYNOS4_GPX2(0),
2330 .ngpio = EXYNOS4_GPIO_X2_NR,
2332 .to_irq = samsung_gpiolib_to_irq,
2335 .base = (S5P_VA_GPIO2 + 0xC60),
2336 .config = &samsung_gpio_cfgs[3],
2337 .irq_base = IRQ_EINT(24),
2339 .base = EXYNOS4_GPX3(0),
2340 .ngpio = EXYNOS4_GPIO_X3_NR,
2342 .to_irq = samsung_gpiolib_to_irq,
2348 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2349 #ifdef CONFIG_ARCH_EXYNOS4
2352 .base = EXYNOS4_GPZ(0),
2353 .ngpio = EXYNOS4_GPIO_Z_NR,
2360 /* TODO: cleanup soc_is_* */
2361 static __init int samsung_gpiolib_init(void)
2363 struct samsung_gpio_chip *chip;
2367 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2369 if (soc_is_s3c24xx()) {
2370 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2371 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2372 } else if (soc_is_s3c64xx()) {
2373 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2374 ARRAY_SIZE(s3c64xx_gpios_2bit),
2375 S3C64XX_VA_GPIO + 0xE0, 0x20);
2376 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2377 ARRAY_SIZE(s3c64xx_gpios_4bit),
2379 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2380 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2381 } else if (soc_is_s5p6440()) {
2382 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2383 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2384 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2385 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2386 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2387 ARRAY_SIZE(s5p6440_gpios_4bit2));
2388 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2389 ARRAY_SIZE(s5p6440_gpios_rbank));
2390 } else if (soc_is_s5p6450()) {
2391 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2392 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2393 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2394 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2395 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2396 ARRAY_SIZE(s5p6450_gpios_4bit2));
2397 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2398 ARRAY_SIZE(s5p6450_gpios_rbank));
2399 } else if (soc_is_s5pc100()) {
2401 chip = s5pc100_gpios_4bit;
2402 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2404 for (i = 0; i < nr_chips; i++, chip++) {
2405 if (!chip->config) {
2406 chip->config = &samsung_gpio_cfgs[3];
2407 chip->group = group++;
2410 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2411 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2412 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2414 } else if (soc_is_s5pv210()) {
2416 chip = s5pv210_gpios_4bit;
2417 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2419 for (i = 0; i < nr_chips; i++, chip++) {
2420 if (!chip->config) {
2421 chip->config = &samsung_gpio_cfgs[3];
2422 chip->group = group++;
2425 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2426 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2427 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2429 } else if (soc_is_exynos4210()) {
2433 chip = exynos4_gpios_1;
2434 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2436 for (i = 0; i < nr_chips; i++, chip++) {
2437 if (!chip->config) {
2438 chip->config = &exynos4_gpio_cfg;
2439 chip->group = group++;
2442 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1);
2445 chip = exynos4_gpios_2;
2446 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2448 for (i = 0; i < nr_chips; i++, chip++) {
2449 if (!chip->config) {
2450 chip->config = &exynos4_gpio_cfg;
2451 chip->group = group++;
2454 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2);
2457 chip = exynos4_gpios_3;
2458 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2460 for (i = 0; i < nr_chips; i++, chip++) {
2461 if (!chip->config) {
2462 chip->config = &exynos4_gpio_cfg;
2463 chip->group = group++;
2466 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3);
2468 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2469 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2470 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2476 core_initcall(samsung_gpiolib_init);
2478 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2480 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2481 unsigned long flags;
2488 offset = pin - chip->chip.base;
2490 samsung_gpio_lock(chip, flags);
2491 ret = samsung_gpio_do_setcfg(chip, offset, config);
2492 samsung_gpio_unlock(chip, flags);
2496 EXPORT_SYMBOL(s3c_gpio_cfgpin);
2498 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
2503 for (; nr > 0; nr--, start++) {
2504 ret = s3c_gpio_cfgpin(start, cfg);
2511 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
2513 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
2514 unsigned int cfg, samsung_gpio_pull_t pull)
2518 for (; nr > 0; nr--, start++) {
2519 s3c_gpio_setpull(start, pull);
2520 ret = s3c_gpio_cfgpin(start, cfg);
2527 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
2529 unsigned s3c_gpio_getcfg(unsigned int pin)
2531 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2532 unsigned long flags;
2537 offset = pin - chip->chip.base;
2539 samsung_gpio_lock(chip, flags);
2540 ret = samsung_gpio_do_getcfg(chip, offset);
2541 samsung_gpio_unlock(chip, flags);
2546 EXPORT_SYMBOL(s3c_gpio_getcfg);
2548 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
2550 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2551 unsigned long flags;
2557 offset = pin - chip->chip.base;
2559 samsung_gpio_lock(chip, flags);
2560 ret = samsung_gpio_do_setpull(chip, offset, pull);
2561 samsung_gpio_unlock(chip, flags);
2565 EXPORT_SYMBOL(s3c_gpio_setpull);
2567 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
2569 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2570 unsigned long flags;
2575 offset = pin - chip->chip.base;
2577 samsung_gpio_lock(chip, flags);
2578 pup = samsung_gpio_do_getpull(chip, offset);
2579 samsung_gpio_unlock(chip, flags);
2582 return (__force samsung_gpio_pull_t)pup;
2584 EXPORT_SYMBOL(s3c_gpio_getpull);
2586 /* gpiolib wrappers until these are totally eliminated */
2588 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
2592 WARN_ON(to); /* should be none of these left */
2595 /* if pull is enabled, try first with up, and if that
2596 * fails, try using down */
2598 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
2600 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
2602 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
2605 EXPORT_SYMBOL(s3c2410_gpio_pullup);
2607 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
2609 /* do this via gpiolib until all users removed */
2611 gpio_request(pin, "temporary");
2612 gpio_set_value(pin, to);
2615 EXPORT_SYMBOL(s3c2410_gpio_setpin);
2617 unsigned int s3c2410_gpio_getpin(unsigned int pin)
2619 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2620 unsigned long offs = pin - chip->chip.base;
2622 return __raw_readl(chip->base + 0x04) & (1 << offs);
2624 EXPORT_SYMBOL(s3c2410_gpio_getpin);
2626 #ifdef CONFIG_S5P_GPIO_DRVSTR
2627 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
2629 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2638 off = pin - chip->chip.base;
2640 reg = chip->base + 0x0C;
2642 drvstr = __raw_readl(reg);
2643 drvstr = drvstr >> shift;
2646 return (__force s5p_gpio_drvstr_t)drvstr;
2648 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
2650 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
2652 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2661 off = pin - chip->chip.base;
2663 reg = chip->base + 0x0C;
2665 tmp = __raw_readl(reg);
2666 tmp &= ~(0x3 << shift);
2667 tmp |= drvstr << shift;
2669 __raw_writel(tmp, reg);
2673 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
2674 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2676 #ifdef CONFIG_PLAT_S3C24XX
2677 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
2679 unsigned long flags;
2680 unsigned long misccr;
2682 local_irq_save(flags);
2683 misccr = __raw_readl(S3C24XX_MISCCR);
2686 __raw_writel(misccr, S3C24XX_MISCCR);
2687 local_irq_restore(flags);
2691 EXPORT_SYMBOL(s3c2410_modify_misccr);