2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-clock.h>
36 #include <mach/regs-gpio.h>
39 #include <plat/gpio-core.h>
40 #include <plat/gpio-cfg.h>
41 #include <plat/gpio-cfg-helpers.h>
42 #include <plat/gpio-fns.h>
45 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
46 unsigned int off, samsung_gpio_pull_t pull)
48 void __iomem *reg = chip->base + 0x08;
52 pup = __raw_readl(reg);
55 __raw_writel(pup, reg);
60 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
63 void __iomem *reg = chip->base + 0x08;
65 u32 pup = __raw_readl(reg);
70 return (__force samsung_gpio_pull_t)pup;
73 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
74 unsigned int off, samsung_gpio_pull_t pull)
77 case S3C_GPIO_PULL_NONE:
80 case S3C_GPIO_PULL_UP:
83 case S3C_GPIO_PULL_DOWN:
87 return samsung_gpio_setpull_updown(chip, off, pull);
90 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
93 samsung_gpio_pull_t pull;
95 pull = samsung_gpio_getpull_updown(chip, off);
99 pull = S3C_GPIO_PULL_UP;
103 pull = S3C_GPIO_PULL_NONE;
106 pull = S3C_GPIO_PULL_DOWN;
113 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
114 unsigned int off, samsung_gpio_pull_t pull,
115 samsung_gpio_pull_t updown)
117 void __iomem *reg = chip->base + 0x08;
118 u32 pup = __raw_readl(reg);
122 else if (pull == S3C_GPIO_PULL_NONE)
127 __raw_writel(pup, reg);
131 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
133 samsung_gpio_pull_t updown)
135 void __iomem *reg = chip->base + 0x08;
136 u32 pup = __raw_readl(reg);
139 return pup ? S3C_GPIO_PULL_NONE : updown;
142 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
145 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
148 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
149 unsigned int off, samsung_gpio_pull_t pull)
151 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
154 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
157 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
160 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
161 unsigned int off, samsung_gpio_pull_t pull)
163 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
166 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
169 if (pull == S3C_GPIO_PULL_UP)
172 return samsung_gpio_setpull_updown(chip, off, pull);
175 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
178 samsung_gpio_pull_t pull;
180 pull = samsung_gpio_getpull_updown(chip, off);
183 pull = S3C_GPIO_PULL_UP;
189 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
190 * @chip: The gpio chip that is being configured.
191 * @off: The offset for the GPIO being configured.
192 * @cfg: The configuration value to set.
194 * This helper deal with the GPIO cases where the control register
195 * has two bits of configuration per gpio, which have the following
199 * 1x = special function
202 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
203 unsigned int off, unsigned int cfg)
205 void __iomem *reg = chip->base;
206 unsigned int shift = off * 2;
209 if (samsung_gpio_is_cfg_special(cfg)) {
217 con = __raw_readl(reg);
218 con &= ~(0x3 << shift);
220 __raw_writel(con, reg);
226 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
227 * @chip: The gpio chip that is being configured.
228 * @off: The offset for the GPIO being configured.
230 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
231 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
232 * S3C_GPIO_SPECIAL() macro.
235 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
240 con = __raw_readl(chip->base);
244 /* this conversion works for IN and OUT as well as special mode */
245 return S3C_GPIO_SPECIAL(con);
249 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
250 * @chip: The gpio chip that is being configured.
251 * @off: The offset for the GPIO being configured.
252 * @cfg: The configuration value to set.
254 * This helper deal with the GPIO cases where the control register has 4 bits
255 * of control per GPIO, generally in the form of:
258 * others = Special functions (dependent on bank)
260 * Note, since the code to deal with the case where there are two control
261 * registers instead of one, we do not have a separate set of functions for
265 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
266 unsigned int off, unsigned int cfg)
268 void __iomem *reg = chip->base;
269 unsigned int shift = (off & 7) * 4;
272 if (off < 8 && chip->chip.ngpio > 8)
275 if (samsung_gpio_is_cfg_special(cfg)) {
280 con = __raw_readl(reg);
281 con &= ~(0xf << shift);
283 __raw_writel(con, reg);
289 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
290 * @chip: The gpio chip that is being configured.
291 * @off: The offset for the GPIO being configured.
293 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
294 * register setting into a value the software can use, such as could be passed
295 * to samsung_gpio_setcfg_4bit().
297 * @sa samsung_gpio_getcfg_2bit
300 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
303 void __iomem *reg = chip->base;
304 unsigned int shift = (off & 7) * 4;
307 if (off < 8 && chip->chip.ngpio > 8)
310 con = __raw_readl(reg);
314 /* this conversion works for IN and OUT as well as special mode */
315 return S3C_GPIO_SPECIAL(con);
318 #ifdef CONFIG_PLAT_S3C24XX
320 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
321 * @chip: The gpio chip that is being configured.
322 * @off: The offset for the GPIO being configured.
323 * @cfg: The configuration value to set.
325 * This helper deal with the GPIO cases where the control register
326 * has one bit of configuration for the gpio, where setting the bit
327 * means the pin is in special function mode and unset means output.
330 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
331 unsigned int off, unsigned int cfg)
333 void __iomem *reg = chip->base;
334 unsigned int shift = off;
337 if (samsung_gpio_is_cfg_special(cfg)) {
340 /* Map output to 0, and SFN2 to 1 */
348 con = __raw_readl(reg);
349 con &= ~(0x1 << shift);
351 __raw_writel(con, reg);
357 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
358 * @chip: The gpio chip that is being configured.
359 * @off: The offset for the GPIO being configured.
361 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
362 * GPIO configuration value.
364 * @sa samsung_gpio_getcfg_2bit
365 * @sa samsung_gpio_getcfg_4bit
368 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
373 con = __raw_readl(chip->base);
378 return S3C_GPIO_SFN(con);
382 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
383 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
384 unsigned int off, unsigned int cfg)
386 void __iomem *reg = chip->base;
397 shift = (off & 7) * 4;
401 shift = ((off + 1) & 7) * 4;
404 shift = ((off + 1) & 7) * 4;
408 if (samsung_gpio_is_cfg_special(cfg)) {
413 con = __raw_readl(reg);
414 con &= ~(0xf << shift);
416 __raw_writel(con, reg);
422 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
425 for (; nr_chips > 0; nr_chips--, chipcfg++) {
426 if (!chipcfg->set_config)
427 chipcfg->set_config = samsung_gpio_setcfg_4bit;
428 if (!chipcfg->get_config)
429 chipcfg->get_config = samsung_gpio_getcfg_4bit;
430 if (!chipcfg->set_pull)
431 chipcfg->set_pull = samsung_gpio_setpull_updown;
432 if (!chipcfg->get_pull)
433 chipcfg->get_pull = samsung_gpio_getpull_updown;
437 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
438 .set_config = samsung_gpio_setcfg_2bit,
439 .get_config = samsung_gpio_getcfg_2bit,
442 #ifdef CONFIG_PLAT_S3C24XX
443 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
444 .set_config = s3c24xx_gpio_setcfg_abank,
445 .get_config = s3c24xx_gpio_getcfg_abank,
449 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
450 static struct samsung_gpio_cfg exynos_gpio_cfg = {
451 .set_pull = exynos_gpio_setpull,
452 .get_pull = exynos_gpio_getpull,
453 .set_config = samsung_gpio_setcfg_4bit,
454 .get_config = samsung_gpio_getcfg_4bit,
458 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
459 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
461 .set_config = s5p64x0_gpio_setcfg_rbank,
462 .get_config = samsung_gpio_getcfg_4bit,
463 .set_pull = samsung_gpio_setpull_updown,
464 .get_pull = samsung_gpio_getpull_updown,
468 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
483 .set_config = samsung_gpio_setcfg_2bit,
484 .get_config = samsung_gpio_getcfg_2bit,
488 .set_config = samsung_gpio_setcfg_2bit,
489 .get_config = samsung_gpio_getcfg_2bit,
493 .set_config = samsung_gpio_setcfg_2bit,
494 .get_config = samsung_gpio_getcfg_2bit,
497 .set_config = samsung_gpio_setcfg_2bit,
498 .get_config = samsung_gpio_getcfg_2bit,
501 .set_pull = exynos_gpio_setpull,
502 .get_pull = exynos_gpio_getpull,
506 .set_pull = exynos_gpio_setpull,
507 .get_pull = exynos_gpio_getpull,
512 * Default routines for controlling GPIO, based on the original S3C24XX
513 * GPIO functions which deal with the case where each gpio bank of the
514 * chip is as following:
516 * base + 0x00: Control register, 2 bits per gpio
517 * gpio n: 2 bits starting at (2*n)
518 * 00 = input, 01 = output, others mean special-function
519 * base + 0x04: Data register, 1 bit per gpio
523 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
525 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
526 void __iomem *base = ourchip->base;
530 samsung_gpio_lock(ourchip, flags);
532 con = __raw_readl(base + 0x00);
533 con &= ~(3 << (offset * 2));
535 __raw_writel(con, base + 0x00);
537 samsung_gpio_unlock(ourchip, flags);
541 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
542 unsigned offset, int value)
544 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
545 void __iomem *base = ourchip->base;
550 samsung_gpio_lock(ourchip, flags);
552 dat = __raw_readl(base + 0x04);
553 dat &= ~(1 << offset);
556 __raw_writel(dat, base + 0x04);
558 con = __raw_readl(base + 0x00);
559 con &= ~(3 << (offset * 2));
560 con |= 1 << (offset * 2);
562 __raw_writel(con, base + 0x00);
563 __raw_writel(dat, base + 0x04);
565 samsung_gpio_unlock(ourchip, flags);
570 * The samsung_gpiolib_4bit routines are to control the gpio banks where
571 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
574 * base + 0x00: Control register, 4 bits per gpio
575 * gpio n: 4 bits starting at (4*n)
576 * 0000 = input, 0001 = output, others mean special-function
577 * base + 0x04: Data register, 1 bit per gpio
580 * Note, since the data register is one bit per gpio and is at base + 0x4
581 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
582 * state of the output.
585 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
588 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
589 void __iomem *base = ourchip->base;
592 con = __raw_readl(base + GPIOCON_OFF);
593 if (ourchip->bitmap_gpio_int & BIT(offset))
594 con |= 0xf << con_4bit_shift(offset);
596 con &= ~(0xf << con_4bit_shift(offset));
597 __raw_writel(con, base + GPIOCON_OFF);
599 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
604 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
605 unsigned int offset, int value)
607 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
608 void __iomem *base = ourchip->base;
612 con = __raw_readl(base + GPIOCON_OFF);
613 con &= ~(0xf << con_4bit_shift(offset));
614 con |= 0x1 << con_4bit_shift(offset);
616 dat = __raw_readl(base + GPIODAT_OFF);
621 dat &= ~(1 << offset);
623 __raw_writel(dat, base + GPIODAT_OFF);
624 __raw_writel(con, base + GPIOCON_OFF);
625 __raw_writel(dat, base + GPIODAT_OFF);
627 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
633 * The next set of routines are for the case where the GPIO configuration
634 * registers are 4 bits per GPIO but there is more than one register (the
635 * bank has more than 8 GPIOs.
637 * This case is the similar to the 4 bit case, but the registers are as
640 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
641 * gpio n: 4 bits starting at (4*n)
642 * 0000 = input, 0001 = output, others mean special-function
643 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
644 * gpio n: 4 bits starting at (4*n)
645 * 0000 = input, 0001 = output, others mean special-function
646 * base + 0x08: Data register, 1 bit per gpio
649 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
650 * routines we store the 'base + 0x4' address so that these routines see
651 * the data register at ourchip->base + 0x04.
654 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
657 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
658 void __iomem *base = ourchip->base;
659 void __iomem *regcon = base;
667 con = __raw_readl(regcon);
668 con &= ~(0xf << con_4bit_shift(offset));
669 __raw_writel(con, regcon);
671 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
676 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
677 unsigned int offset, int value)
679 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
680 void __iomem *base = ourchip->base;
681 void __iomem *regcon = base;
684 unsigned con_offset = offset;
691 con = __raw_readl(regcon);
692 con &= ~(0xf << con_4bit_shift(con_offset));
693 con |= 0x1 << con_4bit_shift(con_offset);
695 dat = __raw_readl(base + GPIODAT_OFF);
700 dat &= ~(1 << offset);
702 __raw_writel(dat, base + GPIODAT_OFF);
703 __raw_writel(con, regcon);
704 __raw_writel(dat, base + GPIODAT_OFF);
706 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
711 #ifdef CONFIG_PLAT_S3C24XX
712 /* The next set of routines are for the case of s3c24xx bank a */
714 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
719 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
720 unsigned offset, int value)
722 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
723 void __iomem *base = ourchip->base;
728 local_irq_save(flags);
730 con = __raw_readl(base + 0x00);
731 dat = __raw_readl(base + 0x04);
733 dat &= ~(1 << offset);
737 __raw_writel(dat, base + 0x04);
739 con &= ~(1 << offset);
741 __raw_writel(con, base + 0x00);
742 __raw_writel(dat, base + 0x04);
744 local_irq_restore(flags);
749 /* The next set of routines are for the case of s5p64x0 bank r */
751 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
754 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
755 void __iomem *base = ourchip->base;
756 void __iomem *regcon = base;
776 samsung_gpio_lock(ourchip, flags);
778 con = __raw_readl(regcon);
779 con &= ~(0xf << con_4bit_shift(offset));
780 __raw_writel(con, regcon);
782 samsung_gpio_unlock(ourchip, flags);
787 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
788 unsigned int offset, int value)
790 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
791 void __iomem *base = ourchip->base;
792 void __iomem *regcon = base;
796 unsigned con_offset = offset;
798 switch (con_offset) {
814 samsung_gpio_lock(ourchip, flags);
816 con = __raw_readl(regcon);
817 con &= ~(0xf << con_4bit_shift(con_offset));
818 con |= 0x1 << con_4bit_shift(con_offset);
820 dat = __raw_readl(base + GPIODAT_OFF);
824 dat &= ~(1 << offset);
826 __raw_writel(con, regcon);
827 __raw_writel(dat, base + GPIODAT_OFF);
829 samsung_gpio_unlock(ourchip, flags);
834 static void samsung_gpiolib_set(struct gpio_chip *chip,
835 unsigned offset, int value)
837 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
838 void __iomem *base = ourchip->base;
842 samsung_gpio_lock(ourchip, flags);
844 dat = __raw_readl(base + 0x04);
845 dat &= ~(1 << offset);
848 __raw_writel(dat, base + 0x04);
850 samsung_gpio_unlock(ourchip, flags);
853 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
855 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
858 val = __raw_readl(ourchip->base + 0x04);
866 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
867 * for use with the configuration calls, and other parts of the s3c gpiolib
870 * Not all s3c support code will need this, as some configurations of cpu
871 * may only support one or two different configuration options and have an
872 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
873 * the machine support file should provide its own samsung_gpiolib_getchip()
874 * and any other necessary functions.
877 #ifdef CONFIG_S3C_GPIO_TRACK
878 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
880 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
885 gpn = chip->chip.base;
886 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
887 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
888 s3c_gpios[gpn] = chip;
891 #endif /* CONFIG_S3C_GPIO_TRACK */
894 * samsung_gpiolib_add() - add the Samsung gpio_chip.
895 * @chip: The chip to register
897 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
898 * information and makes the necessary alterations for the platform and
899 * notes the information for use with the configuration systems and any
900 * other parts of the system.
903 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
905 struct gpio_chip *gc = &chip->chip;
912 spin_lock_init(&chip->lock);
914 if (!gc->direction_input)
915 gc->direction_input = samsung_gpiolib_2bit_input;
916 if (!gc->direction_output)
917 gc->direction_output = samsung_gpiolib_2bit_output;
919 gc->set = samsung_gpiolib_set;
921 gc->get = samsung_gpiolib_get;
924 if (chip->pm != NULL) {
925 if (!chip->pm->save || !chip->pm->resume)
926 pr_err("gpio: %s has missing PM functions\n",
929 pr_err("gpio: %s has no PM function\n", gc->label);
932 /* gpiochip_add() prints own failure message on error. */
933 ret = gpiochip_add(gc);
935 s3c_gpiolib_track(chip);
938 #if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
939 static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
940 const struct of_phandle_args *gpiospec, u32 *flags)
944 if (WARN_ON(gc->of_gpio_n_cells < 3))
947 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
950 if (gpiospec->args[0] > gc->ngpio)
953 pin = gc->base + gpiospec->args[0];
955 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
956 pr_warn("gpio_xlate: failed to set pin function\n");
957 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
958 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
961 *flags = gpiospec->args[2] >> 16;
963 return gpiospec->args[0];
966 static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
967 { .compatible = "samsung,s3c24xx-gpio", },
971 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
972 u64 base, u64 offset)
974 struct gpio_chip *gc = &chip->chip;
977 if (!of_have_populated_dt())
980 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
981 gc->of_node = of_find_matching_node_by_address(NULL,
982 s3c24xx_gpio_dt_match, address);
984 pr_info("gpio: device tree node not found for gpio controller"
985 " with base address %08llx\n", address);
988 gc->of_gpio_n_cells = 3;
989 gc->of_xlate = s3c24xx_gpio_xlate;
992 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
993 u64 base, u64 offset)
997 #endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
999 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
1000 int nr_chips, void __iomem *base)
1003 struct gpio_chip *gc = &chip->chip;
1005 for (i = 0 ; i < nr_chips; i++, chip++) {
1006 /* skip banks not present on SoC */
1007 if (chip->chip.base >= S3C_GPIO_END)
1011 chip->config = &s3c24xx_gpiocfg_default;
1013 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1014 if ((base != NULL) && (chip->base == NULL))
1015 chip->base = base + ((i) * 0x10);
1017 if (!gc->direction_input)
1018 gc->direction_input = samsung_gpiolib_2bit_input;
1019 if (!gc->direction_output)
1020 gc->direction_output = samsung_gpiolib_2bit_output;
1022 samsung_gpiolib_add(chip);
1024 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1028 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1029 int nr_chips, void __iomem *base,
1030 unsigned int offset)
1034 for (i = 0 ; i < nr_chips; i++, chip++) {
1035 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1036 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1039 chip->config = &samsung_gpio_cfgs[7];
1041 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1042 if ((base != NULL) && (chip->base == NULL))
1043 chip->base = base + ((i) * offset);
1045 samsung_gpiolib_add(chip);
1050 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1051 * @chip: The gpio chip that is being configured.
1052 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1054 * This helper deal with the GPIO cases where the control register has 4 bits
1055 * of control per GPIO, generally in the form of:
1058 * others = Special functions (dependent on bank)
1060 * Note, since the code to deal with the case where there are two control
1061 * registers instead of one, we do not have a separate set of function
1062 * (samsung_gpiolib_add_4bit2_chips)for each case.
1065 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1066 int nr_chips, void __iomem *base)
1070 for (i = 0 ; i < nr_chips; i++, chip++) {
1071 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1072 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1075 chip->config = &samsung_gpio_cfgs[2];
1077 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1078 if ((base != NULL) && (chip->base == NULL))
1079 chip->base = base + ((i) * 0x20);
1081 chip->bitmap_gpio_int = 0;
1083 samsung_gpiolib_add(chip);
1087 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1090 for (; nr_chips > 0; nr_chips--, chip++) {
1091 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1092 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1095 chip->config = &samsung_gpio_cfgs[2];
1097 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1099 samsung_gpiolib_add(chip);
1103 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1106 for (; nr_chips > 0; nr_chips--, chip++) {
1107 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1108 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1111 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1113 samsung_gpiolib_add(chip);
1117 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1119 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1121 return samsung_chip->irq_base + offset;
1124 #ifdef CONFIG_PLAT_S3C24XX
1125 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1128 return IRQ_EINT0 + offset;
1131 return IRQ_EINT4 + offset - 4;
1137 #ifdef CONFIG_PLAT_S3C64XX
1138 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1140 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1143 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1145 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1149 struct samsung_gpio_chip s3c24xx_gpios[] = {
1150 #ifdef CONFIG_PLAT_S3C24XX
1152 .config = &s3c24xx_gpiocfg_banka,
1154 .base = S3C2410_GPA(0),
1155 .owner = THIS_MODULE,
1158 .direction_input = s3c24xx_gpiolib_banka_input,
1159 .direction_output = s3c24xx_gpiolib_banka_output,
1163 .base = S3C2410_GPB(0),
1164 .owner = THIS_MODULE,
1170 .base = S3C2410_GPC(0),
1171 .owner = THIS_MODULE,
1177 .base = S3C2410_GPD(0),
1178 .owner = THIS_MODULE,
1184 .base = S3C2410_GPE(0),
1186 .owner = THIS_MODULE,
1191 .base = S3C2410_GPF(0),
1192 .owner = THIS_MODULE,
1195 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1198 .irq_base = IRQ_EINT8,
1200 .base = S3C2410_GPG(0),
1201 .owner = THIS_MODULE,
1204 .to_irq = samsung_gpiolib_to_irq,
1208 .base = S3C2410_GPH(0),
1209 .owner = THIS_MODULE,
1214 /* GPIOS for the S3C2443 and later devices. */
1216 .base = S3C2440_GPJCON,
1218 .base = S3C2410_GPJ(0),
1219 .owner = THIS_MODULE,
1224 .base = S3C2443_GPKCON,
1226 .base = S3C2410_GPK(0),
1227 .owner = THIS_MODULE,
1232 .base = S3C2443_GPLCON,
1234 .base = S3C2410_GPL(0),
1235 .owner = THIS_MODULE,
1240 .base = S3C2443_GPMCON,
1242 .base = S3C2410_GPM(0),
1243 .owner = THIS_MODULE,
1252 * GPIO bank summary:
1254 * Bank GPIOs Style SlpCon ExtInt Group
1260 * F 16 2Bit Yes 4 [1]
1262 * H 10 4Bit[2] Yes 6
1263 * I 16 2Bit Yes None
1264 * J 12 2Bit Yes None
1265 * K 16 4Bit[2] No None
1266 * L 15 4Bit[2] No None
1267 * M 6 4Bit No IRQ_EINT
1268 * N 16 2Bit No IRQ_EINT
1273 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1274 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1277 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1278 #ifdef CONFIG_PLAT_S3C64XX
1281 .base = S3C64XX_GPA(0),
1282 .ngpio = S3C64XX_GPIO_A_NR,
1287 .base = S3C64XX_GPB(0),
1288 .ngpio = S3C64XX_GPIO_B_NR,
1293 .base = S3C64XX_GPC(0),
1294 .ngpio = S3C64XX_GPIO_C_NR,
1299 .base = S3C64XX_GPD(0),
1300 .ngpio = S3C64XX_GPIO_D_NR,
1304 .config = &samsung_gpio_cfgs[0],
1306 .base = S3C64XX_GPE(0),
1307 .ngpio = S3C64XX_GPIO_E_NR,
1311 .base = S3C64XX_GPG_BASE,
1313 .base = S3C64XX_GPG(0),
1314 .ngpio = S3C64XX_GPIO_G_NR,
1318 .base = S3C64XX_GPM_BASE,
1319 .config = &samsung_gpio_cfgs[1],
1321 .base = S3C64XX_GPM(0),
1322 .ngpio = S3C64XX_GPIO_M_NR,
1324 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1330 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1331 #ifdef CONFIG_PLAT_S3C64XX
1333 .base = S3C64XX_GPH_BASE + 0x4,
1335 .base = S3C64XX_GPH(0),
1336 .ngpio = S3C64XX_GPIO_H_NR,
1340 .base = S3C64XX_GPK_BASE + 0x4,
1341 .config = &samsung_gpio_cfgs[0],
1343 .base = S3C64XX_GPK(0),
1344 .ngpio = S3C64XX_GPIO_K_NR,
1348 .base = S3C64XX_GPL_BASE + 0x4,
1349 .config = &samsung_gpio_cfgs[1],
1351 .base = S3C64XX_GPL(0),
1352 .ngpio = S3C64XX_GPIO_L_NR,
1354 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1360 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1361 #ifdef CONFIG_PLAT_S3C64XX
1363 .base = S3C64XX_GPF_BASE,
1364 .config = &samsung_gpio_cfgs[6],
1366 .base = S3C64XX_GPF(0),
1367 .ngpio = S3C64XX_GPIO_F_NR,
1371 .config = &samsung_gpio_cfgs[7],
1373 .base = S3C64XX_GPI(0),
1374 .ngpio = S3C64XX_GPIO_I_NR,
1378 .config = &samsung_gpio_cfgs[7],
1380 .base = S3C64XX_GPJ(0),
1381 .ngpio = S3C64XX_GPIO_J_NR,
1385 .config = &samsung_gpio_cfgs[6],
1387 .base = S3C64XX_GPO(0),
1388 .ngpio = S3C64XX_GPIO_O_NR,
1392 .config = &samsung_gpio_cfgs[6],
1394 .base = S3C64XX_GPP(0),
1395 .ngpio = S3C64XX_GPIO_P_NR,
1399 .config = &samsung_gpio_cfgs[6],
1401 .base = S3C64XX_GPQ(0),
1402 .ngpio = S3C64XX_GPIO_Q_NR,
1406 .base = S3C64XX_GPN_BASE,
1407 .irq_base = IRQ_EINT(0),
1408 .config = &samsung_gpio_cfgs[5],
1410 .base = S3C64XX_GPN(0),
1411 .ngpio = S3C64XX_GPIO_N_NR,
1413 .to_irq = samsung_gpiolib_to_irq,
1420 * S5P6440 GPIO bank summary:
1422 * Bank GPIOs Style SlpCon ExtInt Group
1426 * F 2 2Bit Yes 4 [1]
1428 * H 10 4Bit[2] Yes 6
1429 * I 16 2Bit Yes None
1430 * J 12 2Bit Yes None
1431 * N 16 2Bit No IRQ_EINT
1433 * R 15 4Bit[2] Yes 8
1436 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1437 #ifdef CONFIG_CPU_S5P6440
1440 .base = S5P6440_GPA(0),
1441 .ngpio = S5P6440_GPIO_A_NR,
1446 .base = S5P6440_GPB(0),
1447 .ngpio = S5P6440_GPIO_B_NR,
1452 .base = S5P6440_GPC(0),
1453 .ngpio = S5P6440_GPIO_C_NR,
1457 .base = S5P64X0_GPG_BASE,
1459 .base = S5P6440_GPG(0),
1460 .ngpio = S5P6440_GPIO_G_NR,
1467 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1468 #ifdef CONFIG_CPU_S5P6440
1470 .base = S5P64X0_GPH_BASE + 0x4,
1472 .base = S5P6440_GPH(0),
1473 .ngpio = S5P6440_GPIO_H_NR,
1480 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1481 #ifdef CONFIG_CPU_S5P6440
1483 .base = S5P64X0_GPR_BASE + 0x4,
1484 .config = &s5p64x0_gpio_cfg_rbank,
1486 .base = S5P6440_GPR(0),
1487 .ngpio = S5P6440_GPIO_R_NR,
1494 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1495 #ifdef CONFIG_CPU_S5P6440
1497 .base = S5P64X0_GPF_BASE,
1498 .config = &samsung_gpio_cfgs[6],
1500 .base = S5P6440_GPF(0),
1501 .ngpio = S5P6440_GPIO_F_NR,
1505 .base = S5P64X0_GPI_BASE,
1506 .config = &samsung_gpio_cfgs[4],
1508 .base = S5P6440_GPI(0),
1509 .ngpio = S5P6440_GPIO_I_NR,
1513 .base = S5P64X0_GPJ_BASE,
1514 .config = &samsung_gpio_cfgs[4],
1516 .base = S5P6440_GPJ(0),
1517 .ngpio = S5P6440_GPIO_J_NR,
1521 .base = S5P64X0_GPN_BASE,
1522 .config = &samsung_gpio_cfgs[5],
1524 .base = S5P6440_GPN(0),
1525 .ngpio = S5P6440_GPIO_N_NR,
1529 .base = S5P64X0_GPP_BASE,
1530 .config = &samsung_gpio_cfgs[6],
1532 .base = S5P6440_GPP(0),
1533 .ngpio = S5P6440_GPIO_P_NR,
1541 * S5P6450 GPIO bank summary:
1543 * Bank GPIOs Style SlpCon ExtInt Group
1549 * G 14 4Bit[2] Yes 5
1550 * H 10 4Bit[2] Yes 6
1551 * I 16 2Bit Yes None
1552 * J 12 2Bit Yes None
1554 * N 16 2Bit No IRQ_EINT
1556 * Q 14 2Bit Yes None
1557 * R 15 4Bit[2] Yes None
1560 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1561 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1564 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1565 #ifdef CONFIG_CPU_S5P6450
1568 .base = S5P6450_GPA(0),
1569 .ngpio = S5P6450_GPIO_A_NR,
1574 .base = S5P6450_GPB(0),
1575 .ngpio = S5P6450_GPIO_B_NR,
1580 .base = S5P6450_GPC(0),
1581 .ngpio = S5P6450_GPIO_C_NR,
1586 .base = S5P6450_GPD(0),
1587 .ngpio = S5P6450_GPIO_D_NR,
1591 .base = S5P6450_GPK_BASE,
1593 .base = S5P6450_GPK(0),
1594 .ngpio = S5P6450_GPIO_K_NR,
1601 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1602 #ifdef CONFIG_CPU_S5P6450
1604 .base = S5P64X0_GPG_BASE + 0x4,
1606 .base = S5P6450_GPG(0),
1607 .ngpio = S5P6450_GPIO_G_NR,
1611 .base = S5P64X0_GPH_BASE + 0x4,
1613 .base = S5P6450_GPH(0),
1614 .ngpio = S5P6450_GPIO_H_NR,
1621 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1622 #ifdef CONFIG_CPU_S5P6450
1624 .base = S5P64X0_GPR_BASE + 0x4,
1625 .config = &s5p64x0_gpio_cfg_rbank,
1627 .base = S5P6450_GPR(0),
1628 .ngpio = S5P6450_GPIO_R_NR,
1635 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1636 #ifdef CONFIG_CPU_S5P6450
1638 .base = S5P64X0_GPF_BASE,
1639 .config = &samsung_gpio_cfgs[6],
1641 .base = S5P6450_GPF(0),
1642 .ngpio = S5P6450_GPIO_F_NR,
1646 .base = S5P64X0_GPI_BASE,
1647 .config = &samsung_gpio_cfgs[4],
1649 .base = S5P6450_GPI(0),
1650 .ngpio = S5P6450_GPIO_I_NR,
1654 .base = S5P64X0_GPJ_BASE,
1655 .config = &samsung_gpio_cfgs[4],
1657 .base = S5P6450_GPJ(0),
1658 .ngpio = S5P6450_GPIO_J_NR,
1662 .base = S5P64X0_GPN_BASE,
1663 .config = &samsung_gpio_cfgs[5],
1665 .base = S5P6450_GPN(0),
1666 .ngpio = S5P6450_GPIO_N_NR,
1670 .base = S5P64X0_GPP_BASE,
1671 .config = &samsung_gpio_cfgs[6],
1673 .base = S5P6450_GPP(0),
1674 .ngpio = S5P6450_GPIO_P_NR,
1678 .base = S5P6450_GPQ_BASE,
1679 .config = &samsung_gpio_cfgs[5],
1681 .base = S5P6450_GPQ(0),
1682 .ngpio = S5P6450_GPIO_Q_NR,
1686 .base = S5P6450_GPS_BASE,
1687 .config = &samsung_gpio_cfgs[6],
1689 .base = S5P6450_GPS(0),
1690 .ngpio = S5P6450_GPIO_S_NR,
1698 * S5PC100 GPIO bank summary:
1700 * Bank GPIOs Style INT Type
1701 * A0 8 4Bit GPIO_INT0
1702 * A1 5 4Bit GPIO_INT1
1703 * B 8 4Bit GPIO_INT2
1704 * C 5 4Bit GPIO_INT3
1705 * D 7 4Bit GPIO_INT4
1706 * E0 8 4Bit GPIO_INT5
1707 * E1 6 4Bit GPIO_INT6
1708 * F0 8 4Bit GPIO_INT7
1709 * F1 8 4Bit GPIO_INT8
1710 * F2 8 4Bit GPIO_INT9
1711 * F3 4 4Bit GPIO_INT10
1712 * G0 8 4Bit GPIO_INT11
1713 * G1 3 4Bit GPIO_INT12
1714 * G2 7 4Bit GPIO_INT13
1715 * G3 7 4Bit GPIO_INT14
1716 * H0 8 4Bit WKUP_INT
1717 * H1 8 4Bit WKUP_INT
1718 * H2 8 4Bit WKUP_INT
1719 * H3 8 4Bit WKUP_INT
1720 * I 8 4Bit GPIO_INT15
1721 * J0 8 4Bit GPIO_INT16
1722 * J1 5 4Bit GPIO_INT17
1723 * J2 8 4Bit GPIO_INT18
1724 * J3 8 4Bit GPIO_INT19
1725 * J4 4 4Bit GPIO_INT20
1736 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1737 #ifdef CONFIG_CPU_S5PC100
1740 .base = S5PC100_GPA0(0),
1741 .ngpio = S5PC100_GPIO_A0_NR,
1746 .base = S5PC100_GPA1(0),
1747 .ngpio = S5PC100_GPIO_A1_NR,
1752 .base = S5PC100_GPB(0),
1753 .ngpio = S5PC100_GPIO_B_NR,
1758 .base = S5PC100_GPC(0),
1759 .ngpio = S5PC100_GPIO_C_NR,
1764 .base = S5PC100_GPD(0),
1765 .ngpio = S5PC100_GPIO_D_NR,
1770 .base = S5PC100_GPE0(0),
1771 .ngpio = S5PC100_GPIO_E0_NR,
1776 .base = S5PC100_GPE1(0),
1777 .ngpio = S5PC100_GPIO_E1_NR,
1782 .base = S5PC100_GPF0(0),
1783 .ngpio = S5PC100_GPIO_F0_NR,
1788 .base = S5PC100_GPF1(0),
1789 .ngpio = S5PC100_GPIO_F1_NR,
1794 .base = S5PC100_GPF2(0),
1795 .ngpio = S5PC100_GPIO_F2_NR,
1800 .base = S5PC100_GPF3(0),
1801 .ngpio = S5PC100_GPIO_F3_NR,
1806 .base = S5PC100_GPG0(0),
1807 .ngpio = S5PC100_GPIO_G0_NR,
1812 .base = S5PC100_GPG1(0),
1813 .ngpio = S5PC100_GPIO_G1_NR,
1818 .base = S5PC100_GPG2(0),
1819 .ngpio = S5PC100_GPIO_G2_NR,
1824 .base = S5PC100_GPG3(0),
1825 .ngpio = S5PC100_GPIO_G3_NR,
1830 .base = S5PC100_GPI(0),
1831 .ngpio = S5PC100_GPIO_I_NR,
1836 .base = S5PC100_GPJ0(0),
1837 .ngpio = S5PC100_GPIO_J0_NR,
1842 .base = S5PC100_GPJ1(0),
1843 .ngpio = S5PC100_GPIO_J1_NR,
1848 .base = S5PC100_GPJ2(0),
1849 .ngpio = S5PC100_GPIO_J2_NR,
1854 .base = S5PC100_GPJ3(0),
1855 .ngpio = S5PC100_GPIO_J3_NR,
1860 .base = S5PC100_GPJ4(0),
1861 .ngpio = S5PC100_GPIO_J4_NR,
1866 .base = S5PC100_GPK0(0),
1867 .ngpio = S5PC100_GPIO_K0_NR,
1872 .base = S5PC100_GPK1(0),
1873 .ngpio = S5PC100_GPIO_K1_NR,
1878 .base = S5PC100_GPK2(0),
1879 .ngpio = S5PC100_GPIO_K2_NR,
1884 .base = S5PC100_GPK3(0),
1885 .ngpio = S5PC100_GPIO_K3_NR,
1890 .base = S5PC100_GPL0(0),
1891 .ngpio = S5PC100_GPIO_L0_NR,
1896 .base = S5PC100_GPL1(0),
1897 .ngpio = S5PC100_GPIO_L1_NR,
1902 .base = S5PC100_GPL2(0),
1903 .ngpio = S5PC100_GPIO_L2_NR,
1908 .base = S5PC100_GPL3(0),
1909 .ngpio = S5PC100_GPIO_L3_NR,
1914 .base = S5PC100_GPL4(0),
1915 .ngpio = S5PC100_GPIO_L4_NR,
1919 .base = (S5P_VA_GPIO + 0xC00),
1920 .irq_base = IRQ_EINT(0),
1922 .base = S5PC100_GPH0(0),
1923 .ngpio = S5PC100_GPIO_H0_NR,
1925 .to_irq = samsung_gpiolib_to_irq,
1928 .base = (S5P_VA_GPIO + 0xC20),
1929 .irq_base = IRQ_EINT(8),
1931 .base = S5PC100_GPH1(0),
1932 .ngpio = S5PC100_GPIO_H1_NR,
1934 .to_irq = samsung_gpiolib_to_irq,
1937 .base = (S5P_VA_GPIO + 0xC40),
1938 .irq_base = IRQ_EINT(16),
1940 .base = S5PC100_GPH2(0),
1941 .ngpio = S5PC100_GPIO_H2_NR,
1943 .to_irq = samsung_gpiolib_to_irq,
1946 .base = (S5P_VA_GPIO + 0xC60),
1947 .irq_base = IRQ_EINT(24),
1949 .base = S5PC100_GPH3(0),
1950 .ngpio = S5PC100_GPIO_H3_NR,
1952 .to_irq = samsung_gpiolib_to_irq,
1959 * Followings are the gpio banks in S5PV210/S5PC110
1961 * The 'config' member when left to NULL, is initialized to the default
1962 * structure samsung_gpio_cfgs[3] in the init function below.
1964 * The 'base' member is also initialized in the init function below.
1965 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1966 * uses the above macro and depends on the banks being listed in order here.
1969 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1970 #ifdef CONFIG_CPU_S5PV210
1973 .base = S5PV210_GPA0(0),
1974 .ngpio = S5PV210_GPIO_A0_NR,
1979 .base = S5PV210_GPA1(0),
1980 .ngpio = S5PV210_GPIO_A1_NR,
1985 .base = S5PV210_GPB(0),
1986 .ngpio = S5PV210_GPIO_B_NR,
1991 .base = S5PV210_GPC0(0),
1992 .ngpio = S5PV210_GPIO_C0_NR,
1997 .base = S5PV210_GPC1(0),
1998 .ngpio = S5PV210_GPIO_C1_NR,
2003 .base = S5PV210_GPD0(0),
2004 .ngpio = S5PV210_GPIO_D0_NR,
2009 .base = S5PV210_GPD1(0),
2010 .ngpio = S5PV210_GPIO_D1_NR,
2015 .base = S5PV210_GPE0(0),
2016 .ngpio = S5PV210_GPIO_E0_NR,
2021 .base = S5PV210_GPE1(0),
2022 .ngpio = S5PV210_GPIO_E1_NR,
2027 .base = S5PV210_GPF0(0),
2028 .ngpio = S5PV210_GPIO_F0_NR,
2033 .base = S5PV210_GPF1(0),
2034 .ngpio = S5PV210_GPIO_F1_NR,
2039 .base = S5PV210_GPF2(0),
2040 .ngpio = S5PV210_GPIO_F2_NR,
2045 .base = S5PV210_GPF3(0),
2046 .ngpio = S5PV210_GPIO_F3_NR,
2051 .base = S5PV210_GPG0(0),
2052 .ngpio = S5PV210_GPIO_G0_NR,
2057 .base = S5PV210_GPG1(0),
2058 .ngpio = S5PV210_GPIO_G1_NR,
2063 .base = S5PV210_GPG2(0),
2064 .ngpio = S5PV210_GPIO_G2_NR,
2069 .base = S5PV210_GPG3(0),
2070 .ngpio = S5PV210_GPIO_G3_NR,
2075 .base = S5PV210_GPI(0),
2076 .ngpio = S5PV210_GPIO_I_NR,
2081 .base = S5PV210_GPJ0(0),
2082 .ngpio = S5PV210_GPIO_J0_NR,
2087 .base = S5PV210_GPJ1(0),
2088 .ngpio = S5PV210_GPIO_J1_NR,
2093 .base = S5PV210_GPJ2(0),
2094 .ngpio = S5PV210_GPIO_J2_NR,
2099 .base = S5PV210_GPJ3(0),
2100 .ngpio = S5PV210_GPIO_J3_NR,
2105 .base = S5PV210_GPJ4(0),
2106 .ngpio = S5PV210_GPIO_J4_NR,
2111 .base = S5PV210_MP01(0),
2112 .ngpio = S5PV210_GPIO_MP01_NR,
2117 .base = S5PV210_MP02(0),
2118 .ngpio = S5PV210_GPIO_MP02_NR,
2123 .base = S5PV210_MP03(0),
2124 .ngpio = S5PV210_GPIO_MP03_NR,
2129 .base = S5PV210_MP04(0),
2130 .ngpio = S5PV210_GPIO_MP04_NR,
2135 .base = S5PV210_MP05(0),
2136 .ngpio = S5PV210_GPIO_MP05_NR,
2140 .base = (S5P_VA_GPIO + 0xC00),
2141 .irq_base = IRQ_EINT(0),
2143 .base = S5PV210_GPH0(0),
2144 .ngpio = S5PV210_GPIO_H0_NR,
2146 .to_irq = samsung_gpiolib_to_irq,
2149 .base = (S5P_VA_GPIO + 0xC20),
2150 .irq_base = IRQ_EINT(8),
2152 .base = S5PV210_GPH1(0),
2153 .ngpio = S5PV210_GPIO_H1_NR,
2155 .to_irq = samsung_gpiolib_to_irq,
2158 .base = (S5P_VA_GPIO + 0xC40),
2159 .irq_base = IRQ_EINT(16),
2161 .base = S5PV210_GPH2(0),
2162 .ngpio = S5PV210_GPIO_H2_NR,
2164 .to_irq = samsung_gpiolib_to_irq,
2167 .base = (S5P_VA_GPIO + 0xC60),
2168 .irq_base = IRQ_EINT(24),
2170 .base = S5PV210_GPH3(0),
2171 .ngpio = S5PV210_GPIO_H3_NR,
2173 .to_irq = samsung_gpiolib_to_irq,
2180 * Followings are the gpio banks in EXYNOS SoCs
2182 * The 'config' member when left to NULL, is initialized to the default
2183 * structure exynos_gpio_cfg in the init function below.
2185 * The 'base' member is also initialized in the init function below.
2186 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2187 * uses the above macro and depends on the banks being listed in order here.
2190 #ifdef CONFIG_ARCH_EXYNOS4
2191 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2194 .base = EXYNOS4_GPA0(0),
2195 .ngpio = EXYNOS4_GPIO_A0_NR,
2200 .base = EXYNOS4_GPA1(0),
2201 .ngpio = EXYNOS4_GPIO_A1_NR,
2206 .base = EXYNOS4_GPB(0),
2207 .ngpio = EXYNOS4_GPIO_B_NR,
2212 .base = EXYNOS4_GPC0(0),
2213 .ngpio = EXYNOS4_GPIO_C0_NR,
2218 .base = EXYNOS4_GPC1(0),
2219 .ngpio = EXYNOS4_GPIO_C1_NR,
2224 .base = EXYNOS4_GPD0(0),
2225 .ngpio = EXYNOS4_GPIO_D0_NR,
2230 .base = EXYNOS4_GPD1(0),
2231 .ngpio = EXYNOS4_GPIO_D1_NR,
2236 .base = EXYNOS4_GPE0(0),
2237 .ngpio = EXYNOS4_GPIO_E0_NR,
2242 .base = EXYNOS4_GPE1(0),
2243 .ngpio = EXYNOS4_GPIO_E1_NR,
2248 .base = EXYNOS4_GPE2(0),
2249 .ngpio = EXYNOS4_GPIO_E2_NR,
2254 .base = EXYNOS4_GPE3(0),
2255 .ngpio = EXYNOS4_GPIO_E3_NR,
2260 .base = EXYNOS4_GPE4(0),
2261 .ngpio = EXYNOS4_GPIO_E4_NR,
2266 .base = EXYNOS4_GPF0(0),
2267 .ngpio = EXYNOS4_GPIO_F0_NR,
2272 .base = EXYNOS4_GPF1(0),
2273 .ngpio = EXYNOS4_GPIO_F1_NR,
2278 .base = EXYNOS4_GPF2(0),
2279 .ngpio = EXYNOS4_GPIO_F2_NR,
2284 .base = EXYNOS4_GPF3(0),
2285 .ngpio = EXYNOS4_GPIO_F3_NR,
2292 #ifdef CONFIG_ARCH_EXYNOS4
2293 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2296 .base = EXYNOS4_GPJ0(0),
2297 .ngpio = EXYNOS4_GPIO_J0_NR,
2302 .base = EXYNOS4_GPJ1(0),
2303 .ngpio = EXYNOS4_GPIO_J1_NR,
2308 .base = EXYNOS4_GPK0(0),
2309 .ngpio = EXYNOS4_GPIO_K0_NR,
2314 .base = EXYNOS4_GPK1(0),
2315 .ngpio = EXYNOS4_GPIO_K1_NR,
2320 .base = EXYNOS4_GPK2(0),
2321 .ngpio = EXYNOS4_GPIO_K2_NR,
2326 .base = EXYNOS4_GPK3(0),
2327 .ngpio = EXYNOS4_GPIO_K3_NR,
2332 .base = EXYNOS4_GPL0(0),
2333 .ngpio = EXYNOS4_GPIO_L0_NR,
2338 .base = EXYNOS4_GPL1(0),
2339 .ngpio = EXYNOS4_GPIO_L1_NR,
2344 .base = EXYNOS4_GPL2(0),
2345 .ngpio = EXYNOS4_GPIO_L2_NR,
2349 .config = &samsung_gpio_cfgs[8],
2351 .base = EXYNOS4_GPY0(0),
2352 .ngpio = EXYNOS4_GPIO_Y0_NR,
2356 .config = &samsung_gpio_cfgs[8],
2358 .base = EXYNOS4_GPY1(0),
2359 .ngpio = EXYNOS4_GPIO_Y1_NR,
2363 .config = &samsung_gpio_cfgs[8],
2365 .base = EXYNOS4_GPY2(0),
2366 .ngpio = EXYNOS4_GPIO_Y2_NR,
2370 .config = &samsung_gpio_cfgs[8],
2372 .base = EXYNOS4_GPY3(0),
2373 .ngpio = EXYNOS4_GPIO_Y3_NR,
2377 .config = &samsung_gpio_cfgs[8],
2379 .base = EXYNOS4_GPY4(0),
2380 .ngpio = EXYNOS4_GPIO_Y4_NR,
2384 .config = &samsung_gpio_cfgs[8],
2386 .base = EXYNOS4_GPY5(0),
2387 .ngpio = EXYNOS4_GPIO_Y5_NR,
2391 .config = &samsung_gpio_cfgs[8],
2393 .base = EXYNOS4_GPY6(0),
2394 .ngpio = EXYNOS4_GPIO_Y6_NR,
2398 .config = &samsung_gpio_cfgs[9],
2399 .irq_base = IRQ_EINT(0),
2401 .base = EXYNOS4_GPX0(0),
2402 .ngpio = EXYNOS4_GPIO_X0_NR,
2404 .to_irq = samsung_gpiolib_to_irq,
2407 .config = &samsung_gpio_cfgs[9],
2408 .irq_base = IRQ_EINT(8),
2410 .base = EXYNOS4_GPX1(0),
2411 .ngpio = EXYNOS4_GPIO_X1_NR,
2413 .to_irq = samsung_gpiolib_to_irq,
2416 .config = &samsung_gpio_cfgs[9],
2417 .irq_base = IRQ_EINT(16),
2419 .base = EXYNOS4_GPX2(0),
2420 .ngpio = EXYNOS4_GPIO_X2_NR,
2422 .to_irq = samsung_gpiolib_to_irq,
2425 .config = &samsung_gpio_cfgs[9],
2426 .irq_base = IRQ_EINT(24),
2428 .base = EXYNOS4_GPX3(0),
2429 .ngpio = EXYNOS4_GPIO_X3_NR,
2431 .to_irq = samsung_gpiolib_to_irq,
2437 #ifdef CONFIG_ARCH_EXYNOS4
2438 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2441 .base = EXYNOS4_GPZ(0),
2442 .ngpio = EXYNOS4_GPIO_Z_NR,
2449 #ifdef CONFIG_ARCH_EXYNOS5
2450 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2453 .base = EXYNOS5_GPA0(0),
2454 .ngpio = EXYNOS5_GPIO_A0_NR,
2459 .base = EXYNOS5_GPA1(0),
2460 .ngpio = EXYNOS5_GPIO_A1_NR,
2465 .base = EXYNOS5_GPA2(0),
2466 .ngpio = EXYNOS5_GPIO_A2_NR,
2471 .base = EXYNOS5_GPB0(0),
2472 .ngpio = EXYNOS5_GPIO_B0_NR,
2477 .base = EXYNOS5_GPB1(0),
2478 .ngpio = EXYNOS5_GPIO_B1_NR,
2483 .base = EXYNOS5_GPB2(0),
2484 .ngpio = EXYNOS5_GPIO_B2_NR,
2489 .base = EXYNOS5_GPB3(0),
2490 .ngpio = EXYNOS5_GPIO_B3_NR,
2495 .base = EXYNOS5_GPC0(0),
2496 .ngpio = EXYNOS5_GPIO_C0_NR,
2501 .base = EXYNOS5_GPC1(0),
2502 .ngpio = EXYNOS5_GPIO_C1_NR,
2507 .base = EXYNOS5_GPC2(0),
2508 .ngpio = EXYNOS5_GPIO_C2_NR,
2513 .base = EXYNOS5_GPC3(0),
2514 .ngpio = EXYNOS5_GPIO_C3_NR,
2519 .base = EXYNOS5_GPD0(0),
2520 .ngpio = EXYNOS5_GPIO_D0_NR,
2525 .base = EXYNOS5_GPD1(0),
2526 .ngpio = EXYNOS5_GPIO_D1_NR,
2531 .base = EXYNOS5_GPY0(0),
2532 .ngpio = EXYNOS5_GPIO_Y0_NR,
2537 .base = EXYNOS5_GPY1(0),
2538 .ngpio = EXYNOS5_GPIO_Y1_NR,
2543 .base = EXYNOS5_GPY2(0),
2544 .ngpio = EXYNOS5_GPIO_Y2_NR,
2549 .base = EXYNOS5_GPY3(0),
2550 .ngpio = EXYNOS5_GPIO_Y3_NR,
2555 .base = EXYNOS5_GPY4(0),
2556 .ngpio = EXYNOS5_GPIO_Y4_NR,
2561 .base = EXYNOS5_GPY5(0),
2562 .ngpio = EXYNOS5_GPIO_Y5_NR,
2567 .base = EXYNOS5_GPY6(0),
2568 .ngpio = EXYNOS5_GPIO_Y6_NR,
2573 .base = EXYNOS5_GPC4(0),
2574 .ngpio = EXYNOS5_GPIO_C4_NR,
2578 .config = &samsung_gpio_cfgs[9],
2579 .irq_base = IRQ_EINT(0),
2581 .base = EXYNOS5_GPX0(0),
2582 .ngpio = EXYNOS5_GPIO_X0_NR,
2584 .to_irq = samsung_gpiolib_to_irq,
2587 .config = &samsung_gpio_cfgs[9],
2588 .irq_base = IRQ_EINT(8),
2590 .base = EXYNOS5_GPX1(0),
2591 .ngpio = EXYNOS5_GPIO_X1_NR,
2593 .to_irq = samsung_gpiolib_to_irq,
2596 .config = &samsung_gpio_cfgs[9],
2597 .irq_base = IRQ_EINT(16),
2599 .base = EXYNOS5_GPX2(0),
2600 .ngpio = EXYNOS5_GPIO_X2_NR,
2602 .to_irq = samsung_gpiolib_to_irq,
2605 .config = &samsung_gpio_cfgs[9],
2606 .irq_base = IRQ_EINT(24),
2608 .base = EXYNOS5_GPX3(0),
2609 .ngpio = EXYNOS5_GPIO_X3_NR,
2611 .to_irq = samsung_gpiolib_to_irq,
2617 #ifdef CONFIG_ARCH_EXYNOS5
2618 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2621 .base = EXYNOS5_GPE0(0),
2622 .ngpio = EXYNOS5_GPIO_E0_NR,
2627 .base = EXYNOS5_GPE1(0),
2628 .ngpio = EXYNOS5_GPIO_E1_NR,
2633 .base = EXYNOS5_GPF0(0),
2634 .ngpio = EXYNOS5_GPIO_F0_NR,
2639 .base = EXYNOS5_GPF1(0),
2640 .ngpio = EXYNOS5_GPIO_F1_NR,
2645 .base = EXYNOS5_GPG0(0),
2646 .ngpio = EXYNOS5_GPIO_G0_NR,
2651 .base = EXYNOS5_GPG1(0),
2652 .ngpio = EXYNOS5_GPIO_G1_NR,
2657 .base = EXYNOS5_GPG2(0),
2658 .ngpio = EXYNOS5_GPIO_G2_NR,
2663 .base = EXYNOS5_GPH0(0),
2664 .ngpio = EXYNOS5_GPIO_H0_NR,
2669 .base = EXYNOS5_GPH1(0),
2670 .ngpio = EXYNOS5_GPIO_H1_NR,
2678 #ifdef CONFIG_ARCH_EXYNOS5
2679 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2682 .base = EXYNOS5_GPV0(0),
2683 .ngpio = EXYNOS5_GPIO_V0_NR,
2688 .base = EXYNOS5_GPV1(0),
2689 .ngpio = EXYNOS5_GPIO_V1_NR,
2694 .base = EXYNOS5_GPV2(0),
2695 .ngpio = EXYNOS5_GPIO_V2_NR,
2700 .base = EXYNOS5_GPV3(0),
2701 .ngpio = EXYNOS5_GPIO_V3_NR,
2706 .base = EXYNOS5_GPV4(0),
2707 .ngpio = EXYNOS5_GPIO_V4_NR,
2714 #ifdef CONFIG_ARCH_EXYNOS5
2715 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2718 .base = EXYNOS5_GPZ(0),
2719 .ngpio = EXYNOS5_GPIO_Z_NR,
2727 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2728 static int exynos_gpio_xlate(struct gpio_chip *gc,
2729 const struct of_phandle_args *gpiospec, u32 *flags)
2733 if (WARN_ON(gc->of_gpio_n_cells < 4))
2736 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2739 if (gpiospec->args[0] > gc->ngpio)
2742 pin = gc->base + gpiospec->args[0];
2744 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2745 pr_warn("gpio_xlate: failed to set pin function\n");
2746 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2747 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2748 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2749 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2752 *flags = gpiospec->args[2] >> 16;
2754 return gpiospec->args[0];
2757 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2758 { .compatible = "samsung,exynos4-gpio", },
2762 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2763 u64 base, u64 offset)
2765 struct gpio_chip *gc = &chip->chip;
2768 if (!of_have_populated_dt())
2771 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2772 gc->of_node = of_find_matching_node_by_address(NULL,
2773 exynos_gpio_dt_match, address);
2775 pr_info("gpio: device tree node not found for gpio controller"
2776 " with base address %08llx\n", address);
2779 gc->of_gpio_n_cells = 4;
2780 gc->of_xlate = exynos_gpio_xlate;
2782 #elif defined(CONFIG_ARCH_EXYNOS)
2783 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2784 u64 base, u64 offset)
2788 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2790 static __init void exynos4_gpiolib_init(void)
2792 #ifdef CONFIG_CPU_EXYNOS4210
2793 struct samsung_gpio_chip *chip;
2795 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2797 void __iomem *gpx_base;
2800 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2801 if (gpio_base1 == NULL) {
2802 pr_err("unable to ioremap for gpio_base1\n");
2806 chip = exynos4_gpios_1;
2807 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2809 for (i = 0; i < nr_chips; i++, chip++) {
2810 if (!chip->config) {
2811 chip->config = &exynos_gpio_cfg;
2812 chip->group = group++;
2814 exynos_gpiolib_attach_ofnode(chip,
2815 EXYNOS4_PA_GPIO1, i * 0x20);
2817 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2818 nr_chips, gpio_base1);
2821 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2822 if (gpio_base2 == NULL) {
2823 pr_err("unable to ioremap for gpio_base2\n");
2827 /* need to set base address for gpx */
2828 chip = &exynos4_gpios_2[16];
2829 gpx_base = gpio_base2 + 0xC00;
2830 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2831 chip->base = gpx_base;
2833 chip = exynos4_gpios_2;
2834 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2836 for (i = 0; i < nr_chips; i++, chip++) {
2837 if (!chip->config) {
2838 chip->config = &exynos_gpio_cfg;
2839 chip->group = group++;
2841 exynos_gpiolib_attach_ofnode(chip,
2842 EXYNOS4_PA_GPIO2, i * 0x20);
2844 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2845 nr_chips, gpio_base2);
2848 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2849 if (gpio_base3 == NULL) {
2850 pr_err("unable to ioremap for gpio_base3\n");
2854 chip = exynos4_gpios_3;
2855 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2857 for (i = 0; i < nr_chips; i++, chip++) {
2858 if (!chip->config) {
2859 chip->config = &exynos_gpio_cfg;
2860 chip->group = group++;
2862 exynos_gpiolib_attach_ofnode(chip,
2863 EXYNOS4_PA_GPIO3, i * 0x20);
2865 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2866 nr_chips, gpio_base3);
2868 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2869 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2870 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2876 iounmap(gpio_base2);
2878 iounmap(gpio_base1);
2881 #endif /* CONFIG_CPU_EXYNOS4210 */
2884 static __init void exynos5_gpiolib_init(void)
2886 #ifdef CONFIG_SOC_EXYNOS5250
2887 struct samsung_gpio_chip *chip;
2889 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2891 void __iomem *gpx_base;
2894 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2895 if (gpio_base1 == NULL) {
2896 pr_err("unable to ioremap for gpio_base1\n");
2900 /* need to set base address for gpc4 */
2901 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2903 /* need to set base address for gpx */
2904 chip = &exynos5_gpios_1[21];
2905 gpx_base = gpio_base1 + 0xC00;
2906 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2907 chip->base = gpx_base;
2909 chip = exynos5_gpios_1;
2910 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2912 for (i = 0; i < nr_chips; i++, chip++) {
2913 if (!chip->config) {
2914 chip->config = &exynos_gpio_cfg;
2915 chip->group = group++;
2917 exynos_gpiolib_attach_ofnode(chip,
2918 EXYNOS5_PA_GPIO1, i * 0x20);
2920 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2921 nr_chips, gpio_base1);
2924 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2925 if (gpio_base2 == NULL) {
2926 pr_err("unable to ioremap for gpio_base2\n");
2930 chip = exynos5_gpios_2;
2931 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2933 for (i = 0; i < nr_chips; i++, chip++) {
2934 if (!chip->config) {
2935 chip->config = &exynos_gpio_cfg;
2936 chip->group = group++;
2938 exynos_gpiolib_attach_ofnode(chip,
2939 EXYNOS5_PA_GPIO2, i * 0x20);
2941 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2942 nr_chips, gpio_base2);
2945 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2946 if (gpio_base3 == NULL) {
2947 pr_err("unable to ioremap for gpio_base3\n");
2951 /* need to set base address for gpv */
2952 exynos5_gpios_3[0].base = gpio_base3;
2953 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2954 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2955 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2956 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2958 chip = exynos5_gpios_3;
2959 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2961 for (i = 0; i < nr_chips; i++, chip++) {
2962 if (!chip->config) {
2963 chip->config = &exynos_gpio_cfg;
2964 chip->group = group++;
2966 exynos_gpiolib_attach_ofnode(chip,
2967 EXYNOS5_PA_GPIO3, i * 0x20);
2969 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2970 nr_chips, gpio_base3);
2973 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2974 if (gpio_base4 == NULL) {
2975 pr_err("unable to ioremap for gpio_base4\n");
2979 chip = exynos5_gpios_4;
2980 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2982 for (i = 0; i < nr_chips; i++, chip++) {
2983 if (!chip->config) {
2984 chip->config = &exynos_gpio_cfg;
2985 chip->group = group++;
2987 exynos_gpiolib_attach_ofnode(chip,
2988 EXYNOS5_PA_GPIO4, i * 0x20);
2990 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2991 nr_chips, gpio_base4);
2995 iounmap(gpio_base3);
2997 iounmap(gpio_base2);
2999 iounmap(gpio_base1);
3003 #endif /* CONFIG_SOC_EXYNOS5250 */
3006 /* TODO: cleanup soc_is_* */
3007 static __init int samsung_gpiolib_init(void)
3009 struct samsung_gpio_chip *chip;
3013 #ifdef CONFIG_PINCTRL_SAMSUNG
3015 * This gpio driver includes support for device tree support and there
3016 * are platforms using it. In order to maintain compatibility with those
3017 * platforms, and to allow non-dt Exynos4210 platforms to use this
3018 * gpiolib support, a check is added to find out if there is a active
3019 * pin-controller driver support available. If it is available, this
3020 * gpiolib support is ignored and the gpiolib support available in
3021 * pin-controller driver is used. This is a temporary check and will go
3022 * away when all of the Exynos4210 platforms have switched to using
3023 * device tree and the pin-ctrl driver.
3025 struct device_node *pctrl_np;
3026 static const struct of_device_id exynos_pinctrl_ids[] = {
3027 { .compatible = "samsung,pinctrl-exynos4210", },
3028 { .compatible = "samsung,pinctrl-exynos4x12", },
3030 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3031 if (pctrl_np && of_device_is_available(pctrl_np))
3035 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3037 if (soc_is_s3c24xx()) {
3038 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3039 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3040 } else if (soc_is_s3c64xx()) {
3041 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3042 ARRAY_SIZE(s3c64xx_gpios_2bit),
3043 S3C64XX_VA_GPIO + 0xE0, 0x20);
3044 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3045 ARRAY_SIZE(s3c64xx_gpios_4bit),
3047 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3048 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3049 } else if (soc_is_s5p6440()) {
3050 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3051 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3052 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3053 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3054 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3055 ARRAY_SIZE(s5p6440_gpios_4bit2));
3056 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3057 ARRAY_SIZE(s5p6440_gpios_rbank));
3058 } else if (soc_is_s5p6450()) {
3059 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3060 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3061 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3062 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3063 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3064 ARRAY_SIZE(s5p6450_gpios_4bit2));
3065 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3066 ARRAY_SIZE(s5p6450_gpios_rbank));
3067 } else if (soc_is_s5pc100()) {
3069 chip = s5pc100_gpios_4bit;
3070 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3072 for (i = 0; i < nr_chips; i++, chip++) {
3073 if (!chip->config) {
3074 chip->config = &samsung_gpio_cfgs[3];
3075 chip->group = group++;
3078 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3079 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3080 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3082 } else if (soc_is_s5pv210()) {
3084 chip = s5pv210_gpios_4bit;
3085 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3087 for (i = 0; i < nr_chips; i++, chip++) {
3088 if (!chip->config) {
3089 chip->config = &samsung_gpio_cfgs[3];
3090 chip->group = group++;
3093 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3094 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3095 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3097 } else if (soc_is_exynos4210()) {
3098 exynos4_gpiolib_init();
3099 } else if (soc_is_exynos5250()) {
3100 exynos5_gpiolib_init();
3102 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3108 core_initcall(samsung_gpiolib_init);
3110 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3112 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3113 unsigned long flags;
3120 offset = pin - chip->chip.base;
3122 samsung_gpio_lock(chip, flags);
3123 ret = samsung_gpio_do_setcfg(chip, offset, config);
3124 samsung_gpio_unlock(chip, flags);
3128 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3130 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3135 for (; nr > 0; nr--, start++) {
3136 ret = s3c_gpio_cfgpin(start, cfg);
3143 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3145 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3146 unsigned int cfg, samsung_gpio_pull_t pull)
3150 for (; nr > 0; nr--, start++) {
3151 s3c_gpio_setpull(start, pull);
3152 ret = s3c_gpio_cfgpin(start, cfg);
3159 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3161 unsigned s3c_gpio_getcfg(unsigned int pin)
3163 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3164 unsigned long flags;
3169 offset = pin - chip->chip.base;
3171 samsung_gpio_lock(chip, flags);
3172 ret = samsung_gpio_do_getcfg(chip, offset);
3173 samsung_gpio_unlock(chip, flags);
3178 EXPORT_SYMBOL(s3c_gpio_getcfg);
3180 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3182 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3183 unsigned long flags;
3189 offset = pin - chip->chip.base;
3191 samsung_gpio_lock(chip, flags);
3192 ret = samsung_gpio_do_setpull(chip, offset, pull);
3193 samsung_gpio_unlock(chip, flags);
3197 EXPORT_SYMBOL(s3c_gpio_setpull);
3199 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3201 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3202 unsigned long flags;
3207 offset = pin - chip->chip.base;
3209 samsung_gpio_lock(chip, flags);
3210 pup = samsung_gpio_do_getpull(chip, offset);
3211 samsung_gpio_unlock(chip, flags);
3214 return (__force samsung_gpio_pull_t)pup;
3216 EXPORT_SYMBOL(s3c_gpio_getpull);
3218 #ifdef CONFIG_S5P_GPIO_DRVSTR
3219 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3221 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3230 off = pin - chip->chip.base;
3232 reg = chip->base + 0x0C;
3234 drvstr = __raw_readl(reg);
3235 drvstr = drvstr >> shift;
3238 return (__force s5p_gpio_drvstr_t)drvstr;
3240 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3242 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3244 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3253 off = pin - chip->chip.base;
3255 reg = chip->base + 0x0C;
3257 tmp = __raw_readl(reg);
3258 tmp &= ~(0x3 << shift);
3259 tmp |= drvstr << shift;
3261 __raw_writel(tmp, reg);
3265 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3266 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3268 #ifdef CONFIG_PLAT_S3C24XX
3269 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3271 unsigned long flags;
3272 unsigned long misccr;
3274 local_irq_save(flags);
3275 misccr = __raw_readl(S3C24XX_MISCCR);
3278 __raw_writel(misccr, S3C24XX_MISCCR);
3279 local_irq_restore(flags);
3283 EXPORT_SYMBOL(s3c2410_modify_misccr);