2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-gpio.h>
38 #include <plat/gpio-core.h>
39 #include <plat/gpio-cfg.h>
40 #include <plat/gpio-cfg-helpers.h>
43 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
44 unsigned int off, samsung_gpio_pull_t pull)
46 void __iomem *reg = chip->base + 0x08;
50 pup = __raw_readl(reg);
53 __raw_writel(pup, reg);
58 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
61 void __iomem *reg = chip->base + 0x08;
63 u32 pup = __raw_readl(reg);
68 return (__force samsung_gpio_pull_t)pup;
71 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
72 unsigned int off, samsung_gpio_pull_t pull)
75 case S3C_GPIO_PULL_NONE:
78 case S3C_GPIO_PULL_UP:
81 case S3C_GPIO_PULL_DOWN:
85 return samsung_gpio_setpull_updown(chip, off, pull);
88 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
91 samsung_gpio_pull_t pull;
93 pull = samsung_gpio_getpull_updown(chip, off);
97 pull = S3C_GPIO_PULL_UP;
101 pull = S3C_GPIO_PULL_NONE;
104 pull = S3C_GPIO_PULL_DOWN;
111 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
112 unsigned int off, samsung_gpio_pull_t pull,
113 samsung_gpio_pull_t updown)
115 void __iomem *reg = chip->base + 0x08;
116 u32 pup = __raw_readl(reg);
120 else if (pull == S3C_GPIO_PULL_NONE)
125 __raw_writel(pup, reg);
129 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
131 samsung_gpio_pull_t updown)
133 void __iomem *reg = chip->base + 0x08;
134 u32 pup = __raw_readl(reg);
137 return pup ? S3C_GPIO_PULL_NONE : updown;
140 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
143 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
146 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
147 unsigned int off, samsung_gpio_pull_t pull)
149 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
152 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
155 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
158 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
159 unsigned int off, samsung_gpio_pull_t pull)
161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
164 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
165 unsigned int off, samsung_gpio_pull_t pull)
167 if (pull == S3C_GPIO_PULL_UP)
170 return samsung_gpio_setpull_updown(chip, off, pull);
173 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
176 samsung_gpio_pull_t pull;
178 pull = samsung_gpio_getpull_updown(chip, off);
181 pull = S3C_GPIO_PULL_UP;
187 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
188 * @chip: The gpio chip that is being configured.
189 * @off: The offset for the GPIO being configured.
190 * @cfg: The configuration value to set.
192 * This helper deal with the GPIO cases where the control register
193 * has two bits of configuration per gpio, which have the following
197 * 1x = special function
200 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
201 unsigned int off, unsigned int cfg)
203 void __iomem *reg = chip->base;
204 unsigned int shift = off * 2;
207 if (samsung_gpio_is_cfg_special(cfg)) {
215 con = __raw_readl(reg);
216 con &= ~(0x3 << shift);
218 __raw_writel(con, reg);
224 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
225 * @chip: The gpio chip that is being configured.
226 * @off: The offset for the GPIO being configured.
228 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
229 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
230 * S3C_GPIO_SPECIAL() macro.
233 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
238 con = __raw_readl(chip->base);
242 /* this conversion works for IN and OUT as well as special mode */
243 return S3C_GPIO_SPECIAL(con);
247 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
248 * @chip: The gpio chip that is being configured.
249 * @off: The offset for the GPIO being configured.
250 * @cfg: The configuration value to set.
252 * This helper deal with the GPIO cases where the control register has 4 bits
253 * of control per GPIO, generally in the form of:
256 * others = Special functions (dependent on bank)
258 * Note, since the code to deal with the case where there are two control
259 * registers instead of one, we do not have a separate set of functions for
263 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
264 unsigned int off, unsigned int cfg)
266 void __iomem *reg = chip->base;
267 unsigned int shift = (off & 7) * 4;
270 if (off < 8 && chip->chip.ngpio > 8)
273 if (samsung_gpio_is_cfg_special(cfg)) {
278 con = __raw_readl(reg);
279 con &= ~(0xf << shift);
281 __raw_writel(con, reg);
287 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
288 * @chip: The gpio chip that is being configured.
289 * @off: The offset for the GPIO being configured.
291 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
292 * register setting into a value the software can use, such as could be passed
293 * to samsung_gpio_setcfg_4bit().
295 * @sa samsung_gpio_getcfg_2bit
298 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
301 void __iomem *reg = chip->base;
302 unsigned int shift = (off & 7) * 4;
305 if (off < 8 && chip->chip.ngpio > 8)
308 con = __raw_readl(reg);
312 /* this conversion works for IN and OUT as well as special mode */
313 return S3C_GPIO_SPECIAL(con);
316 #ifdef CONFIG_PLAT_S3C24XX
318 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
319 * @chip: The gpio chip that is being configured.
320 * @off: The offset for the GPIO being configured.
321 * @cfg: The configuration value to set.
323 * This helper deal with the GPIO cases where the control register
324 * has one bit of configuration for the gpio, where setting the bit
325 * means the pin is in special function mode and unset means output.
328 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
329 unsigned int off, unsigned int cfg)
331 void __iomem *reg = chip->base;
332 unsigned int shift = off;
335 if (samsung_gpio_is_cfg_special(cfg)) {
338 /* Map output to 0, and SFN2 to 1 */
346 con = __raw_readl(reg);
347 con &= ~(0x1 << shift);
349 __raw_writel(con, reg);
355 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
356 * @chip: The gpio chip that is being configured.
357 * @off: The offset for the GPIO being configured.
359 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
360 * GPIO configuration value.
362 * @sa samsung_gpio_getcfg_2bit
363 * @sa samsung_gpio_getcfg_4bit
366 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
371 con = __raw_readl(chip->base);
376 return S3C_GPIO_SFN(con);
380 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
381 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
382 unsigned int off, unsigned int cfg)
384 void __iomem *reg = chip->base;
395 shift = (off & 7) * 4;
399 shift = ((off + 1) & 7) * 4;
402 shift = ((off + 1) & 7) * 4;
406 if (samsung_gpio_is_cfg_special(cfg)) {
411 con = __raw_readl(reg);
412 con &= ~(0xf << shift);
414 __raw_writel(con, reg);
420 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
423 for (; nr_chips > 0; nr_chips--, chipcfg++) {
424 if (!chipcfg->set_config)
425 chipcfg->set_config = samsung_gpio_setcfg_4bit;
426 if (!chipcfg->get_config)
427 chipcfg->get_config = samsung_gpio_getcfg_4bit;
428 if (!chipcfg->set_pull)
429 chipcfg->set_pull = samsung_gpio_setpull_updown;
430 if (!chipcfg->get_pull)
431 chipcfg->get_pull = samsung_gpio_getpull_updown;
435 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
436 .set_config = samsung_gpio_setcfg_2bit,
437 .get_config = samsung_gpio_getcfg_2bit,
440 #ifdef CONFIG_PLAT_S3C24XX
441 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
442 .set_config = s3c24xx_gpio_setcfg_abank,
443 .get_config = s3c24xx_gpio_getcfg_abank,
447 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
448 static struct samsung_gpio_cfg exynos_gpio_cfg = {
449 .set_pull = exynos_gpio_setpull,
450 .get_pull = exynos_gpio_getpull,
451 .set_config = samsung_gpio_setcfg_4bit,
452 .get_config = samsung_gpio_getcfg_4bit,
456 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
457 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
459 .set_config = s5p64x0_gpio_setcfg_rbank,
460 .get_config = samsung_gpio_getcfg_4bit,
461 .set_pull = samsung_gpio_setpull_updown,
462 .get_pull = samsung_gpio_getpull_updown,
466 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
481 .set_config = samsung_gpio_setcfg_2bit,
482 .get_config = samsung_gpio_getcfg_2bit,
486 .set_config = samsung_gpio_setcfg_2bit,
487 .get_config = samsung_gpio_getcfg_2bit,
491 .set_config = samsung_gpio_setcfg_2bit,
492 .get_config = samsung_gpio_getcfg_2bit,
495 .set_config = samsung_gpio_setcfg_2bit,
496 .get_config = samsung_gpio_getcfg_2bit,
499 .set_pull = exynos_gpio_setpull,
500 .get_pull = exynos_gpio_getpull,
504 .set_pull = exynos_gpio_setpull,
505 .get_pull = exynos_gpio_getpull,
510 * Default routines for controlling GPIO, based on the original S3C24XX
511 * GPIO functions which deal with the case where each gpio bank of the
512 * chip is as following:
514 * base + 0x00: Control register, 2 bits per gpio
515 * gpio n: 2 bits starting at (2*n)
516 * 00 = input, 01 = output, others mean special-function
517 * base + 0x04: Data register, 1 bit per gpio
521 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
523 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
524 void __iomem *base = ourchip->base;
528 samsung_gpio_lock(ourchip, flags);
530 con = __raw_readl(base + 0x00);
531 con &= ~(3 << (offset * 2));
533 __raw_writel(con, base + 0x00);
535 samsung_gpio_unlock(ourchip, flags);
539 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
540 unsigned offset, int value)
542 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
543 void __iomem *base = ourchip->base;
548 samsung_gpio_lock(ourchip, flags);
550 dat = __raw_readl(base + 0x04);
551 dat &= ~(1 << offset);
554 __raw_writel(dat, base + 0x04);
556 con = __raw_readl(base + 0x00);
557 con &= ~(3 << (offset * 2));
558 con |= 1 << (offset * 2);
560 __raw_writel(con, base + 0x00);
561 __raw_writel(dat, base + 0x04);
563 samsung_gpio_unlock(ourchip, flags);
568 * The samsung_gpiolib_4bit routines are to control the gpio banks where
569 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
572 * base + 0x00: Control register, 4 bits per gpio
573 * gpio n: 4 bits starting at (4*n)
574 * 0000 = input, 0001 = output, others mean special-function
575 * base + 0x04: Data register, 1 bit per gpio
578 * Note, since the data register is one bit per gpio and is at base + 0x4
579 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
580 * state of the output.
583 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
586 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
587 void __iomem *base = ourchip->base;
590 con = __raw_readl(base + GPIOCON_OFF);
591 if (ourchip->bitmap_gpio_int & BIT(offset))
592 con |= 0xf << con_4bit_shift(offset);
594 con &= ~(0xf << con_4bit_shift(offset));
595 __raw_writel(con, base + GPIOCON_OFF);
597 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
602 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
603 unsigned int offset, int value)
605 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
606 void __iomem *base = ourchip->base;
610 con = __raw_readl(base + GPIOCON_OFF);
611 con &= ~(0xf << con_4bit_shift(offset));
612 con |= 0x1 << con_4bit_shift(offset);
614 dat = __raw_readl(base + GPIODAT_OFF);
619 dat &= ~(1 << offset);
621 __raw_writel(dat, base + GPIODAT_OFF);
622 __raw_writel(con, base + GPIOCON_OFF);
623 __raw_writel(dat, base + GPIODAT_OFF);
625 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
631 * The next set of routines are for the case where the GPIO configuration
632 * registers are 4 bits per GPIO but there is more than one register (the
633 * bank has more than 8 GPIOs.
635 * This case is the similar to the 4 bit case, but the registers are as
638 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
639 * gpio n: 4 bits starting at (4*n)
640 * 0000 = input, 0001 = output, others mean special-function
641 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
642 * gpio n: 4 bits starting at (4*n)
643 * 0000 = input, 0001 = output, others mean special-function
644 * base + 0x08: Data register, 1 bit per gpio
647 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
648 * routines we store the 'base + 0x4' address so that these routines see
649 * the data register at ourchip->base + 0x04.
652 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
655 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
656 void __iomem *base = ourchip->base;
657 void __iomem *regcon = base;
665 con = __raw_readl(regcon);
666 con &= ~(0xf << con_4bit_shift(offset));
667 __raw_writel(con, regcon);
669 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
674 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
675 unsigned int offset, int value)
677 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
678 void __iomem *base = ourchip->base;
679 void __iomem *regcon = base;
682 unsigned con_offset = offset;
689 con = __raw_readl(regcon);
690 con &= ~(0xf << con_4bit_shift(con_offset));
691 con |= 0x1 << con_4bit_shift(con_offset);
693 dat = __raw_readl(base + GPIODAT_OFF);
698 dat &= ~(1 << offset);
700 __raw_writel(dat, base + GPIODAT_OFF);
701 __raw_writel(con, regcon);
702 __raw_writel(dat, base + GPIODAT_OFF);
704 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
709 #ifdef CONFIG_PLAT_S3C24XX
710 /* The next set of routines are for the case of s3c24xx bank a */
712 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
717 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
718 unsigned offset, int value)
720 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
721 void __iomem *base = ourchip->base;
726 local_irq_save(flags);
728 con = __raw_readl(base + 0x00);
729 dat = __raw_readl(base + 0x04);
731 dat &= ~(1 << offset);
735 __raw_writel(dat, base + 0x04);
737 con &= ~(1 << offset);
739 __raw_writel(con, base + 0x00);
740 __raw_writel(dat, base + 0x04);
742 local_irq_restore(flags);
747 /* The next set of routines are for the case of s5p64x0 bank r */
749 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
774 samsung_gpio_lock(ourchip, flags);
776 con = __raw_readl(regcon);
777 con &= ~(0xf << con_4bit_shift(offset));
778 __raw_writel(con, regcon);
780 samsung_gpio_unlock(ourchip, flags);
785 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
786 unsigned int offset, int value)
788 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
789 void __iomem *base = ourchip->base;
790 void __iomem *regcon = base;
794 unsigned con_offset = offset;
796 switch (con_offset) {
812 samsung_gpio_lock(ourchip, flags);
814 con = __raw_readl(regcon);
815 con &= ~(0xf << con_4bit_shift(con_offset));
816 con |= 0x1 << con_4bit_shift(con_offset);
818 dat = __raw_readl(base + GPIODAT_OFF);
822 dat &= ~(1 << offset);
824 __raw_writel(con, regcon);
825 __raw_writel(dat, base + GPIODAT_OFF);
827 samsung_gpio_unlock(ourchip, flags);
832 static void samsung_gpiolib_set(struct gpio_chip *chip,
833 unsigned offset, int value)
835 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
836 void __iomem *base = ourchip->base;
840 samsung_gpio_lock(ourchip, flags);
842 dat = __raw_readl(base + 0x04);
843 dat &= ~(1 << offset);
846 __raw_writel(dat, base + 0x04);
848 samsung_gpio_unlock(ourchip, flags);
851 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
853 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
856 val = __raw_readl(ourchip->base + 0x04);
864 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
865 * for use with the configuration calls, and other parts of the s3c gpiolib
868 * Not all s3c support code will need this, as some configurations of cpu
869 * may only support one or two different configuration options and have an
870 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
871 * the machine support file should provide its own samsung_gpiolib_getchip()
872 * and any other necessary functions.
875 #ifdef CONFIG_S3C_GPIO_TRACK
876 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
878 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
883 gpn = chip->chip.base;
884 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
885 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
886 s3c_gpios[gpn] = chip;
889 #endif /* CONFIG_S3C_GPIO_TRACK */
892 * samsung_gpiolib_add() - add the Samsung gpio_chip.
893 * @chip: The chip to register
895 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
896 * information and makes the necessary alterations for the platform and
897 * notes the information for use with the configuration systems and any
898 * other parts of the system.
901 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
903 struct gpio_chip *gc = &chip->chip;
910 spin_lock_init(&chip->lock);
912 if (!gc->direction_input)
913 gc->direction_input = samsung_gpiolib_2bit_input;
914 if (!gc->direction_output)
915 gc->direction_output = samsung_gpiolib_2bit_output;
917 gc->set = samsung_gpiolib_set;
919 gc->get = samsung_gpiolib_get;
922 if (chip->pm != NULL) {
923 if (!chip->pm->save || !chip->pm->resume)
924 pr_err("gpio: %s has missing PM functions\n",
927 pr_err("gpio: %s has no PM function\n", gc->label);
930 /* gpiochip_add() prints own failure message on error. */
931 ret = gpiochip_add(gc);
933 s3c_gpiolib_track(chip);
936 #if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
937 static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
938 const struct of_phandle_args *gpiospec, u32 *flags)
942 if (WARN_ON(gc->of_gpio_n_cells < 3))
945 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
948 if (gpiospec->args[0] > gc->ngpio)
951 pin = gc->base + gpiospec->args[0];
953 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
954 pr_warn("gpio_xlate: failed to set pin function\n");
955 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
956 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
959 *flags = gpiospec->args[2] >> 16;
961 return gpiospec->args[0];
964 static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
965 { .compatible = "samsung,s3c24xx-gpio", },
969 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
970 u64 base, u64 offset)
972 struct gpio_chip *gc = &chip->chip;
975 if (!of_have_populated_dt())
978 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
979 gc->of_node = of_find_matching_node_by_address(NULL,
980 s3c24xx_gpio_dt_match, address);
982 pr_info("gpio: device tree node not found for gpio controller"
983 " with base address %08llx\n", address);
986 gc->of_gpio_n_cells = 3;
987 gc->of_xlate = s3c24xx_gpio_xlate;
990 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
991 u64 base, u64 offset)
995 #endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
997 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
998 int nr_chips, void __iomem *base)
1001 struct gpio_chip *gc = &chip->chip;
1003 for (i = 0 ; i < nr_chips; i++, chip++) {
1004 /* skip banks not present on SoC */
1005 if (chip->chip.base >= S3C_GPIO_END)
1009 chip->config = &s3c24xx_gpiocfg_default;
1011 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1012 if ((base != NULL) && (chip->base == NULL))
1013 chip->base = base + ((i) * 0x10);
1015 if (!gc->direction_input)
1016 gc->direction_input = samsung_gpiolib_2bit_input;
1017 if (!gc->direction_output)
1018 gc->direction_output = samsung_gpiolib_2bit_output;
1020 samsung_gpiolib_add(chip);
1022 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1026 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1027 int nr_chips, void __iomem *base,
1028 unsigned int offset)
1032 for (i = 0 ; i < nr_chips; i++, chip++) {
1033 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1034 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1037 chip->config = &samsung_gpio_cfgs[7];
1039 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1040 if ((base != NULL) && (chip->base == NULL))
1041 chip->base = base + ((i) * offset);
1043 samsung_gpiolib_add(chip);
1048 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1049 * @chip: The gpio chip that is being configured.
1050 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1052 * This helper deal with the GPIO cases where the control register has 4 bits
1053 * of control per GPIO, generally in the form of:
1056 * others = Special functions (dependent on bank)
1058 * Note, since the code to deal with the case where there are two control
1059 * registers instead of one, we do not have a separate set of function
1060 * (samsung_gpiolib_add_4bit2_chips)for each case.
1063 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1064 int nr_chips, void __iomem *base)
1068 for (i = 0 ; i < nr_chips; i++, chip++) {
1069 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1070 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1073 chip->config = &samsung_gpio_cfgs[2];
1075 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1076 if ((base != NULL) && (chip->base == NULL))
1077 chip->base = base + ((i) * 0x20);
1079 chip->bitmap_gpio_int = 0;
1081 samsung_gpiolib_add(chip);
1085 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1088 for (; nr_chips > 0; nr_chips--, chip++) {
1089 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1090 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1093 chip->config = &samsung_gpio_cfgs[2];
1095 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1097 samsung_gpiolib_add(chip);
1101 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1104 for (; nr_chips > 0; nr_chips--, chip++) {
1105 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1106 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1109 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1111 samsung_gpiolib_add(chip);
1115 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1117 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1119 return samsung_chip->irq_base + offset;
1122 #ifdef CONFIG_PLAT_S3C24XX
1123 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1126 if (soc_is_s3c2412())
1127 return IRQ_EINT0_2412 + offset;
1129 return IRQ_EINT0 + offset;
1133 return IRQ_EINT4 + offset - 4;
1139 #ifdef CONFIG_PLAT_S3C64XX
1140 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1142 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1145 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1147 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1151 struct samsung_gpio_chip s3c24xx_gpios[] = {
1152 #ifdef CONFIG_PLAT_S3C24XX
1154 .config = &s3c24xx_gpiocfg_banka,
1156 .base = S3C2410_GPA(0),
1157 .owner = THIS_MODULE,
1160 .direction_input = s3c24xx_gpiolib_banka_input,
1161 .direction_output = s3c24xx_gpiolib_banka_output,
1165 .base = S3C2410_GPB(0),
1166 .owner = THIS_MODULE,
1172 .base = S3C2410_GPC(0),
1173 .owner = THIS_MODULE,
1179 .base = S3C2410_GPD(0),
1180 .owner = THIS_MODULE,
1186 .base = S3C2410_GPE(0),
1188 .owner = THIS_MODULE,
1193 .base = S3C2410_GPF(0),
1194 .owner = THIS_MODULE,
1197 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1200 .irq_base = IRQ_EINT8,
1202 .base = S3C2410_GPG(0),
1203 .owner = THIS_MODULE,
1206 .to_irq = samsung_gpiolib_to_irq,
1210 .base = S3C2410_GPH(0),
1211 .owner = THIS_MODULE,
1216 /* GPIOS for the S3C2443 and later devices. */
1218 .base = S3C2440_GPJCON,
1220 .base = S3C2410_GPJ(0),
1221 .owner = THIS_MODULE,
1226 .base = S3C2443_GPKCON,
1228 .base = S3C2410_GPK(0),
1229 .owner = THIS_MODULE,
1234 .base = S3C2443_GPLCON,
1236 .base = S3C2410_GPL(0),
1237 .owner = THIS_MODULE,
1242 .base = S3C2443_GPMCON,
1244 .base = S3C2410_GPM(0),
1245 .owner = THIS_MODULE,
1254 * GPIO bank summary:
1256 * Bank GPIOs Style SlpCon ExtInt Group
1262 * F 16 2Bit Yes 4 [1]
1264 * H 10 4Bit[2] Yes 6
1265 * I 16 2Bit Yes None
1266 * J 12 2Bit Yes None
1267 * K 16 4Bit[2] No None
1268 * L 15 4Bit[2] No None
1269 * M 6 4Bit No IRQ_EINT
1270 * N 16 2Bit No IRQ_EINT
1275 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1276 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1279 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1280 #ifdef CONFIG_PLAT_S3C64XX
1283 .base = S3C64XX_GPA(0),
1284 .ngpio = S3C64XX_GPIO_A_NR,
1289 .base = S3C64XX_GPB(0),
1290 .ngpio = S3C64XX_GPIO_B_NR,
1295 .base = S3C64XX_GPC(0),
1296 .ngpio = S3C64XX_GPIO_C_NR,
1301 .base = S3C64XX_GPD(0),
1302 .ngpio = S3C64XX_GPIO_D_NR,
1306 .config = &samsung_gpio_cfgs[0],
1308 .base = S3C64XX_GPE(0),
1309 .ngpio = S3C64XX_GPIO_E_NR,
1313 .base = S3C64XX_GPG_BASE,
1315 .base = S3C64XX_GPG(0),
1316 .ngpio = S3C64XX_GPIO_G_NR,
1320 .base = S3C64XX_GPM_BASE,
1321 .config = &samsung_gpio_cfgs[1],
1323 .base = S3C64XX_GPM(0),
1324 .ngpio = S3C64XX_GPIO_M_NR,
1326 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1332 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1333 #ifdef CONFIG_PLAT_S3C64XX
1335 .base = S3C64XX_GPH_BASE + 0x4,
1337 .base = S3C64XX_GPH(0),
1338 .ngpio = S3C64XX_GPIO_H_NR,
1342 .base = S3C64XX_GPK_BASE + 0x4,
1343 .config = &samsung_gpio_cfgs[0],
1345 .base = S3C64XX_GPK(0),
1346 .ngpio = S3C64XX_GPIO_K_NR,
1350 .base = S3C64XX_GPL_BASE + 0x4,
1351 .config = &samsung_gpio_cfgs[1],
1353 .base = S3C64XX_GPL(0),
1354 .ngpio = S3C64XX_GPIO_L_NR,
1356 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1362 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1363 #ifdef CONFIG_PLAT_S3C64XX
1365 .base = S3C64XX_GPF_BASE,
1366 .config = &samsung_gpio_cfgs[6],
1368 .base = S3C64XX_GPF(0),
1369 .ngpio = S3C64XX_GPIO_F_NR,
1373 .config = &samsung_gpio_cfgs[7],
1375 .base = S3C64XX_GPI(0),
1376 .ngpio = S3C64XX_GPIO_I_NR,
1380 .config = &samsung_gpio_cfgs[7],
1382 .base = S3C64XX_GPJ(0),
1383 .ngpio = S3C64XX_GPIO_J_NR,
1387 .config = &samsung_gpio_cfgs[6],
1389 .base = S3C64XX_GPO(0),
1390 .ngpio = S3C64XX_GPIO_O_NR,
1394 .config = &samsung_gpio_cfgs[6],
1396 .base = S3C64XX_GPP(0),
1397 .ngpio = S3C64XX_GPIO_P_NR,
1401 .config = &samsung_gpio_cfgs[6],
1403 .base = S3C64XX_GPQ(0),
1404 .ngpio = S3C64XX_GPIO_Q_NR,
1408 .base = S3C64XX_GPN_BASE,
1409 .irq_base = IRQ_EINT(0),
1410 .config = &samsung_gpio_cfgs[5],
1412 .base = S3C64XX_GPN(0),
1413 .ngpio = S3C64XX_GPIO_N_NR,
1415 .to_irq = samsung_gpiolib_to_irq,
1422 * S5P6440 GPIO bank summary:
1424 * Bank GPIOs Style SlpCon ExtInt Group
1428 * F 2 2Bit Yes 4 [1]
1430 * H 10 4Bit[2] Yes 6
1431 * I 16 2Bit Yes None
1432 * J 12 2Bit Yes None
1433 * N 16 2Bit No IRQ_EINT
1435 * R 15 4Bit[2] Yes 8
1438 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1439 #ifdef CONFIG_CPU_S5P6440
1442 .base = S5P6440_GPA(0),
1443 .ngpio = S5P6440_GPIO_A_NR,
1448 .base = S5P6440_GPB(0),
1449 .ngpio = S5P6440_GPIO_B_NR,
1454 .base = S5P6440_GPC(0),
1455 .ngpio = S5P6440_GPIO_C_NR,
1459 .base = S5P64X0_GPG_BASE,
1461 .base = S5P6440_GPG(0),
1462 .ngpio = S5P6440_GPIO_G_NR,
1469 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1470 #ifdef CONFIG_CPU_S5P6440
1472 .base = S5P64X0_GPH_BASE + 0x4,
1474 .base = S5P6440_GPH(0),
1475 .ngpio = S5P6440_GPIO_H_NR,
1482 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1483 #ifdef CONFIG_CPU_S5P6440
1485 .base = S5P64X0_GPR_BASE + 0x4,
1486 .config = &s5p64x0_gpio_cfg_rbank,
1488 .base = S5P6440_GPR(0),
1489 .ngpio = S5P6440_GPIO_R_NR,
1496 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1497 #ifdef CONFIG_CPU_S5P6440
1499 .base = S5P64X0_GPF_BASE,
1500 .config = &samsung_gpio_cfgs[6],
1502 .base = S5P6440_GPF(0),
1503 .ngpio = S5P6440_GPIO_F_NR,
1507 .base = S5P64X0_GPI_BASE,
1508 .config = &samsung_gpio_cfgs[4],
1510 .base = S5P6440_GPI(0),
1511 .ngpio = S5P6440_GPIO_I_NR,
1515 .base = S5P64X0_GPJ_BASE,
1516 .config = &samsung_gpio_cfgs[4],
1518 .base = S5P6440_GPJ(0),
1519 .ngpio = S5P6440_GPIO_J_NR,
1523 .base = S5P64X0_GPN_BASE,
1524 .config = &samsung_gpio_cfgs[5],
1526 .base = S5P6440_GPN(0),
1527 .ngpio = S5P6440_GPIO_N_NR,
1531 .base = S5P64X0_GPP_BASE,
1532 .config = &samsung_gpio_cfgs[6],
1534 .base = S5P6440_GPP(0),
1535 .ngpio = S5P6440_GPIO_P_NR,
1543 * S5P6450 GPIO bank summary:
1545 * Bank GPIOs Style SlpCon ExtInt Group
1551 * G 14 4Bit[2] Yes 5
1552 * H 10 4Bit[2] Yes 6
1553 * I 16 2Bit Yes None
1554 * J 12 2Bit Yes None
1556 * N 16 2Bit No IRQ_EINT
1558 * Q 14 2Bit Yes None
1559 * R 15 4Bit[2] Yes None
1562 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1563 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1566 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1567 #ifdef CONFIG_CPU_S5P6450
1570 .base = S5P6450_GPA(0),
1571 .ngpio = S5P6450_GPIO_A_NR,
1576 .base = S5P6450_GPB(0),
1577 .ngpio = S5P6450_GPIO_B_NR,
1582 .base = S5P6450_GPC(0),
1583 .ngpio = S5P6450_GPIO_C_NR,
1588 .base = S5P6450_GPD(0),
1589 .ngpio = S5P6450_GPIO_D_NR,
1593 .base = S5P6450_GPK_BASE,
1595 .base = S5P6450_GPK(0),
1596 .ngpio = S5P6450_GPIO_K_NR,
1603 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1604 #ifdef CONFIG_CPU_S5P6450
1606 .base = S5P64X0_GPG_BASE + 0x4,
1608 .base = S5P6450_GPG(0),
1609 .ngpio = S5P6450_GPIO_G_NR,
1613 .base = S5P64X0_GPH_BASE + 0x4,
1615 .base = S5P6450_GPH(0),
1616 .ngpio = S5P6450_GPIO_H_NR,
1623 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1624 #ifdef CONFIG_CPU_S5P6450
1626 .base = S5P64X0_GPR_BASE + 0x4,
1627 .config = &s5p64x0_gpio_cfg_rbank,
1629 .base = S5P6450_GPR(0),
1630 .ngpio = S5P6450_GPIO_R_NR,
1637 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1638 #ifdef CONFIG_CPU_S5P6450
1640 .base = S5P64X0_GPF_BASE,
1641 .config = &samsung_gpio_cfgs[6],
1643 .base = S5P6450_GPF(0),
1644 .ngpio = S5P6450_GPIO_F_NR,
1648 .base = S5P64X0_GPI_BASE,
1649 .config = &samsung_gpio_cfgs[4],
1651 .base = S5P6450_GPI(0),
1652 .ngpio = S5P6450_GPIO_I_NR,
1656 .base = S5P64X0_GPJ_BASE,
1657 .config = &samsung_gpio_cfgs[4],
1659 .base = S5P6450_GPJ(0),
1660 .ngpio = S5P6450_GPIO_J_NR,
1664 .base = S5P64X0_GPN_BASE,
1665 .config = &samsung_gpio_cfgs[5],
1667 .base = S5P6450_GPN(0),
1668 .ngpio = S5P6450_GPIO_N_NR,
1672 .base = S5P64X0_GPP_BASE,
1673 .config = &samsung_gpio_cfgs[6],
1675 .base = S5P6450_GPP(0),
1676 .ngpio = S5P6450_GPIO_P_NR,
1680 .base = S5P6450_GPQ_BASE,
1681 .config = &samsung_gpio_cfgs[5],
1683 .base = S5P6450_GPQ(0),
1684 .ngpio = S5P6450_GPIO_Q_NR,
1688 .base = S5P6450_GPS_BASE,
1689 .config = &samsung_gpio_cfgs[6],
1691 .base = S5P6450_GPS(0),
1692 .ngpio = S5P6450_GPIO_S_NR,
1700 * S5PC100 GPIO bank summary:
1702 * Bank GPIOs Style INT Type
1703 * A0 8 4Bit GPIO_INT0
1704 * A1 5 4Bit GPIO_INT1
1705 * B 8 4Bit GPIO_INT2
1706 * C 5 4Bit GPIO_INT3
1707 * D 7 4Bit GPIO_INT4
1708 * E0 8 4Bit GPIO_INT5
1709 * E1 6 4Bit GPIO_INT6
1710 * F0 8 4Bit GPIO_INT7
1711 * F1 8 4Bit GPIO_INT8
1712 * F2 8 4Bit GPIO_INT9
1713 * F3 4 4Bit GPIO_INT10
1714 * G0 8 4Bit GPIO_INT11
1715 * G1 3 4Bit GPIO_INT12
1716 * G2 7 4Bit GPIO_INT13
1717 * G3 7 4Bit GPIO_INT14
1718 * H0 8 4Bit WKUP_INT
1719 * H1 8 4Bit WKUP_INT
1720 * H2 8 4Bit WKUP_INT
1721 * H3 8 4Bit WKUP_INT
1722 * I 8 4Bit GPIO_INT15
1723 * J0 8 4Bit GPIO_INT16
1724 * J1 5 4Bit GPIO_INT17
1725 * J2 8 4Bit GPIO_INT18
1726 * J3 8 4Bit GPIO_INT19
1727 * J4 4 4Bit GPIO_INT20
1738 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1739 #ifdef CONFIG_CPU_S5PC100
1742 .base = S5PC100_GPA0(0),
1743 .ngpio = S5PC100_GPIO_A0_NR,
1748 .base = S5PC100_GPA1(0),
1749 .ngpio = S5PC100_GPIO_A1_NR,
1754 .base = S5PC100_GPB(0),
1755 .ngpio = S5PC100_GPIO_B_NR,
1760 .base = S5PC100_GPC(0),
1761 .ngpio = S5PC100_GPIO_C_NR,
1766 .base = S5PC100_GPD(0),
1767 .ngpio = S5PC100_GPIO_D_NR,
1772 .base = S5PC100_GPE0(0),
1773 .ngpio = S5PC100_GPIO_E0_NR,
1778 .base = S5PC100_GPE1(0),
1779 .ngpio = S5PC100_GPIO_E1_NR,
1784 .base = S5PC100_GPF0(0),
1785 .ngpio = S5PC100_GPIO_F0_NR,
1790 .base = S5PC100_GPF1(0),
1791 .ngpio = S5PC100_GPIO_F1_NR,
1796 .base = S5PC100_GPF2(0),
1797 .ngpio = S5PC100_GPIO_F2_NR,
1802 .base = S5PC100_GPF3(0),
1803 .ngpio = S5PC100_GPIO_F3_NR,
1808 .base = S5PC100_GPG0(0),
1809 .ngpio = S5PC100_GPIO_G0_NR,
1814 .base = S5PC100_GPG1(0),
1815 .ngpio = S5PC100_GPIO_G1_NR,
1820 .base = S5PC100_GPG2(0),
1821 .ngpio = S5PC100_GPIO_G2_NR,
1826 .base = S5PC100_GPG3(0),
1827 .ngpio = S5PC100_GPIO_G3_NR,
1832 .base = S5PC100_GPI(0),
1833 .ngpio = S5PC100_GPIO_I_NR,
1838 .base = S5PC100_GPJ0(0),
1839 .ngpio = S5PC100_GPIO_J0_NR,
1844 .base = S5PC100_GPJ1(0),
1845 .ngpio = S5PC100_GPIO_J1_NR,
1850 .base = S5PC100_GPJ2(0),
1851 .ngpio = S5PC100_GPIO_J2_NR,
1856 .base = S5PC100_GPJ3(0),
1857 .ngpio = S5PC100_GPIO_J3_NR,
1862 .base = S5PC100_GPJ4(0),
1863 .ngpio = S5PC100_GPIO_J4_NR,
1868 .base = S5PC100_GPK0(0),
1869 .ngpio = S5PC100_GPIO_K0_NR,
1874 .base = S5PC100_GPK1(0),
1875 .ngpio = S5PC100_GPIO_K1_NR,
1880 .base = S5PC100_GPK2(0),
1881 .ngpio = S5PC100_GPIO_K2_NR,
1886 .base = S5PC100_GPK3(0),
1887 .ngpio = S5PC100_GPIO_K3_NR,
1892 .base = S5PC100_GPL0(0),
1893 .ngpio = S5PC100_GPIO_L0_NR,
1898 .base = S5PC100_GPL1(0),
1899 .ngpio = S5PC100_GPIO_L1_NR,
1904 .base = S5PC100_GPL2(0),
1905 .ngpio = S5PC100_GPIO_L2_NR,
1910 .base = S5PC100_GPL3(0),
1911 .ngpio = S5PC100_GPIO_L3_NR,
1916 .base = S5PC100_GPL4(0),
1917 .ngpio = S5PC100_GPIO_L4_NR,
1921 .base = (S5P_VA_GPIO + 0xC00),
1922 .irq_base = IRQ_EINT(0),
1924 .base = S5PC100_GPH0(0),
1925 .ngpio = S5PC100_GPIO_H0_NR,
1927 .to_irq = samsung_gpiolib_to_irq,
1930 .base = (S5P_VA_GPIO + 0xC20),
1931 .irq_base = IRQ_EINT(8),
1933 .base = S5PC100_GPH1(0),
1934 .ngpio = S5PC100_GPIO_H1_NR,
1936 .to_irq = samsung_gpiolib_to_irq,
1939 .base = (S5P_VA_GPIO + 0xC40),
1940 .irq_base = IRQ_EINT(16),
1942 .base = S5PC100_GPH2(0),
1943 .ngpio = S5PC100_GPIO_H2_NR,
1945 .to_irq = samsung_gpiolib_to_irq,
1948 .base = (S5P_VA_GPIO + 0xC60),
1949 .irq_base = IRQ_EINT(24),
1951 .base = S5PC100_GPH3(0),
1952 .ngpio = S5PC100_GPIO_H3_NR,
1954 .to_irq = samsung_gpiolib_to_irq,
1961 * Followings are the gpio banks in S5PV210/S5PC110
1963 * The 'config' member when left to NULL, is initialized to the default
1964 * structure samsung_gpio_cfgs[3] in the init function below.
1966 * The 'base' member is also initialized in the init function below.
1967 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1968 * uses the above macro and depends on the banks being listed in order here.
1971 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1972 #ifdef CONFIG_CPU_S5PV210
1975 .base = S5PV210_GPA0(0),
1976 .ngpio = S5PV210_GPIO_A0_NR,
1981 .base = S5PV210_GPA1(0),
1982 .ngpio = S5PV210_GPIO_A1_NR,
1987 .base = S5PV210_GPB(0),
1988 .ngpio = S5PV210_GPIO_B_NR,
1993 .base = S5PV210_GPC0(0),
1994 .ngpio = S5PV210_GPIO_C0_NR,
1999 .base = S5PV210_GPC1(0),
2000 .ngpio = S5PV210_GPIO_C1_NR,
2005 .base = S5PV210_GPD0(0),
2006 .ngpio = S5PV210_GPIO_D0_NR,
2011 .base = S5PV210_GPD1(0),
2012 .ngpio = S5PV210_GPIO_D1_NR,
2017 .base = S5PV210_GPE0(0),
2018 .ngpio = S5PV210_GPIO_E0_NR,
2023 .base = S5PV210_GPE1(0),
2024 .ngpio = S5PV210_GPIO_E1_NR,
2029 .base = S5PV210_GPF0(0),
2030 .ngpio = S5PV210_GPIO_F0_NR,
2035 .base = S5PV210_GPF1(0),
2036 .ngpio = S5PV210_GPIO_F1_NR,
2041 .base = S5PV210_GPF2(0),
2042 .ngpio = S5PV210_GPIO_F2_NR,
2047 .base = S5PV210_GPF3(0),
2048 .ngpio = S5PV210_GPIO_F3_NR,
2053 .base = S5PV210_GPG0(0),
2054 .ngpio = S5PV210_GPIO_G0_NR,
2059 .base = S5PV210_GPG1(0),
2060 .ngpio = S5PV210_GPIO_G1_NR,
2065 .base = S5PV210_GPG2(0),
2066 .ngpio = S5PV210_GPIO_G2_NR,
2071 .base = S5PV210_GPG3(0),
2072 .ngpio = S5PV210_GPIO_G3_NR,
2077 .base = S5PV210_GPI(0),
2078 .ngpio = S5PV210_GPIO_I_NR,
2083 .base = S5PV210_GPJ0(0),
2084 .ngpio = S5PV210_GPIO_J0_NR,
2089 .base = S5PV210_GPJ1(0),
2090 .ngpio = S5PV210_GPIO_J1_NR,
2095 .base = S5PV210_GPJ2(0),
2096 .ngpio = S5PV210_GPIO_J2_NR,
2101 .base = S5PV210_GPJ3(0),
2102 .ngpio = S5PV210_GPIO_J3_NR,
2107 .base = S5PV210_GPJ4(0),
2108 .ngpio = S5PV210_GPIO_J4_NR,
2113 .base = S5PV210_MP01(0),
2114 .ngpio = S5PV210_GPIO_MP01_NR,
2119 .base = S5PV210_MP02(0),
2120 .ngpio = S5PV210_GPIO_MP02_NR,
2125 .base = S5PV210_MP03(0),
2126 .ngpio = S5PV210_GPIO_MP03_NR,
2131 .base = S5PV210_MP04(0),
2132 .ngpio = S5PV210_GPIO_MP04_NR,
2137 .base = S5PV210_MP05(0),
2138 .ngpio = S5PV210_GPIO_MP05_NR,
2142 .base = (S5P_VA_GPIO + 0xC00),
2143 .irq_base = IRQ_EINT(0),
2145 .base = S5PV210_GPH0(0),
2146 .ngpio = S5PV210_GPIO_H0_NR,
2148 .to_irq = samsung_gpiolib_to_irq,
2151 .base = (S5P_VA_GPIO + 0xC20),
2152 .irq_base = IRQ_EINT(8),
2154 .base = S5PV210_GPH1(0),
2155 .ngpio = S5PV210_GPIO_H1_NR,
2157 .to_irq = samsung_gpiolib_to_irq,
2160 .base = (S5P_VA_GPIO + 0xC40),
2161 .irq_base = IRQ_EINT(16),
2163 .base = S5PV210_GPH2(0),
2164 .ngpio = S5PV210_GPIO_H2_NR,
2166 .to_irq = samsung_gpiolib_to_irq,
2169 .base = (S5P_VA_GPIO + 0xC60),
2170 .irq_base = IRQ_EINT(24),
2172 .base = S5PV210_GPH3(0),
2173 .ngpio = S5PV210_GPIO_H3_NR,
2175 .to_irq = samsung_gpiolib_to_irq,
2182 * Followings are the gpio banks in EXYNOS SoCs
2184 * The 'config' member when left to NULL, is initialized to the default
2185 * structure exynos_gpio_cfg in the init function below.
2187 * The 'base' member is also initialized in the init function below.
2188 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2189 * uses the above macro and depends on the banks being listed in order here.
2192 #ifdef CONFIG_ARCH_EXYNOS4
2193 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2196 .base = EXYNOS4_GPA0(0),
2197 .ngpio = EXYNOS4_GPIO_A0_NR,
2202 .base = EXYNOS4_GPA1(0),
2203 .ngpio = EXYNOS4_GPIO_A1_NR,
2208 .base = EXYNOS4_GPB(0),
2209 .ngpio = EXYNOS4_GPIO_B_NR,
2214 .base = EXYNOS4_GPC0(0),
2215 .ngpio = EXYNOS4_GPIO_C0_NR,
2220 .base = EXYNOS4_GPC1(0),
2221 .ngpio = EXYNOS4_GPIO_C1_NR,
2226 .base = EXYNOS4_GPD0(0),
2227 .ngpio = EXYNOS4_GPIO_D0_NR,
2232 .base = EXYNOS4_GPD1(0),
2233 .ngpio = EXYNOS4_GPIO_D1_NR,
2238 .base = EXYNOS4_GPE0(0),
2239 .ngpio = EXYNOS4_GPIO_E0_NR,
2244 .base = EXYNOS4_GPE1(0),
2245 .ngpio = EXYNOS4_GPIO_E1_NR,
2250 .base = EXYNOS4_GPE2(0),
2251 .ngpio = EXYNOS4_GPIO_E2_NR,
2256 .base = EXYNOS4_GPE3(0),
2257 .ngpio = EXYNOS4_GPIO_E3_NR,
2262 .base = EXYNOS4_GPE4(0),
2263 .ngpio = EXYNOS4_GPIO_E4_NR,
2268 .base = EXYNOS4_GPF0(0),
2269 .ngpio = EXYNOS4_GPIO_F0_NR,
2274 .base = EXYNOS4_GPF1(0),
2275 .ngpio = EXYNOS4_GPIO_F1_NR,
2280 .base = EXYNOS4_GPF2(0),
2281 .ngpio = EXYNOS4_GPIO_F2_NR,
2286 .base = EXYNOS4_GPF3(0),
2287 .ngpio = EXYNOS4_GPIO_F3_NR,
2294 #ifdef CONFIG_ARCH_EXYNOS4
2295 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2298 .base = EXYNOS4_GPJ0(0),
2299 .ngpio = EXYNOS4_GPIO_J0_NR,
2304 .base = EXYNOS4_GPJ1(0),
2305 .ngpio = EXYNOS4_GPIO_J1_NR,
2310 .base = EXYNOS4_GPK0(0),
2311 .ngpio = EXYNOS4_GPIO_K0_NR,
2316 .base = EXYNOS4_GPK1(0),
2317 .ngpio = EXYNOS4_GPIO_K1_NR,
2322 .base = EXYNOS4_GPK2(0),
2323 .ngpio = EXYNOS4_GPIO_K2_NR,
2328 .base = EXYNOS4_GPK3(0),
2329 .ngpio = EXYNOS4_GPIO_K3_NR,
2334 .base = EXYNOS4_GPL0(0),
2335 .ngpio = EXYNOS4_GPIO_L0_NR,
2340 .base = EXYNOS4_GPL1(0),
2341 .ngpio = EXYNOS4_GPIO_L1_NR,
2346 .base = EXYNOS4_GPL2(0),
2347 .ngpio = EXYNOS4_GPIO_L2_NR,
2351 .config = &samsung_gpio_cfgs[8],
2353 .base = EXYNOS4_GPY0(0),
2354 .ngpio = EXYNOS4_GPIO_Y0_NR,
2358 .config = &samsung_gpio_cfgs[8],
2360 .base = EXYNOS4_GPY1(0),
2361 .ngpio = EXYNOS4_GPIO_Y1_NR,
2365 .config = &samsung_gpio_cfgs[8],
2367 .base = EXYNOS4_GPY2(0),
2368 .ngpio = EXYNOS4_GPIO_Y2_NR,
2372 .config = &samsung_gpio_cfgs[8],
2374 .base = EXYNOS4_GPY3(0),
2375 .ngpio = EXYNOS4_GPIO_Y3_NR,
2379 .config = &samsung_gpio_cfgs[8],
2381 .base = EXYNOS4_GPY4(0),
2382 .ngpio = EXYNOS4_GPIO_Y4_NR,
2386 .config = &samsung_gpio_cfgs[8],
2388 .base = EXYNOS4_GPY5(0),
2389 .ngpio = EXYNOS4_GPIO_Y5_NR,
2393 .config = &samsung_gpio_cfgs[8],
2395 .base = EXYNOS4_GPY6(0),
2396 .ngpio = EXYNOS4_GPIO_Y6_NR,
2400 .config = &samsung_gpio_cfgs[9],
2401 .irq_base = IRQ_EINT(0),
2403 .base = EXYNOS4_GPX0(0),
2404 .ngpio = EXYNOS4_GPIO_X0_NR,
2406 .to_irq = samsung_gpiolib_to_irq,
2409 .config = &samsung_gpio_cfgs[9],
2410 .irq_base = IRQ_EINT(8),
2412 .base = EXYNOS4_GPX1(0),
2413 .ngpio = EXYNOS4_GPIO_X1_NR,
2415 .to_irq = samsung_gpiolib_to_irq,
2418 .config = &samsung_gpio_cfgs[9],
2419 .irq_base = IRQ_EINT(16),
2421 .base = EXYNOS4_GPX2(0),
2422 .ngpio = EXYNOS4_GPIO_X2_NR,
2424 .to_irq = samsung_gpiolib_to_irq,
2427 .config = &samsung_gpio_cfgs[9],
2428 .irq_base = IRQ_EINT(24),
2430 .base = EXYNOS4_GPX3(0),
2431 .ngpio = EXYNOS4_GPIO_X3_NR,
2433 .to_irq = samsung_gpiolib_to_irq,
2439 #ifdef CONFIG_ARCH_EXYNOS4
2440 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2443 .base = EXYNOS4_GPZ(0),
2444 .ngpio = EXYNOS4_GPIO_Z_NR,
2451 #ifdef CONFIG_SOC_EXYNOS5250
2452 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2455 .base = EXYNOS5_GPA0(0),
2456 .ngpio = EXYNOS5_GPIO_A0_NR,
2461 .base = EXYNOS5_GPA1(0),
2462 .ngpio = EXYNOS5_GPIO_A1_NR,
2467 .base = EXYNOS5_GPA2(0),
2468 .ngpio = EXYNOS5_GPIO_A2_NR,
2473 .base = EXYNOS5_GPB0(0),
2474 .ngpio = EXYNOS5_GPIO_B0_NR,
2479 .base = EXYNOS5_GPB1(0),
2480 .ngpio = EXYNOS5_GPIO_B1_NR,
2485 .base = EXYNOS5_GPB2(0),
2486 .ngpio = EXYNOS5_GPIO_B2_NR,
2491 .base = EXYNOS5_GPB3(0),
2492 .ngpio = EXYNOS5_GPIO_B3_NR,
2497 .base = EXYNOS5_GPC0(0),
2498 .ngpio = EXYNOS5_GPIO_C0_NR,
2503 .base = EXYNOS5_GPC1(0),
2504 .ngpio = EXYNOS5_GPIO_C1_NR,
2509 .base = EXYNOS5_GPC2(0),
2510 .ngpio = EXYNOS5_GPIO_C2_NR,
2515 .base = EXYNOS5_GPC3(0),
2516 .ngpio = EXYNOS5_GPIO_C3_NR,
2521 .base = EXYNOS5_GPD0(0),
2522 .ngpio = EXYNOS5_GPIO_D0_NR,
2527 .base = EXYNOS5_GPD1(0),
2528 .ngpio = EXYNOS5_GPIO_D1_NR,
2533 .base = EXYNOS5_GPY0(0),
2534 .ngpio = EXYNOS5_GPIO_Y0_NR,
2539 .base = EXYNOS5_GPY1(0),
2540 .ngpio = EXYNOS5_GPIO_Y1_NR,
2545 .base = EXYNOS5_GPY2(0),
2546 .ngpio = EXYNOS5_GPIO_Y2_NR,
2551 .base = EXYNOS5_GPY3(0),
2552 .ngpio = EXYNOS5_GPIO_Y3_NR,
2557 .base = EXYNOS5_GPY4(0),
2558 .ngpio = EXYNOS5_GPIO_Y4_NR,
2563 .base = EXYNOS5_GPY5(0),
2564 .ngpio = EXYNOS5_GPIO_Y5_NR,
2569 .base = EXYNOS5_GPY6(0),
2570 .ngpio = EXYNOS5_GPIO_Y6_NR,
2575 .base = EXYNOS5_GPC4(0),
2576 .ngpio = EXYNOS5_GPIO_C4_NR,
2580 .config = &samsung_gpio_cfgs[9],
2581 .irq_base = IRQ_EINT(0),
2583 .base = EXYNOS5_GPX0(0),
2584 .ngpio = EXYNOS5_GPIO_X0_NR,
2586 .to_irq = samsung_gpiolib_to_irq,
2589 .config = &samsung_gpio_cfgs[9],
2590 .irq_base = IRQ_EINT(8),
2592 .base = EXYNOS5_GPX1(0),
2593 .ngpio = EXYNOS5_GPIO_X1_NR,
2595 .to_irq = samsung_gpiolib_to_irq,
2598 .config = &samsung_gpio_cfgs[9],
2599 .irq_base = IRQ_EINT(16),
2601 .base = EXYNOS5_GPX2(0),
2602 .ngpio = EXYNOS5_GPIO_X2_NR,
2604 .to_irq = samsung_gpiolib_to_irq,
2607 .config = &samsung_gpio_cfgs[9],
2608 .irq_base = IRQ_EINT(24),
2610 .base = EXYNOS5_GPX3(0),
2611 .ngpio = EXYNOS5_GPIO_X3_NR,
2613 .to_irq = samsung_gpiolib_to_irq,
2619 #ifdef CONFIG_SOC_EXYNOS5250
2620 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2623 .base = EXYNOS5_GPE0(0),
2624 .ngpio = EXYNOS5_GPIO_E0_NR,
2629 .base = EXYNOS5_GPE1(0),
2630 .ngpio = EXYNOS5_GPIO_E1_NR,
2635 .base = EXYNOS5_GPF0(0),
2636 .ngpio = EXYNOS5_GPIO_F0_NR,
2641 .base = EXYNOS5_GPF1(0),
2642 .ngpio = EXYNOS5_GPIO_F1_NR,
2647 .base = EXYNOS5_GPG0(0),
2648 .ngpio = EXYNOS5_GPIO_G0_NR,
2653 .base = EXYNOS5_GPG1(0),
2654 .ngpio = EXYNOS5_GPIO_G1_NR,
2659 .base = EXYNOS5_GPG2(0),
2660 .ngpio = EXYNOS5_GPIO_G2_NR,
2665 .base = EXYNOS5_GPH0(0),
2666 .ngpio = EXYNOS5_GPIO_H0_NR,
2671 .base = EXYNOS5_GPH1(0),
2672 .ngpio = EXYNOS5_GPIO_H1_NR,
2680 #ifdef CONFIG_SOC_EXYNOS5250
2681 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2684 .base = EXYNOS5_GPV0(0),
2685 .ngpio = EXYNOS5_GPIO_V0_NR,
2690 .base = EXYNOS5_GPV1(0),
2691 .ngpio = EXYNOS5_GPIO_V1_NR,
2696 .base = EXYNOS5_GPV2(0),
2697 .ngpio = EXYNOS5_GPIO_V2_NR,
2702 .base = EXYNOS5_GPV3(0),
2703 .ngpio = EXYNOS5_GPIO_V3_NR,
2708 .base = EXYNOS5_GPV4(0),
2709 .ngpio = EXYNOS5_GPIO_V4_NR,
2716 #ifdef CONFIG_SOC_EXYNOS5250
2717 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2720 .base = EXYNOS5_GPZ(0),
2721 .ngpio = EXYNOS5_GPIO_Z_NR,
2729 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2730 static int exynos_gpio_xlate(struct gpio_chip *gc,
2731 const struct of_phandle_args *gpiospec, u32 *flags)
2735 if (WARN_ON(gc->of_gpio_n_cells < 4))
2738 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2741 if (gpiospec->args[0] > gc->ngpio)
2744 pin = gc->base + gpiospec->args[0];
2746 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2747 pr_warn("gpio_xlate: failed to set pin function\n");
2748 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2749 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2750 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2751 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2754 *flags = gpiospec->args[2] >> 16;
2756 return gpiospec->args[0];
2759 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2760 { .compatible = "samsung,exynos4-gpio", },
2764 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2765 u64 base, u64 offset)
2767 struct gpio_chip *gc = &chip->chip;
2770 if (!of_have_populated_dt())
2773 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2774 gc->of_node = of_find_matching_node_by_address(NULL,
2775 exynos_gpio_dt_match, address);
2777 pr_info("gpio: device tree node not found for gpio controller"
2778 " with base address %08llx\n", address);
2781 gc->of_gpio_n_cells = 4;
2782 gc->of_xlate = exynos_gpio_xlate;
2784 #elif defined(CONFIG_ARCH_EXYNOS)
2785 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2786 u64 base, u64 offset)
2790 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2792 static __init void exynos4_gpiolib_init(void)
2794 #ifdef CONFIG_CPU_EXYNOS4210
2795 struct samsung_gpio_chip *chip;
2797 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2799 void __iomem *gpx_base;
2802 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2803 if (gpio_base1 == NULL) {
2804 pr_err("unable to ioremap for gpio_base1\n");
2808 chip = exynos4_gpios_1;
2809 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2811 for (i = 0; i < nr_chips; i++, chip++) {
2812 if (!chip->config) {
2813 chip->config = &exynos_gpio_cfg;
2814 chip->group = group++;
2816 exynos_gpiolib_attach_ofnode(chip,
2817 EXYNOS4_PA_GPIO1, i * 0x20);
2819 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2820 nr_chips, gpio_base1);
2823 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2824 if (gpio_base2 == NULL) {
2825 pr_err("unable to ioremap for gpio_base2\n");
2829 /* need to set base address for gpx */
2830 chip = &exynos4_gpios_2[16];
2831 gpx_base = gpio_base2 + 0xC00;
2832 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2833 chip->base = gpx_base;
2835 chip = exynos4_gpios_2;
2836 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2838 for (i = 0; i < nr_chips; i++, chip++) {
2839 if (!chip->config) {
2840 chip->config = &exynos_gpio_cfg;
2841 chip->group = group++;
2843 exynos_gpiolib_attach_ofnode(chip,
2844 EXYNOS4_PA_GPIO2, i * 0x20);
2846 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2847 nr_chips, gpio_base2);
2850 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2851 if (gpio_base3 == NULL) {
2852 pr_err("unable to ioremap for gpio_base3\n");
2856 chip = exynos4_gpios_3;
2857 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2859 for (i = 0; i < nr_chips; i++, chip++) {
2860 if (!chip->config) {
2861 chip->config = &exynos_gpio_cfg;
2862 chip->group = group++;
2864 exynos_gpiolib_attach_ofnode(chip,
2865 EXYNOS4_PA_GPIO3, i * 0x20);
2867 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2868 nr_chips, gpio_base3);
2870 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2871 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2872 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2878 iounmap(gpio_base2);
2880 iounmap(gpio_base1);
2883 #endif /* CONFIG_CPU_EXYNOS4210 */
2886 static __init void exynos5_gpiolib_init(void)
2888 #ifdef CONFIG_SOC_EXYNOS5250
2889 struct samsung_gpio_chip *chip;
2891 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2893 void __iomem *gpx_base;
2896 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2897 if (gpio_base1 == NULL) {
2898 pr_err("unable to ioremap for gpio_base1\n");
2902 /* need to set base address for gpc4 */
2903 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2905 /* need to set base address for gpx */
2906 chip = &exynos5_gpios_1[21];
2907 gpx_base = gpio_base1 + 0xC00;
2908 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2909 chip->base = gpx_base;
2911 chip = exynos5_gpios_1;
2912 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2914 for (i = 0; i < nr_chips; i++, chip++) {
2915 if (!chip->config) {
2916 chip->config = &exynos_gpio_cfg;
2917 chip->group = group++;
2919 exynos_gpiolib_attach_ofnode(chip,
2920 EXYNOS5_PA_GPIO1, i * 0x20);
2922 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2923 nr_chips, gpio_base1);
2926 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2927 if (gpio_base2 == NULL) {
2928 pr_err("unable to ioremap for gpio_base2\n");
2932 chip = exynos5_gpios_2;
2933 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2935 for (i = 0; i < nr_chips; i++, chip++) {
2936 if (!chip->config) {
2937 chip->config = &exynos_gpio_cfg;
2938 chip->group = group++;
2940 exynos_gpiolib_attach_ofnode(chip,
2941 EXYNOS5_PA_GPIO2, i * 0x20);
2943 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2944 nr_chips, gpio_base2);
2947 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2948 if (gpio_base3 == NULL) {
2949 pr_err("unable to ioremap for gpio_base3\n");
2953 /* need to set base address for gpv */
2954 exynos5_gpios_3[0].base = gpio_base3;
2955 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2956 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2957 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2958 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2960 chip = exynos5_gpios_3;
2961 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2963 for (i = 0; i < nr_chips; i++, chip++) {
2964 if (!chip->config) {
2965 chip->config = &exynos_gpio_cfg;
2966 chip->group = group++;
2968 exynos_gpiolib_attach_ofnode(chip,
2969 EXYNOS5_PA_GPIO3, i * 0x20);
2971 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2972 nr_chips, gpio_base3);
2975 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2976 if (gpio_base4 == NULL) {
2977 pr_err("unable to ioremap for gpio_base4\n");
2981 chip = exynos5_gpios_4;
2982 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2984 for (i = 0; i < nr_chips; i++, chip++) {
2985 if (!chip->config) {
2986 chip->config = &exynos_gpio_cfg;
2987 chip->group = group++;
2989 exynos_gpiolib_attach_ofnode(chip,
2990 EXYNOS5_PA_GPIO4, i * 0x20);
2992 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2993 nr_chips, gpio_base4);
2997 iounmap(gpio_base3);
2999 iounmap(gpio_base2);
3001 iounmap(gpio_base1);
3005 #endif /* CONFIG_SOC_EXYNOS5250 */
3008 /* TODO: cleanup soc_is_* */
3009 static __init int samsung_gpiolib_init(void)
3011 struct samsung_gpio_chip *chip;
3015 #if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
3017 * This gpio driver includes support for device tree support and there
3018 * are platforms using it. In order to maintain compatibility with those
3019 * platforms, and to allow non-dt Exynos4210 platforms to use this
3020 * gpiolib support, a check is added to find out if there is a active
3021 * pin-controller driver support available. If it is available, this
3022 * gpiolib support is ignored and the gpiolib support available in
3023 * pin-controller driver is used. This is a temporary check and will go
3024 * away when all of the Exynos4210 platforms have switched to using
3025 * device tree and the pin-ctrl driver.
3027 struct device_node *pctrl_np;
3028 static const struct of_device_id exynos_pinctrl_ids[] = {
3029 { .compatible = "samsung,exynos4210-pinctrl", },
3030 { .compatible = "samsung,exynos4x12-pinctrl", },
3031 { .compatible = "samsung,exynos5250-pinctrl", },
3032 { .compatible = "samsung,exynos5440-pinctrl", },
3035 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3036 if (pctrl_np && of_device_is_available(pctrl_np))
3040 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3042 if (soc_is_s3c24xx()) {
3043 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3044 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3045 } else if (soc_is_s3c64xx()) {
3046 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3047 ARRAY_SIZE(s3c64xx_gpios_2bit),
3048 S3C64XX_VA_GPIO + 0xE0, 0x20);
3049 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3050 ARRAY_SIZE(s3c64xx_gpios_4bit),
3052 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3053 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3054 } else if (soc_is_s5p6440()) {
3055 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3056 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3057 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3058 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3059 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3060 ARRAY_SIZE(s5p6440_gpios_4bit2));
3061 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3062 ARRAY_SIZE(s5p6440_gpios_rbank));
3063 } else if (soc_is_s5p6450()) {
3064 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3065 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3066 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3067 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3068 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3069 ARRAY_SIZE(s5p6450_gpios_4bit2));
3070 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3071 ARRAY_SIZE(s5p6450_gpios_rbank));
3072 } else if (soc_is_s5pc100()) {
3074 chip = s5pc100_gpios_4bit;
3075 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3077 for (i = 0; i < nr_chips; i++, chip++) {
3078 if (!chip->config) {
3079 chip->config = &samsung_gpio_cfgs[3];
3080 chip->group = group++;
3083 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3084 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3085 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3087 } else if (soc_is_s5pv210()) {
3089 chip = s5pv210_gpios_4bit;
3090 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3092 for (i = 0; i < nr_chips; i++, chip++) {
3093 if (!chip->config) {
3094 chip->config = &samsung_gpio_cfgs[3];
3095 chip->group = group++;
3098 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3099 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3100 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3102 } else if (soc_is_exynos4210()) {
3103 exynos4_gpiolib_init();
3104 } else if (soc_is_exynos5250()) {
3105 exynos5_gpiolib_init();
3107 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3113 core_initcall(samsung_gpiolib_init);
3115 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3117 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3118 unsigned long flags;
3125 offset = pin - chip->chip.base;
3127 samsung_gpio_lock(chip, flags);
3128 ret = samsung_gpio_do_setcfg(chip, offset, config);
3129 samsung_gpio_unlock(chip, flags);
3133 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3135 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3140 for (; nr > 0; nr--, start++) {
3141 ret = s3c_gpio_cfgpin(start, cfg);
3148 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3150 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3151 unsigned int cfg, samsung_gpio_pull_t pull)
3155 for (; nr > 0; nr--, start++) {
3156 s3c_gpio_setpull(start, pull);
3157 ret = s3c_gpio_cfgpin(start, cfg);
3164 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3166 unsigned s3c_gpio_getcfg(unsigned int pin)
3168 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3169 unsigned long flags;
3174 offset = pin - chip->chip.base;
3176 samsung_gpio_lock(chip, flags);
3177 ret = samsung_gpio_do_getcfg(chip, offset);
3178 samsung_gpio_unlock(chip, flags);
3183 EXPORT_SYMBOL(s3c_gpio_getcfg);
3185 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3187 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3188 unsigned long flags;
3194 offset = pin - chip->chip.base;
3196 samsung_gpio_lock(chip, flags);
3197 ret = samsung_gpio_do_setpull(chip, offset, pull);
3198 samsung_gpio_unlock(chip, flags);
3202 EXPORT_SYMBOL(s3c_gpio_setpull);
3204 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3206 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3207 unsigned long flags;
3212 offset = pin - chip->chip.base;
3214 samsung_gpio_lock(chip, flags);
3215 pup = samsung_gpio_do_getpull(chip, offset);
3216 samsung_gpio_unlock(chip, flags);
3219 return (__force samsung_gpio_pull_t)pup;
3221 EXPORT_SYMBOL(s3c_gpio_getpull);
3223 #ifdef CONFIG_S5P_GPIO_DRVSTR
3224 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3226 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3235 off = pin - chip->chip.base;
3237 reg = chip->base + 0x0C;
3239 drvstr = __raw_readl(reg);
3240 drvstr = drvstr >> shift;
3243 return (__force s5p_gpio_drvstr_t)drvstr;
3245 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3247 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3249 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3258 off = pin - chip->chip.base;
3260 reg = chip->base + 0x0C;
3262 tmp = __raw_readl(reg);
3263 tmp &= ~(0x3 << shift);
3264 tmp |= drvstr << shift;
3266 __raw_writel(tmp, reg);
3270 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3271 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3273 #ifdef CONFIG_PLAT_S3C24XX
3274 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3276 unsigned long flags;
3277 unsigned long misccr;
3279 local_irq_save(flags);
3280 misccr = __raw_readl(S3C24XX_MISCCR);
3283 __raw_writel(misccr, S3C24XX_MISCCR);
3284 local_irq_restore(flags);
3288 EXPORT_SYMBOL(s3c2410_modify_misccr);