1 /* langwell_gpio.c Moorestown platform Langwell chip GPIO driver
2 * Copyright (c) 2008 - 2009, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 * Moorestown platform Langwell chip.
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/stddef.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/irq.h>
31 #include <linux/gpio.h>
33 struct lnw_gpio_register {
44 struct gpio_chip chip;
45 struct lnw_gpio_register *reg_base;
50 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
52 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
56 gplr = (void __iomem *)(&lnw->reg_base->GPLR[reg]);
57 return readl(gplr) & BIT(offset % 32);
60 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
62 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
64 void __iomem *gpsr, *gpcr;
67 gpsr = (void __iomem *)(&lnw->reg_base->GPSR[reg]);
68 writel(BIT(offset % 32), gpsr);
70 gpcr = (void __iomem *)(&lnw->reg_base->GPCR[reg]);
71 writel(BIT(offset % 32), gpcr);
75 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
77 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
83 gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
84 spin_lock_irqsave(&lnw->lock, flags);
86 value &= ~BIT(offset % 32);
88 spin_unlock_irqrestore(&lnw->lock, flags);
92 static int lnw_gpio_direction_output(struct gpio_chip *chip,
93 unsigned offset, int value)
95 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
100 lnw_gpio_set(chip, offset, value);
101 gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
102 spin_lock_irqsave(&lnw->lock, flags);
104 value |= BIT(offset % 32);;
106 spin_unlock_irqrestore(&lnw->lock, flags);
110 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
112 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
113 return lnw->irq_base + offset;
116 static int lnw_irq_type(unsigned irq, unsigned type)
118 struct lnw_gpio *lnw = get_irq_chip_data(irq);
119 u32 gpio = irq - lnw->irq_base;
123 void __iomem *grer = (void __iomem *)(&lnw->reg_base->GRER[reg]);
124 void __iomem *gfer = (void __iomem *)(&lnw->reg_base->GFER[reg]);
126 if (gpio >= lnw->chip.ngpio)
128 spin_lock_irqsave(&lnw->lock, flags);
129 if (type & IRQ_TYPE_EDGE_RISING)
130 value = readl(grer) | BIT(gpio % 32);
132 value = readl(grer) & (~BIT(gpio % 32));
135 if (type & IRQ_TYPE_EDGE_FALLING)
136 value = readl(gfer) | BIT(gpio % 32);
138 value = readl(gfer) & (~BIT(gpio % 32));
140 spin_unlock_irqrestore(&lnw->lock, flags);
145 static void lnw_irq_unmask(unsigned irq)
149 static void lnw_irq_mask(unsigned irq)
153 static struct irq_chip lnw_irqchip = {
155 .mask = lnw_irq_mask,
156 .unmask = lnw_irq_unmask,
157 .set_type = lnw_irq_type,
160 static struct pci_device_id lnw_gpio_ids[] = {
161 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f) },
164 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
166 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
168 struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq);
173 /* check GPIO controller to check which pin triggered the interrupt */
174 for (reg = 0; reg < lnw->chip.ngpio / 32; reg++) {
175 gedr = (void __iomem *)(&lnw->reg_base->GEDR[reg]);
176 gedr_v = readl(gedr);
179 for (gpio = reg*32; gpio < reg*32+32; gpio++)
180 if (gedr_v & BIT(gpio % 32)) {
181 pr_debug("pin %d triggered\n", gpio);
182 generic_handle_irq(lnw->irq_base + gpio);
184 /* clear the edge detect status bit */
185 writel(gedr_v, gedr);
187 desc->chip->eoi(irq);
190 static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id)
195 resource_size_t start, len;
196 struct lnw_gpio *lnw;
201 retval = pci_enable_device(pdev);
205 retval = pci_request_regions(pdev, "langwell_gpio");
207 dev_err(&pdev->dev, "error requesting resources\n");
210 /* get the irq_base from bar1 */
211 start = pci_resource_start(pdev, 1);
212 len = pci_resource_len(pdev, 1);
213 base = ioremap_nocache(start, len);
215 dev_err(&pdev->dev, "error mapping bar1\n");
218 irq_base = *(u32 *)base;
219 gpio_base = *((u32 *)base + 1);
220 /* release the IO mapping, since we already get the info from bar1 */
222 /* get the register base from bar0 */
223 start = pci_resource_start(pdev, 0);
224 len = pci_resource_len(pdev, 0);
225 base = ioremap_nocache(start, len);
227 dev_err(&pdev->dev, "error mapping bar0\n");
232 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
234 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
238 lnw->reg_base = base;
239 lnw->irq_base = irq_base;
240 lnw->chip.label = dev_name(&pdev->dev);
241 lnw->chip.direction_input = lnw_gpio_direction_input;
242 lnw->chip.direction_output = lnw_gpio_direction_output;
243 lnw->chip.get = lnw_gpio_get;
244 lnw->chip.set = lnw_gpio_set;
245 lnw->chip.to_irq = lnw_gpio_to_irq;
246 lnw->chip.base = gpio_base;
247 lnw->chip.ngpio = 64;
248 lnw->chip.can_sleep = 0;
249 pci_set_drvdata(pdev, lnw);
250 retval = gpiochip_add(&lnw->chip);
252 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
255 set_irq_data(pdev->irq, lnw);
256 set_irq_chained_handler(pdev->irq, lnw_irq_handler);
257 for (i = 0; i < lnw->chip.ngpio; i++) {
258 set_irq_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
259 handle_simple_irq, "demux");
260 set_irq_chip_data(i + lnw->irq_base, lnw);
263 spin_lock_init(&lnw->lock);
270 pci_release_regions(pdev);
272 pci_disable_device(pdev);
277 static struct pci_driver lnw_gpio_driver = {
278 .name = "langwell_gpio",
279 .id_table = lnw_gpio_ids,
280 .probe = lnw_gpio_probe,
283 static int __init lnw_gpio_init(void)
285 return pci_register_driver(&lnw_gpio_driver);
288 device_initcall(lnw_gpio_init);