drivers/gpu/arm/mali400/mali/include/linux/mali/mali_utgard.h

   1 /*
   2  * Copyright (C) 2012-2014 ARM Limited. All rights reserved.
   3  *
   4  * This program is free software and is provided to you under the terms of the GNU General Public License version 2
   5  * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
   6  *
   7  * A copy of the licence is included with the program, and can also be obtained from Free Software
   8  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
   9  */
  10
  11 /**
  12  * @file mali_utgard.h
  13  * Defines types and interface exposed by the Mali Utgard device driver
  14  */
  15
  16 #ifndef __MALI_UTGARD_H__
  17 #define __MALI_UTGARD_H__
  18
  19 #include "mali_osk_types.h"
  20
  21 #define MALI_GPU_NAME_UTGARD "mali-utgard"
  22
  23
  24 #define MALI_OFFSET_GP                    0x00000
  25 #define MALI_OFFSET_GP_MMU                0x03000
  26
  27 #define MALI_OFFSET_PP0                   0x08000
  28 #define MALI_OFFSET_PP0_MMU               0x04000
  29 #define MALI_OFFSET_PP1                   0x0A000
  30 #define MALI_OFFSET_PP1_MMU               0x05000
  31 #define MALI_OFFSET_PP2                   0x0C000
  32 #define MALI_OFFSET_PP2_MMU               0x06000
  33 #define MALI_OFFSET_PP3                   0x0E000
  34 #define MALI_OFFSET_PP3_MMU               0x07000
  35
  36 #define MALI_OFFSET_PP4                   0x28000
  37 #define MALI_OFFSET_PP4_MMU               0x1C000
  38 #define MALI_OFFSET_PP5                   0x2A000
  39 #define MALI_OFFSET_PP5_MMU               0x1D000
  40 #define MALI_OFFSET_PP6                   0x2C000
  41 #define MALI_OFFSET_PP6_MMU               0x1E000
  42 #define MALI_OFFSET_PP7                   0x2E000
  43 #define MALI_OFFSET_PP7_MMU               0x1F000
  44
  45 #define MALI_OFFSET_L2_RESOURCE0          0x01000
  46 #define MALI_OFFSET_L2_RESOURCE1          0x10000
  47 #define MALI_OFFSET_L2_RESOURCE2          0x11000
  48
  49 #define MALI400_OFFSET_L2_CACHE0          MALI_OFFSET_L2_RESOURCE0
  50 #define MALI450_OFFSET_L2_CACHE0          MALI_OFFSET_L2_RESOURCE1
  51 #define MALI450_OFFSET_L2_CACHE1          MALI_OFFSET_L2_RESOURCE0
  52 #define MALI450_OFFSET_L2_CACHE2          MALI_OFFSET_L2_RESOURCE2
  53
  54 #define MALI_OFFSET_BCAST                 0x13000
  55 #define MALI_OFFSET_DLBU                  0x14000
  56
  57 #define MALI_OFFSET_PP_BCAST              0x16000
  58 #define MALI_OFFSET_PP_BCAST_MMU          0x15000
  59
  60 #define MALI_OFFSET_PMU                   0x02000
  61 #define MALI_OFFSET_DMA                   0x12000
  62
  63 /* Mali-300 */
  64
  65 #define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
  66         MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
  67
  68 #define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
  69         MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
  70
  71 /* Mali-400 */
  72
  73 #define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
  74         MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
  75         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
  76         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq)
  77
  78 #define MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
  79         MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
  80         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU)
  81
  82 #define MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
  83         MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
  84         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
  85         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
  86         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq)
  87
  88 #define MALI_GPU_RESOURCES_MALI400_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
  89         MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
  90         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU)
  91
  92 #define MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
  93         MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
  94         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
  95         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
  96         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
  97         MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq)
  98
  99 #define MALI_GPU_RESOURCES_MALI400_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
 100         MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
 101         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU)
 102
 103 #define MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
 104         MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
 105         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
 106         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
 107         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
 108         MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
 109         MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq)
 110
 111 #define MALI_GPU_RESOURCES_MALI400_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
 112         MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
 113         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
 114
 115 /* Mali-450 */
 116 #define MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
 117         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
 118         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
 119         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
 120         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
 121         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
 122         MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
 123         MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
 124         MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
 125         MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
 126         MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
 127
 128 #define MALI_GPU_RESOURCES_MALI450_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
 129         MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
 130         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
 131
 132 #define MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
 133         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
 134         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
 135         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
 136         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
 137         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
 138         MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
 139         MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
 140         MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
 141         MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
 142         MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU)
 143
 144 #define MALI_GPU_RESOURCES_MALI450_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
 145         MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
 146         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
 147
 148 #define MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
 149         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
 150         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
 151         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
 152         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
 153         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
 154         MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
 155         MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \
 156         MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
 157         MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
 158         MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
 159         MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
 160         MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
 161
 162 #define MALI_GPU_RESOURCES_MALI450_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
 163         MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
 164         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
 165
 166 #define MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
 167         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
 168         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
 169         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
 170         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
 171         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
 172         MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
 173         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE2) \
 174         MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP4, pp3_irq, base_addr + MALI_OFFSET_PP4_MMU, pp3_mmu_irq) \
 175         MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + MALI_OFFSET_PP5, pp4_irq, base_addr + MALI_OFFSET_PP5_MMU, pp4_mmu_irq) \
 176         MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + MALI_OFFSET_PP6, pp5_irq, base_addr + MALI_OFFSET_PP6_MMU, pp5_mmu_irq) \
 177         MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
 178         MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
 179         MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
 180         MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
 181         MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
 182
 183 #define MALI_GPU_RESOURCES_MALI450_MP6_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
 184         MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
 185         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
 186
 187 #define MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
 188         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
 189         MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
 190         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
 191         MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
 192         MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
 193         MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
 194         MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \
 195         MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE2) \
 196         MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + MALI_OFFSET_PP4, pp4_irq, base_addr + MALI_OFFSET_PP4_MMU, pp4_mmu_irq) \
 197         MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + MALI_OFFSET_PP5, pp5_irq, base_addr + MALI_OFFSET_PP5_MMU, pp5_mmu_irq) \
 198         MALI_GPU_RESOURCE_PP_WITH_MMU(6, base_addr + MALI_OFFSET_PP6, pp6_irq, base_addr + MALI_OFFSET_PP6_MMU, pp6_mmu_irq) \
 199         MALI_GPU_RESOURCE_PP_WITH_MMU(7, base_addr + MALI_OFFSET_PP7, pp7_irq, base_addr + MALI_OFFSET_PP7_MMU, pp7_mmu_irq) \
 200         MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
 201         MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
 202         MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
 203         MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
 204         MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
 205
 206 #define MALI_GPU_RESOURCES_MALI450_MP8_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
 207         MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
 208         MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
 209
 210 #define MALI_GPU_RESOURCE_L2(addr) \
 211         { \
 212                 .name = "Mali_L2", \
 213                         .flags = IORESOURCE_MEM, \
 214                                  .start = addr, \
 215                                           .end   = addr + 0x200, \
 216         },
 217
 218 #define MALI_GPU_RESOURCE_GP(gp_addr, gp_irq) \
 219         { \
 220                 .name = "Mali_GP", \
 221                         .flags = IORESOURCE_MEM, \
 222                                  .start = gp_addr, \
 223                                           .end =   gp_addr + 0x100, \
 224         }, \
 225         { \
 226                 .name = "Mali_GP_IRQ", \
 227                         .flags = IORESOURCE_IRQ, \
 228                                  .start = gp_irq, \
 229                                           .end   = gp_irq, \
 230         }, \
 231
 232 #define MALI_GPU_RESOURCE_GP_WITH_MMU(gp_addr, gp_irq, gp_mmu_addr, gp_mmu_irq) \
 233         { \
 234                 .name = "Mali_GP", \
 235                         .flags = IORESOURCE_MEM, \
 236                                  .start = gp_addr, \
 237                                           .end =   gp_addr + 0x100, \
 238         }, \
 239         { \
 240                 .name = "Mali_GP_IRQ", \
 241                         .flags = IORESOURCE_IRQ, \
 242                                  .start = gp_irq, \
 243                                           .end   = gp_irq, \
 244         }, \
 245         { \
 246                 .name = "Mali_GP_MMU", \
 247                         .flags = IORESOURCE_MEM, \
 248                                  .start = gp_mmu_addr, \
 249                                           .end =   gp_mmu_addr + 0x100, \
 250         }, \
 251         { \
 252                 .name = "Mali_GP_MMU_IRQ", \
 253                         .flags = IORESOURCE_IRQ, \
 254                                  .start = gp_mmu_irq, \
 255                                           .end =   gp_mmu_irq, \
 256         },
 257
 258 #define MALI_GPU_RESOURCE_PP(pp_addr, pp_irq) \
 259         { \
 260                 .name = "Mali_PP", \
 261                         .flags = IORESOURCE_MEM, \
 262                                  .start = pp_addr, \
 263                                           .end =   pp_addr + 0x1100, \
 264         }, \
 265         { \
 266                 .name = "Mali_PP_IRQ", \
 267                         .flags = IORESOURCE_IRQ, \
 268                                  .start = pp_irq, \
 269                                           .end =   pp_irq, \
 270         }, \
 271
 272 #define MALI_GPU_RESOURCE_PP_WITH_MMU(id, pp_addr, pp_irq, pp_mmu_addr, pp_mmu_irq) \
 273         { \
 274                 .name = "Mali_PP" #id, \
 275                         .flags = IORESOURCE_MEM, \
 276                                  .start = pp_addr, \
 277                                           .end =   pp_addr + 0x1100, \
 278         }, \
 279         { \
 280                 .name = "Mali_PP" #id "_IRQ", \
 281                         .flags = IORESOURCE_IRQ, \
 282                                  .start = pp_irq, \
 283                                           .end =   pp_irq, \
 284         }, \
 285         { \
 286                 .name = "Mali_PP" #id "_MMU", \
 287                         .flags = IORESOURCE_MEM, \
 288                                  .start = pp_mmu_addr, \
 289                                           .end =   pp_mmu_addr + 0x100, \
 290         }, \
 291         { \
 292                 .name = "Mali_PP" #id "_MMU_IRQ", \
 293                         .flags = IORESOURCE_IRQ, \
 294                                  .start = pp_mmu_irq, \
 295                                           .end =   pp_mmu_irq, \
 296         },
 297
 298 #define MALI_GPU_RESOURCE_MMU(mmu_addr, mmu_irq) \
 299         { \
 300                 .name = "Mali_MMU", \
 301                         .flags = IORESOURCE_MEM, \
 302                                  .start = mmu_addr, \
 303                                           .end =   mmu_addr + 0x100, \
 304         }, \
 305         { \
 306                 .name = "Mali_MMU_IRQ", \
 307                         .flags = IORESOURCE_IRQ, \
 308                                  .start = mmu_irq, \
 309                                           .end =   mmu_irq, \
 310         },
 311
 312 #define MALI_GPU_RESOURCE_PMU(pmu_addr) \
 313         { \
 314                 .name = "Mali_PMU", \
 315                         .flags = IORESOURCE_MEM, \
 316                                  .start = pmu_addr, \
 317                                           .end =   pmu_addr + 0x100, \
 318         },
 319
 320 #define MALI_GPU_RESOURCE_DMA(dma_addr) \
 321         { \
 322                 .name = "Mali_DMA", \
 323                         .flags = IORESOURCE_MEM, \
 324                                  .start = dma_addr, \
 325                                           .end = dma_addr + 0x100, \
 326         },
 327
 328 #define MALI_GPU_RESOURCE_DLBU(dlbu_addr) \
 329         { \
 330                 .name = "Mali_DLBU", \
 331                         .flags = IORESOURCE_MEM, \
 332                                  .start = dlbu_addr, \
 333                                           .end = dlbu_addr + 0x100, \
 334         },
 335
 336 #define MALI_GPU_RESOURCE_BCAST(bcast_addr) \
 337         { \
 338                 .name = "Mali_Broadcast", \
 339                         .flags = IORESOURCE_MEM, \
 340                                  .start = bcast_addr, \
 341                                           .end = bcast_addr + 0x100, \
 342         },
 343
 344 #define MALI_GPU_RESOURCE_PP_BCAST(pp_addr, pp_irq) \
 345         { \
 346                 .name = "Mali_PP_Broadcast", \
 347                         .flags = IORESOURCE_MEM, \
 348                                  .start = pp_addr, \
 349                                           .end =   pp_addr + 0x1100, \
 350         }, \
 351         { \
 352                 .name = "Mali_PP_Broadcast_IRQ", \
 353                         .flags = IORESOURCE_IRQ, \
 354                                  .start = pp_irq, \
 355                                           .end =   pp_irq, \
 356         }, \
 357
 358 #define MALI_GPU_RESOURCE_PP_MMU_BCAST(pp_mmu_bcast_addr) \
 359         { \
 360                 .name = "Mali_PP_MMU_Broadcast", \
 361                         .flags = IORESOURCE_MEM, \
 362                                  .start = pp_mmu_bcast_addr, \
 363                                           .end = pp_mmu_bcast_addr + 0x100, \
 364         },
 365
 366 struct mali_gpu_utilization_data {
 367         unsigned int utilization_gpu; /* Utilization for GP and all PP cores combined, 0 = no utilization, 256 = full utilization */
 368         unsigned int utilization_gp;  /* Utilization for GP core only, 0 = no utilization, 256 = full utilization */
 369         unsigned int utilization_pp;  /* Utilization for all PP cores combined, 0 = no utilization, 256 = full utilization */
 370 };
 371
 372 struct mali_gpu_clk_item {
 373         unsigned int clock; /* unit(MHz) */
 374         unsigned int vol;
 375 };
 376
 377 struct mali_gpu_clock {
 378         struct mali_gpu_clk_item *item;
 379         unsigned int num_of_steps;
 380 };
 381
 382 struct mali_gpu_device_data {
 383         /* Shared GPU memory */
 384         unsigned long shared_mem_size;
 385
 386         /*
 387          * Mali PMU switch delay.
 388          * Only needed if the power gates are connected to the PMU in a high fanout
 389          * network. This value is the number of Mali clock cycles it takes to
 390          * enable the power gates and turn on the power mesh.
 391          * This value will have no effect if a daisy chain implementation is used.
 392          */
 393         u32 pmu_switch_delay;
 394
 395         /* Mali Dynamic power domain configuration in sequence from 0-11
 396          *  GP  PP0 PP1  PP2  PP3  PP4  PP5  PP6  PP7, L2$0 L2$1 L2$2
 397          */
 398         u16 pmu_domain_config[12];
 399
 400         /* Dedicated GPU memory range (physical). */
 401         unsigned long dedicated_mem_start;
 402         unsigned long dedicated_mem_size;
 403
 404         /* Frame buffer memory to be accessible by Mali GPU (physical) */
 405         unsigned long fb_start;
 406         unsigned long fb_size;
 407
 408         /* Max runtime [ms] for jobs */
 409         int max_job_runtime;
 410
 411         /* Report GPU utilization and related control in this interval (specified in ms) */
 412         unsigned long control_interval;
 413
 414         /* Function that will receive periodic GPU utilization numbers */
 415         void (*utilization_callback)(struct mali_gpu_utilization_data *data);
 416
 417         /* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
 418         int (*set_freq)(int setting_clock_step);
 419         /* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
 420         void (*get_clock_info)(struct mali_gpu_clock **data);
 421         /* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
 422         int (*get_freq)(void);
 423 };
 424
 425 /**
 426  * Pause the scheduling and power state changes of Mali device driver.
 427  * mali_dev_resume() must always be called as soon as possible after this function
 428  * in order to resume normal operation of the Mali driver.
 429  */
 430 void mali_dev_pause(void);
 431
 432 /**
 433  * Resume scheduling and allow power changes in Mali device driver.
 434  * This must always be called after mali_dev_pause().
 435  */
 436 void mali_dev_resume(void);
 437
 438 /** @brief Set the desired number of PP cores to use.
 439  *
 440  * The internal Mali PMU will be used, if present, to physically power off the PP cores.
 441  *
 442  * @param num_cores The number of desired cores
 443  * @return 0 on success, otherwise error. -EINVAL means an invalid number of cores was specified.
 444  */
 445 int mali_perf_set_num_pp_cores(unsigned int num_cores);
 446
 447 #endif