3 * (C) COPYRIGHT ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
22 * Base structures shared with the kernel.
25 #ifndef _BASE_KERNEL_H_
26 #define _BASE_KERNEL_H_
28 /* For now we support the legacy API as well as the new API */
29 #define BASE_LEGACY_JD_API 1
31 typedef mali_addr64 base_mem_handle;
33 #include "mali_base_mem_priv.h"
34 #include "mali_kbase_profiling_gator_api.h"
37 * Dependency stuff, keep it private for now. May want to expose it if
38 * we decide to make the number of semaphores a configurable
41 #define BASE_JD_ATOM_COUNT 256
43 #define BASEP_JD_SEM_PER_WORD_LOG2 5
44 #define BASEP_JD_SEM_PER_WORD (1 << BASEP_JD_SEM_PER_WORD_LOG2)
45 #define BASEP_JD_SEM_WORD_NR(x) ((x) >> BASEP_JD_SEM_PER_WORD_LOG2)
46 #define BASEP_JD_SEM_MASK_IN_WORD(x) (1 << ((x) & (BASEP_JD_SEM_PER_WORD - 1)))
47 #define BASEP_JD_SEM_ARRAY_SIZE BASEP_JD_SEM_WORD_NR(BASE_JD_ATOM_COUNT)
49 #if BASE_LEGACY_JD_API
50 /* Size of the ring buffer */
51 #define BASEP_JCTX_RB_NRPAGES 4
52 #endif /* BASE_LEGACY_JD_API */
54 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
56 #define BASE_MAX_COHERENT_GROUPS 16
58 #if defined CDBG_ASSERT
59 #define LOCAL_ASSERT CDBG_ASSERT
60 #elif defined KBASE_DEBUG_ASSERT
61 #define LOCAL_ASSERT KBASE_DEBUG_ASSERT
63 #error assert macro not defined!
67 #define LOCAL_PAGE_LSB ~PAGE_MASK
69 #include <osu/mali_osu.h>
71 #if defined OSU_CONFIG_CPU_PAGE_SIZE_LOG2
72 #define LOCAL_PAGE_LSB ((1ul << OSU_CONFIG_CPU_PAGE_SIZE_LOG2) - 1)
74 #error Failed to find page size
78 /** 32/64-bit neutral way to represent pointers */
79 typedef union kbase_pointer {
80 void *value; /**< client should store their pointers here */
81 u32 compat_value; /**< 64-bit kernels should fetch value here when handling 32-bit clients */
82 u64 sizer; /**< Force 64-bit storage for all clients regardless */
86 * @addtogroup base_user_api User-side Base APIs
91 * @addtogroup base_user_api_memory User-side Base Memory APIs
96 * @brief Memory allocation, access/hint flags
98 * A combination of MEM_PROT/MEM_HINT flags must be passed to each allocator
99 * in order to determine the best cache policy. Some combinations are
100 * of course invalid (eg @c MEM_PROT_CPU_WR | @c MEM_HINT_CPU_RD),
101 * which defines a @a write-only region on the CPU side, which is
102 * heavily read by the CPU...
103 * Other flags are only meaningful to a particular allocator.
104 * More flags can be added to this list, as long as they don't clash
105 * (see ::BASE_MEM_FLAGS_NR_BITS for the number of the first free bit).
107 typedef u32 base_mem_alloc_flags;
110 * @brief Memory allocation, access/hint flags
112 * See ::base_mem_alloc_flags.
116 BASE_MEM_PROT_CPU_RD = (1U << 0), /**< Read access CPU side */
117 BASE_MEM_PROT_CPU_WR = (1U << 1), /**< Write access CPU side */
118 BASE_MEM_PROT_GPU_RD = (1U << 2), /**< Read access GPU side */
119 BASE_MEM_PROT_GPU_WR = (1U << 3), /**< Write access GPU side */
120 BASE_MEM_PROT_GPU_EX = (1U << 4), /**< Execute allowed on the GPU side */
122 /* Note that the HINT flags are obsolete now. If you want the memory
123 * to be cached on the CPU please use the BASE_MEM_CACHED_CPU flag
125 BASE_MEM_HINT_CPU_RD = (1U << 5), /**< Heavily read CPU side - OBSOLETE */
126 BASE_MEM_HINT_CPU_WR = (1U << 6), /**< Heavily written CPU side - OBSOLETE */
127 BASE_MEM_HINT_GPU_RD = (1U << 7), /**< Heavily read GPU side - OBSOLETE */
128 BASE_MEM_HINT_GPU_WR = (1U << 8), /**< Heavily written GPU side - OBSOLETE */
130 BASE_MEM_GROW_ON_GPF = (1U << 9), /**< Grow backing store on GPU Page Fault */
132 BASE_MEM_COHERENT_SYSTEM = (1U << 10), /**< Page coherence Outer shareable */
133 BASE_MEM_COHERENT_LOCAL = (1U << 11), /**< Page coherence Inner shareable */
134 BASE_MEM_CACHED_CPU = (1U << 12), /**< Should be cached on the CPU */
136 BASE_MEM_SAME_VA = (1U << 13) /**< Must have same VA on both the GPU and the CPU */
140 * @brief Memory types supported by @a base_mem_import
142 * Each type defines what the supported handle type is.
144 * If any new type is added here ARM must be contacted
145 * to allocate a numeric value for it.
146 * Do not just add a new type without synchronizing with ARM
147 * as future releases from ARM might include other new types
148 * which could clash with your custom types.
150 typedef enum base_mem_import_type {
151 BASE_MEM_IMPORT_TYPE_INVALID = 0,
152 /** UMP import. Handle type is ump_secure_id. */
153 BASE_MEM_IMPORT_TYPE_UMP = 1,
154 /** UMM import. Handle type is a file descriptor (int) */
155 BASE_MEM_IMPORT_TYPE_UMM = 2
156 } base_mem_import_type;
158 /* legacy API wrappers */
159 #define base_tmem_import_type base_mem_import_type
160 #define BASE_TMEM_IMPORT_TYPE_INVALID BASE_MEM_IMPORT_TYPE_INVALID
161 #define BASE_TMEM_IMPORT_TYPE_UMP BASE_MEM_IMPORT_TYPE_UMP
162 #define BASE_TMEM_IMPORT_TYPE_UMM BASE_MEM_IMPORT_TYPE_UMM
165 * @brief Invalid memory handle type.
166 * Return value from functions returning @a base_mem_handle on error.
168 #define BASE_MEM_INVALID_HANDLE (0ull << 12)
169 #define BASE_MEM_MMU_DUMP_HANDLE (1ull << 12)
170 #define BASE_MEM_TRACE_BUFFER_HANDLE (2ull << 12)
171 #define BASE_MEM_MAP_TRACKING_HANDLE (3ull << 12)
172 #define BASE_MEM_WRITE_ALLOC_PAGES_HANDLE (4ull << 12)
173 /* reserved handles ..-64<<PAGE_SHIFT> for future special handles */
174 #define BASE_MEM_COOKIE_BASE (64ul << 12)
175 #define BASE_MEM_FIRST_FREE_ADDRESS ((BITS_PER_LONG << 12) + \
176 BASE_MEM_COOKIE_BASE)
178 /* Bit mask of cookies used for for memory allocation setup */
179 #define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */
182 * @brief Number of bits used as flags for base memory management
184 * Must be kept in sync with the ::base_mem_alloc_flags flags
186 #define BASE_MEM_FLAGS_NR_BITS 14
189 * @brief Result codes of changing the size of the backing store allocated to a tmem region
191 typedef enum base_backing_threshold_status {
192 BASE_BACKING_THRESHOLD_OK = 0, /**< Resize successful */
193 BASE_BACKING_THRESHOLD_ERROR_NOT_GROWABLE = -1, /**< Not a growable tmem object */
194 BASE_BACKING_THRESHOLD_ERROR_OOM = -2, /**< Increase failed due to an out-of-memory condition */
195 BASE_BACKING_THRESHOLD_ERROR_MAPPED = -3, /**< Resize attempted on buffer while it was mapped, which is not permitted */
196 BASE_BACKING_THRESHOLD_ERROR_INVALID_ARGUMENTS = -4 /**< Invalid arguments (not tmem, illegal size request, etc.) */
197 } base_backing_threshold_status;
200 * @addtogroup base_user_api_memory_defered User-side Base Defered Memory Coherency APIs
205 * @brief a basic memory operation (sync-set).
207 * The content of this structure is private, and should only be used
210 typedef struct base_syncset {
211 basep_syncset basep_sset;
214 /** @} end group base_user_api_memory_defered */
217 * Handle to represent imported memory object.
218 * Simple opague handle to imported memory, can't be used
219 * with anything but base_external_resource_init to bind to an atom.
221 typedef struct base_import_handle {
225 } base_import_handle;
227 /** @} end group base_user_api_memory */
230 * @addtogroup base_user_api_job_dispatch User-side Base Job Dispatcher APIs
234 typedef int platform_fence_type;
235 #define INVALID_PLATFORM_FENCE ((platform_fence_type)-1)
238 * Base stream handle.
240 * References an underlying base stream object.
242 typedef struct base_stream {
251 * References an underlying base fence object.
253 typedef struct base_fence {
260 #if BASE_LEGACY_JD_API
262 * @brief A pre- or post- dual dependency.
264 * This structure is used to express either
265 * @li a single or dual pre-dependency (a job depending on one or two
267 * @li a single or dual post-dependency (a job resolving a dependency
268 * for one or two other jobs).
270 * The dependency itself is specified as a u8, where 0 indicates no
271 * dependency. A single dependency is expressed by having one of the
272 * dependencies set to 0.
274 typedef struct base_jd_dep {
275 u8 dep[2]; /**< pre/post dependencies */
277 #endif /* BASE_LEGACY_JD_API */
280 * @brief Per-job data
282 * This structure is used to store per-job data, and is completly unused
283 * by the Base driver. It can be used to store things such as callback
284 * function pointer, data to handle job completion. It is guaranteed to be
285 * untouched by the Base driver.
287 typedef struct base_jd_udata {
288 u64 blob[2]; /**< per-job data array */
292 * @brief Memory aliasing info
294 * Describes a memory handle to be aliased.
295 * A subset of the handle can be chosen for aliasing, given an offset and a
297 * A special handle BASE_MEM_WRITE_ALLOC_PAGES_HANDLE is used to represent a
298 * region where a special page is mapped with a write-alloc cache setup,
299 * typically used when the write result of the GPU isn't needed, but the GPU
302 * Offset and length are specified in pages.
303 * Offset must be within the size of the handle.
304 * Offset+length must not overrun the size of the handle.
306 * @handle Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
307 * @offset Offset within the handle to start aliasing from, in pages.
308 * Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
309 * @length Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
310 * specifies the number of times the special page is needed.
312 struct base_mem_aliasing_info {
313 base_mem_handle handle;
319 * @brief Job dependency type.
321 * A flags field will be inserted into the atom structure to specify whether a dependency is a data or
322 * ordering dependency (by putting it before/after 'core_req' in the structure it should be possible to add without
323 * changing the structure size).
324 * When the flag is set for a particular dependency to signal that it is an ordering only dependency then
325 * errors will not be propagated.
327 typedef u8 base_jd_dep_type;
330 #define BASE_JD_DEP_TYPE_INVALID (0) /**< Invalid dependency */
331 #define BASE_JD_DEP_TYPE_DATA (1U << 0) /**< Data dependency */
332 #define BASE_JD_DEP_TYPE_ORDER (1U << 1) /**< Order dependency */
335 * @brief Job chain hardware requirements.
337 * A job chain must specify what GPU features it needs to allow the
338 * driver to schedule the job correctly. By not specifying the
339 * correct settings can/will cause an early job termination. Multiple
340 * values can be ORed together to specify multiple requirements.
341 * Special case is ::BASE_JD_REQ_DEP, which is used to express complex
342 * dependencies, and that doesn't execute anything on the hardware.
344 typedef u16 base_jd_core_req;
346 /* Requirements that come from the HW */
347 #define BASE_JD_REQ_DEP 0 /**< No requirement, dependency only */
348 #define BASE_JD_REQ_FS (1U << 0) /**< Requires fragment shaders */
350 * Requires compute shaders
351 * This covers any of the following Midgard Job types:
352 * - Vertex Shader Job
353 * - Geometry Shader Job
354 * - An actual Compute Shader Job
356 * Compare this with @ref BASE_JD_REQ_ONLY_COMPUTE, which specifies that the
357 * job is specifically just the "Compute Shader" job type, and not the "Vertex
358 * Shader" nor the "Geometry Shader" job type.
360 #define BASE_JD_REQ_CS (1U << 1)
361 #define BASE_JD_REQ_T (1U << 2) /**< Requires tiling */
362 #define BASE_JD_REQ_CF (1U << 3) /**< Requires cache flushes */
363 #define BASE_JD_REQ_V (1U << 4) /**< Requires value writeback */
365 /* SW-only requirements - the HW does not expose these as part of the job slot capabilities */
367 /* Requires fragment job with AFBC encoding */
368 #define BASE_JD_REQ_FS_AFBC (1U << 13)
371 * SW Only requirement: the job chain requires a coherent core group. We don't
372 * mind which coherent core group is used.
374 #define BASE_JD_REQ_COHERENT_GROUP (1U << 6)
377 * SW Only requirement: The performance counters should be enabled only when
378 * they are needed, to reduce power consumption.
381 #define BASE_JD_REQ_PERMON (1U << 7)
384 * SW Only requirement: External resources are referenced by this atom.
385 * When external resources are referenced no syncsets can be bundled with the atom
386 * but should instead be part of a NULL jobs inserted into the dependency tree.
387 * The first pre_dep object must be configured for the external resouces to use,
388 * the second pre_dep object can be used to create other dependencies.
390 #define BASE_JD_REQ_EXTERNAL_RESOURCES (1U << 8)
393 * SW Only requirement: Software defined job. Jobs with this bit set will not be submitted
394 * to the hardware but will cause some action to happen within the driver
396 #define BASE_JD_REQ_SOFT_JOB (1U << 9)
398 #define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1)
399 #define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2)
400 #define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3)
403 * SW Only requirement : Replay job.
405 * If the preceeding job fails, the replay job will cause the jobs specified in
406 * the list of base_jd_replay_payload pointed to by the jc pointer to be
409 * A replay job will only cause jobs to be replayed up to BASEP_JD_REPLAY_LIMIT
410 * times. If a job fails more than BASEP_JD_REPLAY_LIMIT times then the replay
411 * job is failed, as well as any following dependencies.
413 * The replayed jobs will require a number of atom IDs. If there are not enough
414 * free atom IDs then the replay job will fail.
416 * If the preceeding job does not fail, then the replay job is returned as
419 * The replayed jobs will never be returned to userspace. The preceeding failed
420 * job will be returned to userspace as failed; the status of this job should
421 * be ignored. Completion should be determined by the status of the replay soft
424 * In order for the jobs to be replayed, the job headers will have to be
425 * modified. The Status field will be reset to NOT_STARTED. If the Job Type
426 * field indicates a Vertex Shader Job then it will be changed to Null Job.
428 * The replayed jobs have the following assumptions :
430 * - No external resources. Any required external resources will be held by the
432 * - Pre-dependencies are created based on job order.
433 * - Atom numbers are automatically assigned.
434 * - device_nr is set to 0. This is not relevant as
435 * BASE_JD_REQ_SPECIFIC_COHERENT_GROUP should not be set.
436 * - Priority is inherited from the replay job.
438 #define BASE_JD_REQ_SOFT_REPLAY (BASE_JD_REQ_SOFT_JOB | 0x4)
441 * HW Requirement: Requires Compute shaders (but not Vertex or Geometry Shaders)
443 * This indicates that the Job Chain contains Midgard Jobs of the 'Compute Shaders' type.
445 * In contrast to @ref BASE_JD_REQ_CS, this does \b not indicate that the Job
446 * Chain contains 'Geometry Shader' or 'Vertex Shader' jobs.
448 * @note This is a more flexible variant of the @ref BASE_CONTEXT_HINT_ONLY_COMPUTE flag,
449 * allowing specific jobs to be marked as 'Only Compute' instead of the entire context
451 #define BASE_JD_REQ_ONLY_COMPUTE (1U << 10)
454 * HW Requirement: Use the base_jd_atom::device_nr field to specify a
455 * particular core group
457 * If both BASE_JD_REQ_COHERENT_GROUP and this flag are set, this flag takes priority
459 * This is only guaranteed to work for BASE_JD_REQ_ONLY_COMPUTE atoms.
461 * If the core availability policy is keeping the required core group turned off, then
462 * the job will fail with a BASE_JD_EVENT_PM_EVENT error code.
464 #define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP (1U << 11)
467 * SW Flag: If this bit is set then the successful completion of this atom
468 * will not cause an event to be sent to userspace
470 #define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE (1U << 12)
473 * SW Flag: If this bit is set then completion of this atom will not cause an
474 * event to be sent to userspace, whether successful or not.
476 #define BASEP_JD_REQ_EVENT_NEVER (1U << 14)
479 * These requirement bits are currently unused in base_jd_core_req (currently a u16)
482 #define BASEP_JD_REQ_RESERVED_BIT5 (1U << 5)
483 #define BASEP_JD_REQ_RESERVED_BIT15 (1U << 15)
486 * Mask of all the currently unused requirement bits in base_jd_core_req.
489 #define BASEP_JD_REQ_RESERVED (BASEP_JD_REQ_RESERVED_BIT5 | \
490 BASEP_JD_REQ_RESERVED_BIT15)
493 * Mask of all bits in base_jd_core_req that control the type of the atom.
495 * This allows dependency only atoms to have flags set
497 #define BASEP_JD_REQ_ATOM_TYPE (~(BASEP_JD_REQ_RESERVED | BASE_JD_REQ_EVENT_ONLY_ON_FAILURE |\
498 BASE_JD_REQ_EXTERNAL_RESOURCES | BASEP_JD_REQ_EVENT_NEVER))
500 #if BASE_LEGACY_JD_API
502 * @brief A single job chain, with pre/post dependendencies and mem ops
504 * This structure is used to describe a single job-chain to be submitted
506 * It contains all the necessary information for Base to take care of this
507 * job-chain, including core requirements, priority, syncsets and
510 typedef struct base_jd_atom {
511 mali_addr64 jc; /**< job-chain GPU address */
512 base_jd_udata udata; /**< user data */
513 base_jd_dep pre_dep; /**< pre-dependencies */
514 base_jd_dep post_dep; /**< post-dependencies */
515 base_jd_core_req core_req; /**< core requirements */
516 u16 nr_syncsets; /**< nr of syncsets following the atom */
517 u16 nr_extres; /**< nr of external resources following the atom */
519 /** @brief Relative priority.
521 * A positive value requests a lower priority, whilst a negative value
522 * requests a higher priority. Only privileged processes may request a
523 * higher priority. For unprivileged processes, a negative priority will
524 * be interpreted as zero.
529 * @brief Device number to use, depending on @ref base_jd_core_req flags set.
531 * When BASE_JD_REQ_SPECIFIC_COHERENT_GROUP is set, a 'device' is one of
532 * the coherent core groups, and so this targets a particular coherent
533 * core-group. They are numbered from 0 to (mali_base_gpu_coherent_group_info::num_groups - 1),
534 * and the cores targeted by this device_nr will usually be those specified by
535 * (mali_base_gpu_coherent_group_info::group[device_nr].core_mask).
536 * Further, two atoms from different processes using the same \a device_nr
537 * at the same time will always target the same coherent core-group.
539 * There are exceptions to when the device_nr is ignored:
540 * - when any process in the system uses a BASE_JD_REQ_CS or
541 * BASE_JD_REQ_ONLY_COMPUTE atom that can run on all cores across all
542 * coherency groups (i.e. also does \b not have the
543 * BASE_JD_REQ_COHERENT_GROUP or BASE_JD_REQ_SPECIFIC_COHERENT_GROUP flags
544 * set). In this case, such atoms would block device_nr==1 being used due
545 * to restrictions on affinity, perhaps indefinitely. To ensure progress is
546 * made, the atoms targeted for device_nr 1 will instead be redirected to
548 * - During certain HW workarounds, such as BASE_HW_ISSUE_8987, where
549 * BASE_JD_REQ_ONLY_COMPUTE atoms must not use the same cores as other
550 * atoms. In this case, all atoms are targeted to device_nr == min( num_groups, 1 )
552 * Note that the 'device' number for a coherent coregroup cannot exceed
553 * (BASE_MAX_COHERENT_GROUPS - 1).
557 #endif /* BASE_LEGACY_JD_API */
559 typedef u8 base_atom_id; /**< Type big enough to store an atom number in */
561 struct base_dependency {
562 base_atom_id atom_id; /**< An atom number */
563 base_jd_dep_type dependency_type; /**< Dependency type */
566 typedef struct base_jd_atom_v2 {
567 mali_addr64 jc; /**< job-chain GPU address */
568 base_jd_udata udata; /**< user data */
569 kbase_pointer extres_list; /**< list of external resources */
570 u16 nr_extres; /**< nr of external resources */
571 base_jd_core_req core_req; /**< core requirements */
572 const struct base_dependency pre_dep[2]; /**< pre-dependencies, one need to use SETTER function to assign this field,
573 this is done in order to reduce possibility of improper assigment of a dependency field */
574 base_atom_id atom_number; /**< unique number to identify the atom */
575 s8 prio; /**< priority - smaller is higher priority */
576 u8 device_nr; /**< coregroup when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP specified */
580 #if BASE_LEGACY_JD_API
581 /* Structure definition works around the fact that C89 doesn't allow arrays of size 0 */
582 typedef struct basep_jd_atom_ss {
584 base_syncset syncsets[1];
586 #endif /* BASE_LEGACY_JD_API */
588 typedef enum base_external_resource_access {
589 BASE_EXT_RES_ACCESS_SHARED,
590 BASE_EXT_RES_ACCESS_EXCLUSIVE
591 } base_external_resource_access;
593 typedef struct base_external_resource {
595 } base_external_resource;
597 #if BASE_LEGACY_JD_API
598 /* Structure definition works around the fact that C89 doesn't allow arrays of size 0 */
599 typedef struct basep_jd_atom_ext_res {
601 base_external_resource resources[1];
602 } basep_jd_atom_ext_res;
604 static INLINE size_t base_jd_atom_size_ex(u32 syncset_count, u32 external_res_count)
608 LOCAL_ASSERT(0 == syncset_count || 0 == external_res_count);
610 size = syncset_count ? offsetof(basep_jd_atom_ss, syncsets[0]) + (sizeof(base_syncset) * syncset_count) : external_res_count ? offsetof(basep_jd_atom_ext_res, resources[0]) + (sizeof(base_external_resource) * external_res_count) : sizeof(base_jd_atom);
612 /* Atom minimum size set to 64 bytes to ensure that the maximum
613 * number of atoms in the ring buffer is limited to 256 */
614 return MAX(64, size);
618 * @brief Atom size evaluator
620 * This function returns the size in bytes of a ::base_jd_atom
621 * containing @a n syncsets. It must be used to compute the size of a
622 * bag before allocation.
624 * @param nr the number of syncsets for this atom
625 * @return the atom size in bytes
627 static INLINE size_t base_jd_atom_size(u32 nr)
629 return base_jd_atom_size_ex(nr, 0);
633 * @brief Atom syncset accessor
635 * This function returns a pointer to the nth syncset allocated
636 * together with an atom.
638 * @param[in] atom The allocated atom
639 * @param n The number of the syncset to be returned
640 * @return a pointer to the nth syncset.
642 static INLINE base_syncset *base_jd_get_atom_syncset(base_jd_atom *atom, u16 n)
644 LOCAL_ASSERT(atom != NULL);
645 LOCAL_ASSERT(0 == (atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES));
646 LOCAL_ASSERT(n <= atom->nr_syncsets);
647 return &((basep_jd_atom_ss *) atom)->syncsets[n];
649 #endif /* BASE_LEGACY_JD_API */
653 * @brief Setter for a dependency structure
655 * @param[in] dep The kbase jd atom dependency to be initialized.
656 * @param id The atom_id to be assigned.
657 * @param dep_type The dep_type to be assigned.
660 static INLINE void base_jd_atom_dep_set(const struct base_dependency* const_dep, base_atom_id id, base_jd_dep_type dep_type)
662 struct base_dependency* dep;
664 LOCAL_ASSERT(const_dep != NULL);
665 /* make sure we don't set not allowed combinations of atom_id/dependency_type */
666 LOCAL_ASSERT( ( id == 0 && dep_type == BASE_JD_DEP_TYPE_INVALID) ||
667 (id > 0 && dep_type != BASE_JD_DEP_TYPE_INVALID) );
669 dep = REINTERPRET_CAST(struct base_dependency*)const_dep;
672 dep->dependency_type = dep_type;
676 * @brief Make a copy of a dependency structure
678 * @param[in,out] dep The kbase jd atom dependency to be written.
679 * @param[in] from The dependency to make a copy from.
682 static INLINE void base_jd_atom_dep_copy(const struct base_dependency* const_dep, const struct base_dependency* from)
684 LOCAL_ASSERT(const_dep != NULL);
686 base_jd_atom_dep_set(const_dep, from->atom_id, from->dependency_type);
690 * @brief Soft-atom fence trigger setup.
692 * Sets up an atom to be a SW-only atom signaling a fence
693 * when it reaches the run state.
695 * Using the existing base dependency system the fence can
696 * be set to trigger when a GPU job has finished.
698 * The base fence object must not be terminated until the atom
699 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
701 * @a fence must be a valid fence set up with @a base_fence_init.
702 * Calling this function with a uninitialized fence results in undefined behavior.
704 * @param[out] atom A pre-allocated atom to configure as a fence trigger SW atom
705 * @param[in] fence The base fence object to trigger.
707 static INLINE void base_jd_fence_trigger_setup(base_jd_atom * const atom, base_fence *fence)
711 LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
712 LOCAL_ASSERT(fence->basep.stream_fd >= 0);
713 atom->jc = (uintptr_t) fence;
714 atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
717 static INLINE void base_jd_fence_trigger_setup_v2(base_jd_atom_v2 *atom, base_fence *fence)
721 LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
722 LOCAL_ASSERT(fence->basep.stream_fd >= 0);
723 atom->jc = (uintptr_t) fence;
724 atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
728 * @brief Soft-atom fence wait setup.
730 * Sets up an atom to be a SW-only atom waiting on a fence.
731 * When the fence becomes triggered the atom becomes runnable
732 * and completes immediately.
734 * Using the existing base dependency system the fence can
735 * be set to block a GPU job until it has been triggered.
737 * The base fence object must not be terminated until the atom
738 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
740 * @a fence must be a valid fence set up with @a base_fence_init or @a base_fence_import.
741 * Calling this function with a uninitialized fence results in undefined behavior.
743 * @param[out] atom A pre-allocated atom to configure as a fence wait SW atom
744 * @param[in] fence The base fence object to wait on
746 static INLINE void base_jd_fence_wait_setup(base_jd_atom * const atom, base_fence *fence)
750 LOCAL_ASSERT(fence->basep.fd >= 0);
751 atom->jc = (uintptr_t) fence;
752 atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
755 static INLINE void base_jd_fence_wait_setup_v2(base_jd_atom_v2 *atom, base_fence *fence)
759 LOCAL_ASSERT(fence->basep.fd >= 0);
760 atom->jc = (uintptr_t) fence;
761 atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
764 #if BASE_LEGACY_JD_API
766 * @brief Atom external resource accessor
768 * This functions returns a pointer to the nth external resource tracked by the atom.
770 * @param[in] atom The allocated atom
771 * @param n The number of the external resource to return a pointer to
772 * @return a pointer to the nth external resource
774 static INLINE base_external_resource * base_jd_get_external_resource(base_jd_atom *atom, u16 n)
776 LOCAL_ASSERT(atom != NULL);
777 LOCAL_ASSERT(BASE_JD_REQ_EXTERNAL_RESOURCES == (atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES));
778 LOCAL_ASSERT(n <= atom->nr_extres);
779 return &((basep_jd_atom_ext_res *) atom)->resources[n];
781 #endif /* BASE_LEGACY_JD_API */
784 * @brief External resource info initialization.
786 * Sets up a external resource object to reference
787 * a memory allocation and the type of access requested.
789 * @param[in] res The resource object to initialize
790 * @param handle The handle to the imported memory object
791 * @param access The type of access requested
793 static INLINE void base_external_resource_init(base_external_resource * res, base_import_handle handle, base_external_resource_access access)
796 address = handle.basep.handle;
798 LOCAL_ASSERT(res != NULL);
799 LOCAL_ASSERT(0 == (address & LOCAL_PAGE_LSB));
800 LOCAL_ASSERT(access == BASE_EXT_RES_ACCESS_SHARED || access == BASE_EXT_RES_ACCESS_EXCLUSIVE);
802 res->ext_resource = address | (access & LOCAL_PAGE_LSB);
805 #if BASE_LEGACY_JD_API
807 * @brief Next atom accessor
809 * This function returns a pointer to the next allocated atom. It
810 * relies on the fact that the current atom has been correctly
811 * initialized (relies on the base_jd_atom::nr_syncsets field).
813 * @param[in] atom The allocated atom
814 * @return a pointer to the next atom.
816 static INLINE base_jd_atom *base_jd_get_next_atom(base_jd_atom *atom)
818 LOCAL_ASSERT(atom != NULL);
819 return (atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES) ? (base_jd_atom *) base_jd_get_external_resource(atom, atom->nr_extres) : (base_jd_atom *) base_jd_get_atom_syncset(atom, atom->nr_syncsets);
821 #endif /* BASE_LEGACY_JD_API */
824 * @brief Job chain event code bits
825 * Defines the bits used to create ::base_jd_event_code
828 BASE_JD_SW_EVENT_KERNEL = (1u << 15), /**< Kernel side event */
829 BASE_JD_SW_EVENT = (1u << 14), /**< SW defined event */
830 BASE_JD_SW_EVENT_SUCCESS = (1u << 13), /**< Event idicates success (SW events only) */
831 BASE_JD_SW_EVENT_JOB = (0u << 11), /**< Job related event */
832 BASE_JD_SW_EVENT_BAG = (1u << 11), /**< Bag related event */
833 BASE_JD_SW_EVENT_INFO = (2u << 11), /**< Misc/info event */
834 BASE_JD_SW_EVENT_RESERVED = (3u << 11), /**< Reserved event type */
835 BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11) /**< Mask to extract the type from an event code */
839 * @brief Job chain event codes
841 * HW and low-level SW events are represented by event codes.
842 * The status of jobs which succeeded are also represented by
843 * an event code (see ::BASE_JD_EVENT_DONE).
844 * Events are usually reported as part of a ::base_jd_event.
846 * The event codes are encoded in the following way:
849 * @li 13 - SW success (only valid if the SW bit is set)
850 * @li 14 - SW event (HW event if not set)
851 * @li 15 - Kernel event (should never be seen in userspace)
853 * Events are split up into ranges as follows:
854 * - BASE_JD_EVENT_RANGE_\<description\>_START
855 * - BASE_JD_EVENT_RANGE_\<description\>_END
857 * \a code is in \<description\>'s range when:
858 * - <tt>BASE_JD_EVENT_RANGE_\<description\>_START <= code < BASE_JD_EVENT_RANGE_\<description\>_END </tt>
860 * Ranges can be asserted for adjacency by testing that the END of the previous
861 * is equal to the START of the next. This is useful for optimizing some tests
864 * A limitation is that the last member of this enum must explicitly be handled
865 * (with an assert-unreachable statement) in switch statements that use
866 * variables of this type. Otherwise, the compiler warns that we have not
867 * handled that enum value.
869 typedef enum base_jd_event_code {
870 /* HW defined exceptions */
872 /** Start of HW Non-fault status codes
874 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
875 * because the job was hard-stopped
877 BASE_JD_EVENT_RANGE_HW_NONFAULT_START = 0,
879 /* non-fatal exceptions */
880 BASE_JD_EVENT_NOT_STARTED = 0x00, /**< Can't be seen by userspace, treated as 'previous job done' */
881 BASE_JD_EVENT_DONE = 0x01,
882 BASE_JD_EVENT_STOPPED = 0x03, /**< Can't be seen by userspace, becomes TERMINATED, DONE or JOB_CANCELLED */
883 BASE_JD_EVENT_TERMINATED = 0x04, /**< This is actually a fault status code - the job was hard stopped */
884 BASE_JD_EVENT_ACTIVE = 0x08, /**< Can't be seen by userspace, jobs only returned on complete/fail/cancel */
886 /** End of HW Non-fault status codes
888 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
889 * because the job was hard-stopped
891 BASE_JD_EVENT_RANGE_HW_NONFAULT_END = 0x40,
893 /** Start of HW fault and SW Error status codes */
894 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START = 0x40,
897 BASE_JD_EVENT_JOB_CONFIG_FAULT = 0x40,
898 BASE_JD_EVENT_JOB_POWER_FAULT = 0x41,
899 BASE_JD_EVENT_JOB_READ_FAULT = 0x42,
900 BASE_JD_EVENT_JOB_WRITE_FAULT = 0x43,
901 BASE_JD_EVENT_JOB_AFFINITY_FAULT = 0x44,
902 BASE_JD_EVENT_JOB_BUS_FAULT = 0x48,
903 BASE_JD_EVENT_INSTR_INVALID_PC = 0x50,
904 BASE_JD_EVENT_INSTR_INVALID_ENC = 0x51,
905 BASE_JD_EVENT_INSTR_TYPE_MISMATCH = 0x52,
906 BASE_JD_EVENT_INSTR_OPERAND_FAULT = 0x53,
907 BASE_JD_EVENT_INSTR_TLS_FAULT = 0x54,
908 BASE_JD_EVENT_INSTR_BARRIER_FAULT = 0x55,
909 BASE_JD_EVENT_INSTR_ALIGN_FAULT = 0x56,
910 BASE_JD_EVENT_DATA_INVALID_FAULT = 0x58,
911 BASE_JD_EVENT_TILE_RANGE_FAULT = 0x59,
912 BASE_JD_EVENT_STATE_FAULT = 0x5A,
913 BASE_JD_EVENT_OUT_OF_MEMORY = 0x60,
914 BASE_JD_EVENT_UNKNOWN = 0x7F,
917 BASE_JD_EVENT_DELAYED_BUS_FAULT = 0x80,
918 BASE_JD_EVENT_SHAREABILITY_FAULT = 0x88,
921 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1 = 0xC1,
922 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2 = 0xC2,
923 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3 = 0xC3,
924 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4 = 0xC4,
925 BASE_JD_EVENT_PERMISSION_FAULT = 0xC8,
926 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1 = 0xD1,
927 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2 = 0xD2,
928 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3 = 0xD3,
929 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4 = 0xD4,
930 BASE_JD_EVENT_ACCESS_FLAG = 0xD8,
932 /* SW defined exceptions */
933 BASE_JD_EVENT_MEM_GROWTH_FAILED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
934 BASE_JD_EVENT_TIMED_OUT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001,
935 BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
936 BASE_JD_EVENT_JOB_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
937 BASE_JD_EVENT_PM_EVENT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004,
939 BASE_JD_EVENT_BAG_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003,
941 /** End of HW fault and SW Error status codes */
942 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
944 /** Start of SW Success status codes */
945 BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 0x000,
947 BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000,
948 BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_BAG | 0x000,
949 BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000,
951 /** End of SW Success status codes */
952 BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
954 /** Start of Kernel-only status codes. Such codes are never returned to user-space */
955 BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | 0x000,
956 BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000,
958 /** End of Kernel-only status codes. */
959 BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF
960 } base_jd_event_code;
963 * @brief Event reporting structure
965 * This structure is used by the kernel driver to report information
966 * about GPU events. The can either be HW-specific events or low-level
967 * SW events, such as job-chain completion.
969 * The event code contains an event type field which can be extracted
970 * by ANDing with ::BASE_JD_SW_EVENT_TYPE_MASK.
972 * Based on the event type base_jd_event::data holds:
973 * @li ::BASE_JD_SW_EVENT_JOB : the offset in the ring-buffer for the completed
975 * @li ::BASE_JD_SW_EVENT_BAG : The address of the ::base_jd_bag that has
976 * been completed (ie all contained job-chains have been completed).
977 * @li ::BASE_JD_SW_EVENT_INFO : base_jd_event::data not used
979 #if BASE_LEGACY_JD_API
980 typedef struct base_jd_event {
981 base_jd_event_code event_code; /**< event code */
982 void *data; /**< event specific data */
986 typedef struct base_jd_event_v2 {
987 base_jd_event_code event_code; /**< event code */
988 base_atom_id atom_number; /**< the atom number that has completed */
989 base_jd_udata udata; /**< user data */
993 * Padding required to ensure that the @ref base_dump_cpu_gpu_counters structure fills
997 #define BASE_CPU_GPU_CACHE_LINE_PADDING (36)
1001 * @brief Structure for BASE_JD_REQ_SOFT_DUMP_CPU_GPU_COUNTERS jobs.
1003 * This structure is stored into the memory pointed to by the @c jc field of @ref base_jd_atom.
1005 * This structure must be padded to ensure that it will occupy whole cache lines. This is to avoid
1006 * cases where access to pages containing the structure is shared between cached and un-cached
1007 * memory regions, which would cause memory corruption. Here we set the structure size to be 64 bytes
1008 * which is the cache line for ARM A15 processors.
1011 typedef struct base_dump_cpu_gpu_counters {
1016 u8 padding[BASE_CPU_GPU_CACHE_LINE_PADDING];
1017 } base_dump_cpu_gpu_counters;
1021 /** @} end group base_user_api_job_dispatch */
1025 * The following typedefs should be removed when a midg types header is added.
1026 * See MIDCOM-1657 for details.
1028 typedef u32 midg_product_id;
1029 typedef u32 midg_cache_features;
1030 typedef u32 midg_tiler_features;
1031 typedef u32 midg_mem_features;
1032 typedef u32 midg_mmu_features;
1033 typedef u32 midg_js_features;
1034 typedef u32 midg_as_present;
1035 typedef u32 midg_js_present;
1037 #define MIDG_MAX_JOB_SLOTS 16
1040 #include <midg/mali_midg.h>
1044 * @page page_base_user_api_gpuprops User-side Base GPU Property Query API
1046 * The User-side Base GPU Property Query API encapsulates two
1049 * - @ref base_user_api_gpuprops_dyn "Dynamic GPU Properties"
1050 * - @ref base_plat_config_gpuprops "Base Platform Config GPU Properties"
1052 * There is a related third module outside of Base, which is owned by the MIDG
1054 * - @ref midg_gpuprops_static "Midgard Compile-time GPU Properties"
1056 * Base only deals with properties that vary between different Midgard
1057 * implementations - the Dynamic GPU properties and the Platform Config
1060 * For properties that are constant for the Midgard Architecture, refer to the
1061 * MIDG module. However, we will discuss their relevance here <b>just to
1062 * provide background information.</b>
1064 * @section sec_base_user_api_gpuprops_about About the GPU Properties in Base and MIDG modules
1066 * The compile-time properties (Platform Config, Midgard Compile-time
1067 * properties) are exposed as pre-processor macros.
1069 * Complementing the compile-time properties are the Dynamic GPU
1070 * Properties, which act as a conduit for the Midgard Configuration
1073 * In general, the dynamic properties are present to verify that the platform
1074 * has been configured correctly with the right set of Platform Config
1075 * Compile-time Properties.
1077 * As a consistant guide across the entire DDK, the choice for dynamic or
1078 * compile-time should consider the following, in order:
1079 * -# Can the code be written so that it doesn't need to know the
1080 * implementation limits at all?
1081 * -# If you need the limits, get the information from the Dynamic Property
1082 * lookup. This should be done once as you fetch the context, and then cached
1083 * as part of the context data structure, so it's cheap to access.
1084 * -# If there's a clear and arguable inefficiency in using Dynamic Properties,
1085 * then use a Compile-Time Property (Platform Config, or Midgard Compile-time
1086 * property). Examples of where this might be sensible follow:
1087 * - Part of a critical inner-loop
1088 * - Frequent re-use throughout the driver, causing significant extra load
1089 * instructions or control flow that would be worthwhile optimizing out.
1091 * We cannot provide an exhaustive set of examples, neither can we provide a
1092 * rule for every possible situation. Use common sense, and think about: what
1093 * the rest of the driver will be doing; how the compiler might represent the
1094 * value if it is a compile-time constant; whether an OEM shipping multiple
1095 * devices would benefit much more from a single DDK binary, instead of
1096 * insignificant micro-optimizations.
1098 * @section sec_base_user_api_gpuprops_dyn Dynamic GPU Properties
1100 * Dynamic GPU properties are presented in two sets:
1101 * -# the commonly used properties in @ref base_gpu_props, which have been
1102 * unpacked from GPU register bitfields.
1103 * -# The full set of raw, unprocessed properties in @ref midg_raw_gpu_props
1104 * (also a member of @ref base_gpu_props). All of these are presented in
1105 * the packed form, as presented by the GPU registers themselves.
1107 * @usecase The raw properties in @ref midg_raw_gpu_props are necessary to
1108 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
1109 * behaving differently?". In this case, all information about the
1110 * configuration is potentially useful, but it <b>does not need to be processed
1111 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1112 * Tools software on the host PC.
1114 * The properties returned extend the Midgard Configuration Discovery
1115 * registers. For example, GPU clock speed is not specified in the Midgard
1116 * Architecture, but is <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1118 * The GPU properties are obtained by a call to
1119 * _mali_base_get_gpu_props(). This simply returns a pointer to a const
1120 * base_gpu_props structure. It is constant for the life of a base
1121 * context. Multiple calls to _mali_base_get_gpu_props() to a base context
1122 * return the same pointer to a constant structure. This avoids cache pollution
1123 * of the common data.
1125 * This pointer must not be freed, because it does not point to the start of a
1126 * region allocated by the memory allocator; instead, just close the @ref
1130 * @section sec_base_user_api_gpuprops_config Platform Config Compile-time Properties
1132 * The Platform Config File sets up gpu properties that are specific to a
1133 * certain platform. Properties that are 'Implementation Defined' in the
1134 * Midgard Architecture spec are placed here.
1136 * @note Reference configurations are provided for Midgard Implementations, such as
1137 * the Mali-T600 family. The customer need not repeat this information, and can select one of
1138 * these reference configurations. For example, VA_BITS, PA_BITS and the
1139 * maximum number of samples per pixel might vary between Midgard Implementations, but
1140 * \b not for platforms using the Mali-T604. This information is placed in
1141 * the reference configuration files.
1143 * The System Integrator creates the following structure:
1145 * - platform_XYZ/plat
1146 * - platform_XYZ/plat/plat_config.h
1148 * They then edit plat_config.h, using the example plat_config.h files as a
1151 * At the very least, the customer must set @ref CONFIG_GPU_CORE_TYPE, and will
1152 * receive a helpful \#error message if they do not do this correctly. This
1153 * selects the Reference Configuration for the Midgard Implementation. The rationale
1154 * behind this decision (against asking the customer to write \#include
1155 * <gpus/mali_t600.h> in their plat_config.h) is as follows:
1156 * - This mechanism 'looks' like a regular config file (such as Linux's
1158 * - It is difficult to get wrong in a way that will produce strange build
1160 * - They need not know where the mali_t600.h, other_midg_gpu.h etc. files are stored - and
1161 * so they won't accidentally pick another file with 'mali_t600' in its name
1162 * - When the build doesn't work, the System Integrator may think the DDK is
1163 * doesn't work, and attempt to fix it themselves:
1164 * - For the @ref CONFIG_GPU_CORE_TYPE mechanism, the only way to get past the
1165 * error is to set @ref CONFIG_GPU_CORE_TYPE, and this is what the \#error tells
1167 * - For a \#include mechanism, checks must still be made elsewhere, which the
1168 * System Integrator may try working around by setting \#defines (such as
1169 * VA_BITS) themselves in their plat_config.h. In the worst case, they may
1170 * set the prevention-mechanism \#define of
1171 * "A_CORRECT_MIDGARD_CORE_WAS_CHOSEN".
1172 * - In this case, they would believe they are on the right track, because
1173 * the build progresses with their fix, but with errors elsewhere.
1175 * However, there is nothing to prevent the customer using \#include to organize
1176 * their own configurations files hierarchically.
1178 * The mechanism for the header file processing is as follows:
1181 digraph plat_config_mechanism {
1190 rank = same; ordering = out;
1192 "midg/midg_gpu_props.h";
1193 "base/midg_gpus/mali_t600.h";
1194 "base/midg_gpus/other_midg_gpu.h";
1196 { rank = same; "plat/plat_config.h"; }
1199 "midg/midg.h" [ shape=box ];
1200 gpu_chooser [ label="" style="invisible" width=0 height=0 fixedsize=true ];
1201 select_gpu [ label="Mali-T600 | Other\n(select_gpu.h)" shape=polygon,sides=4,distortion=0.25 width=3.3 height=0.99 fixedsize=true ] ;
1204 { rank = same; "plat/plat_config.h"; }
1205 { rank = same; "mali_base.h"; }
1207 "mali_base.h" -> "midg/midg.h" -> "midg/midg_gpu_props.h";
1208 "mali_base.h" -> "plat/plat_config.h" ;
1209 "mali_base.h" -> select_gpu ;
1211 "plat/plat_config.h" -> gpu_chooser [style="dotted,bold" dir=none weight=4] ;
1212 gpu_chooser -> select_gpu [style="dotted,bold"] ;
1214 select_gpu -> "base/midg_gpus/mali_t600.h" ;
1215 select_gpu -> "base/midg_gpus/other_midg_gpu.h" ;
1220 * @section sec_base_user_api_gpuprops_kernel Kernel Operation
1222 * During Base Context Create time, user-side makes a single kernel call:
1223 * - A call to fill user memory with GPU information structures
1225 * The kernel-side will fill the provided the entire processed @ref base_gpu_props
1226 * structure, because this information is required in both
1227 * user and kernel side; it does not make sense to decode it twice.
1229 * Coherency groups must be derived from the bitmasks, but this can be done
1230 * kernel side, and just once at kernel startup: Coherency groups must already
1231 * be known kernel-side, to support chains that specify a 'Only Coherent Group'
1232 * SW requirement, or 'Only Coherent Group with Tiler' SW requirement.
1234 * @section sec_base_user_api_gpuprops_cocalc Coherency Group calculation
1235 * Creation of the coherent group data is done at device-driver startup, and so
1236 * is one-time. This will most likely involve a loop with CLZ, shifting, and
1237 * bit clearing on the L2_PRESENT or L3_PRESENT masks, depending on whether the
1238 * system is L2 or L2+L3 Coherent. The number of shader cores is done by a
1239 * population count, since faulty cores may be disabled during production,
1240 * producing a non-contiguous mask.
1242 * The memory requirements for this algoirthm can be determined either by a u64
1243 * population count on the L2/L3_PRESENT masks (a LUT helper already is
1244 * requried for the above), or simple assumption that there can be no more than
1245 * 16 coherent groups, since core groups are typically 4 cores.
1249 * @addtogroup base_user_api_gpuprops User-side Base GPU Property Query APIs
1254 * @addtogroup base_user_api_gpuprops_dyn Dynamic HW Properties
1258 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
1260 #define BASE_MAX_COHERENT_GROUPS 16
1262 struct mali_base_gpu_core_props {
1264 * Product specific value.
1266 midg_product_id product_id;
1269 * Status of the GPU release.
1270 * No defined values, but starts at 0 and increases by one for each release
1271 * status (alpha, beta, EAC, etc.).
1272 * 4 bit values (0-15).
1277 * Minor release number of the GPU. "P" part of an "RnPn" release number.
1278 * 8 bit values (0-255).
1283 * Major release number of the GPU. "R" part of an "RnPn" release number.
1284 * 4 bit values (0-15).
1291 * @usecase GPU clock speed is not specified in the Midgard Architecture, but is
1292 * <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1297 * @usecase GPU clock max/min speed is required for computing best/worst case
1298 * in tasks as job scheduling ant irq_throttling. (It is not specified in the
1299 * Midgard Architecture).
1301 u32 gpu_freq_khz_max;
1302 u32 gpu_freq_khz_min;
1305 * Size of the shader program counter, in bits.
1307 u32 log2_program_counter_size;
1310 * TEXTURE_FEATURES_x registers, as exposed by the GPU. This is a
1311 * bitpattern where a set bit indicates that the format is supported.
1313 * Before using a texture format, it is recommended that the corresponding
1316 u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
1319 * Theoretical maximum memory available to the GPU. It is unlikely that a
1320 * client will be able to allocate all of this memory for their own
1321 * purposes, but this at least provides an upper bound on the memory
1322 * available to the GPU.
1324 * This is required for OpenCL's clGetDeviceInfo() call when
1325 * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
1326 * client will not be expecting to allocate anywhere near this value.
1328 u64 gpu_available_memory_size;
1333 * More information is possible - but associativity and bus width are not
1334 * required by upper-level apis.
1336 struct mali_base_gpu_l2_cache_props {
1339 u8 num_l2_slices; /* Number of L2C slices. 1 or higher */
1343 struct mali_base_gpu_l3_cache_props {
1349 struct mali_base_gpu_tiler_props {
1350 u32 bin_size_bytes; /* Max is 4*2^15 */
1351 u32 max_active_levels; /* Max is 2^15 */
1355 * GPU threading system details.
1357 struct mali_base_gpu_thread_props {
1358 u32 max_threads; /* Max. number of threads per core */
1359 u32 max_workgroup_size; /* Max. number of threads per workgroup */
1360 u32 max_barrier_size; /* Max. number of threads that can synchronize on a simple barrier */
1361 u16 max_registers; /* Total size [1..65535] of the register file available per core. */
1362 u8 max_task_queue; /* Max. tasks [1..255] which may be sent to a core before it becomes blocked. */
1363 u8 max_thread_group_split; /* Max. allowed value [1..15] of the Thread Group Split field. */
1364 u8 impl_tech; /* 0 = Not specified, 1 = Silicon, 2 = FPGA, 3 = SW Model/Emulation */
1369 * @brief descriptor for a coherent group
1371 * \c core_mask exposes all cores in that coherent group, and \c num_cores
1372 * provides a cached population-count for that mask.
1374 * @note Whilst all cores are exposed in the mask, not all may be available to
1375 * the application, depending on the Kernel Job Scheduler policy. Therefore,
1376 * the application should not further restrict the core mask itself, as it may
1377 * result in an empty core mask. However, it can guarentee that there will be
1378 * at least one core available for each core group exposed .
1380 * @usecase Chains marked at certain user-side priorities (e.g. the Long-running
1381 * (batch) priority ) can be prevented from running on entire core groups by the
1382 * Kernel Chain Scheduler policy.
1384 * @note if u64s must be 8-byte aligned, then this structure has 32-bits of wastage.
1386 struct mali_base_gpu_coherent_group {
1387 u64 core_mask; /**< Core restriction mask required for the group */
1388 u16 num_cores; /**< Number of cores in the group */
1393 * @brief Coherency group information
1395 * Note that the sizes of the members could be reduced. However, the \c group
1396 * member might be 8-byte aligned to ensure the u64 core_mask is 8-byte
1397 * aligned, thus leading to wastage if the other members sizes were reduced.
1399 * The groups are sorted by core mask. The core masks are non-repeating and do
1402 struct mali_base_gpu_coherent_group_info {
1406 * Number of core groups (coherent or not) in the GPU. Equivalent to the number of L2 Caches.
1408 * The GPU Counter dumping writes 2048 bytes per core group, regardless of
1409 * whether the core groups are coherent or not. Hence this member is needed
1410 * to calculate how much memory is required for dumping.
1412 * @note Do not use it to work out how many valid elements are in the
1413 * group[] member. Use num_groups instead.
1415 u32 num_core_groups;
1418 * Coherency features of the memory, accessed by @ref midg_mem_features
1421 midg_mem_features coherency;
1426 * Descriptors of coherent groups
1428 struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
1432 * A complete description of the GPU's Hardware Configuration Discovery
1435 * The information is presented inefficiently for access. For frequent access,
1436 * the values should be better expressed in an unpacked form in the
1437 * base_gpu_props structure.
1439 * @usecase The raw properties in @ref midg_raw_gpu_props are necessary to
1440 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
1441 * behaving differently?". In this case, all information about the
1442 * configuration is potentially useful, but it <b>does not need to be processed
1443 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1444 * Tools software on the host PC.
1447 struct midg_raw_gpu_props {
1453 midg_cache_features l2_features;
1454 midg_cache_features l3_features;
1455 midg_mem_features mem_features;
1456 midg_mmu_features mmu_features;
1458 midg_as_present as_present;
1461 midg_js_features js_features[MIDG_MAX_JOB_SLOTS];
1462 midg_tiler_features tiler_features;
1463 u32 texture_features[3];
1467 u32 thread_max_threads;
1468 u32 thread_max_workgroup_size;
1469 u32 thread_max_barrier_size;
1470 u32 thread_features;
1476 * Return structure for _mali_base_get_gpu_props().
1478 * NOTE: the raw_props member in this datastructure contains the register
1479 * values from which the value of the other members are derived. The derived
1480 * members exist to allow for efficient access and/or shielding the details
1481 * of the layout of the registers.
1484 typedef struct mali_base_gpu_props {
1485 struct mali_base_gpu_core_props core_props;
1486 struct mali_base_gpu_l2_cache_props l2_props;
1487 struct mali_base_gpu_l3_cache_props l3_props;
1488 struct mali_base_gpu_tiler_props tiler_props;
1489 struct mali_base_gpu_thread_props thread_props;
1491 /** This member is large, likely to be 128 bytes */
1492 struct midg_raw_gpu_props raw_props;
1494 /** This must be last member of the structure */
1495 struct mali_base_gpu_coherent_group_info coherency_info;
1498 /** @} end group base_user_api_gpuprops_dyn */
1500 /** @} end group base_user_api_gpuprops */
1503 * @addtogroup base_user_api_core User-side Base core APIs
1508 * \enum base_context_create_flags
1510 * Flags to pass to ::base_context_init.
1511 * Flags can be ORed together to enable multiple things.
1513 * These share the same space as @ref basep_context_private_flags, and so must
1514 * not collide with them.
1516 enum base_context_create_flags {
1518 BASE_CONTEXT_CREATE_FLAG_NONE = 0,
1520 /** Base context is embedded in a cctx object (flag used for CINSTR software counter macros) */
1521 BASE_CONTEXT_CCTX_EMBEDDED = (1u << 0),
1523 /** Base context is a 'System Monitor' context for Hardware counters.
1525 * One important side effect of this is that job submission is disabled. */
1526 BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED = (1u << 1),
1528 /** Base context flag indicating a 'hint' that this context uses Compute
1531 * Specifially, this means that it only sends atoms that <b>do not</b>
1532 * contain the following @ref base_jd_core_req :
1536 * Violation of these requirements will cause the Job-Chains to be rejected.
1538 * In addition, it is inadvisable for the atom's Job-Chains to contain Jobs
1539 * of the following @ref midg_job_type (whilst it may work now, it may not
1541 * - @ref MIDG_JOB_VERTEX
1542 * - @ref MIDG_JOB_GEOMETRY
1544 * @note An alternative to using this is to specify the BASE_JD_REQ_ONLY_COMPUTE
1545 * requirement in atoms.
1547 BASE_CONTEXT_HINT_ONLY_COMPUTE = (1u << 2)
1551 * Bitpattern describing the ::base_context_create_flags that can be passed to base_context_init()
1553 #define BASE_CONTEXT_CREATE_ALLOWED_FLAGS \
1554 (((u32)BASE_CONTEXT_CCTX_EMBEDDED) | \
1555 ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED) | \
1556 ((u32)BASE_CONTEXT_HINT_ONLY_COMPUTE))
1559 * Bitpattern describing the ::base_context_create_flags that can be passed to the kernel
1561 #define BASE_CONTEXT_CREATE_KERNEL_FLAGS \
1562 (((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED) | \
1563 ((u32)BASE_CONTEXT_HINT_ONLY_COMPUTE))
1566 * Private flags used on the base context
1568 * These start at bit 31, and run down to zero.
1570 * They share the same space as @ref base_context_create_flags, and so must
1571 * not collide with them.
1573 enum basep_context_private_flags {
1574 /** Private flag tracking whether job descriptor dumping is disabled */
1575 BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED = (1 << 31)
1578 /** @} end group base_user_api_core */
1580 /** @} end group base_user_api */
1583 * @addtogroup base_plat_config_gpuprops Base Platform Config GPU Properties
1586 * C Pre-processor macros are exposed here to do with Platform
1590 * - GPU Properties that are constant on a particular Midgard Family
1591 * Implementation e.g. Maximum samples per pixel on Mali-T600.
1592 * - General platform config for the GPU, such as the GPU major and minor
1596 /** @} end group base_plat_config_gpuprops */
1599 * @addtogroup base_api Base APIs
1603 * @addtogroup basecpuprops Base CPU Properties
1608 * @brief CPU Property Flag for base_cpu_props::cpu_flags, indicating a
1609 * Little Endian System. If not set in base_cpu_props::cpu_flags, then the
1610 * system is Big Endian.
1612 * The compile-time equivalent is @ref OSU_CONFIG_CPU_LITTLE_ENDIAN.
1614 #define BASE_CPU_PROPERTY_FLAG_LITTLE_ENDIAN F_BIT_0
1618 * @brief Platform dynamic CPU ID properties structure
1620 typedef struct base_cpu_id_props
1633 * ASCII code of implementer trademark
1653 Validity of CPU id where 0-invalid and
1654 1-valid only if ALL the cpu_id props are valid
1662 /** @brief Platform Dynamic CPU properties structure */
1663 typedef struct base_cpu_props {
1664 u32 nr_cores; /**< Number of CPU cores */
1667 * CPU page size as a Logarithm to Base 2. The compile-time
1668 * equivalent is @ref OSU_CONFIG_CPU_PAGE_SIZE_LOG2
1670 u32 cpu_page_size_log2;
1673 * CPU L1 Data cache line size as a Logarithm to Base 2. The compile-time
1674 * equivalent is @ref OSU_CONFIG_CPU_L1_DCACHE_LINE_SIZE_LOG2.
1676 u32 cpu_l1_dcache_line_size_log2;
1679 * CPU L1 Data cache size, in bytes. The compile-time equivalient is
1680 * @ref OSU_CONFIG_CPU_L1_DCACHE_SIZE.
1682 * This CPU Property is mainly provided to implement OpenCL's
1683 * clGetDeviceInfo(), which allows the CL_DEVICE_GLOBAL_MEM_CACHE_SIZE
1684 * hint to be queried.
1686 u32 cpu_l1_dcache_size;
1689 * CPU Property Flags bitpattern.
1691 * This is a combination of bits as specified by the macros prefixed with
1692 * 'BASE_CPU_PROPERTY_FLAG_'.
1697 * Maximum clock speed in MHz.
1698 * @usecase 'Maximum' CPU Clock Speed information is required by OpenCL's
1699 * clGetDeviceInfo() function for the CL_DEVICE_MAX_CLOCK_FREQUENCY hint.
1701 u32 max_cpu_clock_speed_mhz;
1704 * @brief Total memory, in bytes.
1706 * This is the theoretical maximum memory available to the CPU. It is
1707 * unlikely that a client will be able to allocate all of this memory for
1708 * their own purposes, but this at least provides an upper bound on the
1709 * memory available to the CPU.
1711 * This is required for OpenCL's clGetDeviceInfo() call when
1712 * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL CPU devices.
1714 u64 available_memory_size;
1717 * CPU ID detailed info
1719 base_cpu_id_props cpu_id;
1723 /** @} end group basecpuprops */
1726 * @brief The payload for a replay job. This must be in GPU memory.
1728 typedef struct base_jd_replay_payload {
1730 * Pointer to the first entry in the base_jd_replay_jc list. These
1731 * will be replayed in @b reverse order (so that extra ones can be added
1732 * to the head in future soft jobs without affecting this soft job)
1734 mali_addr64 tiler_jc_list;
1737 * Pointer to the fragment job chain.
1739 mali_addr64 fragment_jc;
1742 * Pointer to the tiler heap free FBD field to be modified.
1744 mali_addr64 tiler_heap_free;
1747 * Hierarchy mask for the replayed fragment jobs. May be zero.
1749 u16 fragment_hierarchy_mask;
1752 * Hierarchy mask for the replayed tiler jobs. May be zero.
1754 u16 tiler_hierarchy_mask;
1757 * Default weight to be used for hierarchy levels not in the original
1760 u32 hierarchy_default_weight;
1763 * Core requirements for the tiler job chain
1765 base_jd_core_req tiler_core_req;
1768 * Core requirements for the fragment job chain
1770 base_jd_core_req fragment_core_req;
1773 } base_jd_replay_payload;
1776 * @brief An entry in the linked list of job chains to be replayed. This must
1779 typedef struct base_jd_replay_jc {
1781 * Pointer to next entry in the list. A setting of NULL indicates the
1787 * Pointer to the job chain.
1791 } base_jd_replay_jc;
1793 /* Maximum number of jobs allowed in a fragment chain in the payload of a
1795 #define BASE_JD_REPLAY_F_CHAIN_JOB_LIMIT 256
1797 /** @} end group base_api */
1799 typedef struct base_profiling_controls {
1800 u32 profiling_controls[FBDUMP_CONTROL_MAX];
1801 } base_profiling_controls;
1803 #endif /* _BASE_KERNEL_H_ */