3 * (C) COPYRIGHT ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
22 * Base structures shared with the kernel.
25 #ifndef _BASE_KERNEL_H_
26 #define _BASE_KERNEL_H_
32 /* Support UK6 IOCTLS */
33 #define BASE_LEGACY_UK6_SUPPORT 1
35 /* Support UK7 IOCTLS */
36 /* NB: To support UK6 we also need to support UK7 */
37 #define BASE_LEGACY_UK7_SUPPORT 1
39 typedef mali_addr64 base_mem_handle;
41 #include "mali_base_mem_priv.h"
42 #include "mali_kbase_profiling_gator_api.h"
45 * Dependency stuff, keep it private for now. May want to expose it if
46 * we decide to make the number of semaphores a configurable
49 #define BASE_JD_ATOM_COUNT 256
51 #define BASEP_JD_SEM_PER_WORD_LOG2 5
52 #define BASEP_JD_SEM_PER_WORD (1 << BASEP_JD_SEM_PER_WORD_LOG2)
53 #define BASEP_JD_SEM_WORD_NR(x) ((x) >> BASEP_JD_SEM_PER_WORD_LOG2)
54 #define BASEP_JD_SEM_MASK_IN_WORD(x) (1 << ((x) & (BASEP_JD_SEM_PER_WORD - 1)))
55 #define BASEP_JD_SEM_ARRAY_SIZE BASEP_JD_SEM_WORD_NR(BASE_JD_ATOM_COUNT)
57 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
59 #define BASE_MAX_COHERENT_GROUPS 16
61 #if defined CDBG_ASSERT
62 #define LOCAL_ASSERT CDBG_ASSERT
63 #elif defined KBASE_DEBUG_ASSERT
64 #define LOCAL_ASSERT KBASE_DEBUG_ASSERT
66 #error assert macro not defined!
70 #define LOCAL_PAGE_LSB ~PAGE_MASK
72 #include <osu/mali_osu.h>
74 #if defined OSU_CONFIG_CPU_PAGE_SIZE_LOG2
75 #define LOCAL_PAGE_LSB ((1ul << OSU_CONFIG_CPU_PAGE_SIZE_LOG2) - 1)
77 #error Failed to find page size
81 /** 32/64-bit neutral way to represent pointers */
82 typedef union kbase_pointer {
83 void __user *value; /**< client should store their pointers here */
84 u32 compat_value; /**< 64-bit kernels should fetch value here when handling 32-bit clients */
85 u64 sizer; /**< Force 64-bit storage for all clients regardless */
89 * @addtogroup base_user_api User-side Base APIs
94 * @addtogroup base_user_api_memory User-side Base Memory APIs
99 * @brief Memory allocation, access/hint flags
101 * A combination of MEM_PROT/MEM_HINT flags must be passed to each allocator
102 * in order to determine the best cache policy. Some combinations are
103 * of course invalid (eg @c MEM_PROT_CPU_WR | @c MEM_HINT_CPU_RD),
104 * which defines a @a write-only region on the CPU side, which is
105 * heavily read by the CPU...
106 * Other flags are only meaningful to a particular allocator.
107 * More flags can be added to this list, as long as they don't clash
108 * (see ::BASE_MEM_FLAGS_NR_TOTAL_BITS for the number of the first free bit).
110 typedef u32 base_mem_alloc_flags;
113 * @brief Memory allocation, access/hint flags
115 * See ::base_mem_alloc_flags.
120 BASE_MEM_PROT_CPU_RD = (1U << 0), /**< Read access CPU side */
121 BASE_MEM_PROT_CPU_WR = (1U << 1), /**< Write access CPU side */
122 BASE_MEM_PROT_GPU_RD = (1U << 2), /**< Read access GPU side */
123 BASE_MEM_PROT_GPU_WR = (1U << 3), /**< Write access GPU side */
124 BASE_MEM_PROT_GPU_EX = (1U << 4), /**< Execute allowed on the GPU
127 /* Note that the HINT flags are obsolete now. If you want the memory
128 * to be cached on the CPU please use the BASE_MEM_CACHED_CPU flag
130 BASE_MEM_HINT_CPU_RD = (1U << 5), /**< Heavily read CPU side
132 BASE_MEM_HINT_CPU_WR = (1U << 6), /**< Heavily written CPU side
134 BASE_MEM_HINT_GPU_RD = (1U << 7), /**< Heavily read GPU side
136 BASE_MEM_HINT_GPU_WR = (1U << 8), /**< Heavily written GPU side
139 BASE_MEM_GROW_ON_GPF = (1U << 9), /**< Grow backing store on GPU
142 BASE_MEM_COHERENT_SYSTEM = (1U << 10), /**< Page coherence Outer
144 BASE_MEM_COHERENT_LOCAL = (1U << 11), /**< Page coherence Inner
146 BASE_MEM_CACHED_CPU = (1U << 12), /**< Should be cached on the
150 BASE_MEM_SAME_VA = (1U << 13), /**< Must have same VA on both the GPU
153 BASE_MEM_NEED_MMAP = (1U << 14) /**< Must call mmap to aquire a GPU
154 address for the alloc */
158 * @brief Number of bits used as flags for base memory management
160 * Must be kept in sync with the ::base_mem_alloc_flags flags
162 #define BASE_MEM_FLAGS_NR_INPUT_BITS 14
163 #define BASE_MEM_FLAGS_NR_OUTPUT_BITS 1
164 #define BASE_MEM_FLAGS_NR_TOTAL_BITS ((BASE_MEM_FLAGS_NR_INPUT_BITS) + (BASE_MEM_FLAGS_NR_OUTPUT_BITS))
165 #define BASE_MEM_FLAGS_NR_BITS 15
167 #if BASE_MEM_FLAGS_NR_TOTAL_BITS > BASE_MEM_FLAGS_NR_BITS
168 #error "Too many flag bits, will require change in cmem"
172 * @brief Memory types supported by @a base_mem_import
174 * Each type defines what the supported handle type is.
176 * If any new type is added here ARM must be contacted
177 * to allocate a numeric value for it.
178 * Do not just add a new type without synchronizing with ARM
179 * as future releases from ARM might include other new types
180 * which could clash with your custom types.
182 typedef enum base_mem_import_type {
183 BASE_MEM_IMPORT_TYPE_INVALID = 0,
184 /** UMP import. Handle type is ump_secure_id. */
185 BASE_MEM_IMPORT_TYPE_UMP = 1,
186 /** UMM import. Handle type is a file descriptor (int) */
187 BASE_MEM_IMPORT_TYPE_UMM = 2
188 } base_mem_import_type;
190 /* legacy API wrappers */
191 #define base_tmem_import_type base_mem_import_type
192 #define BASE_TMEM_IMPORT_TYPE_INVALID BASE_MEM_IMPORT_TYPE_INVALID
193 #define BASE_TMEM_IMPORT_TYPE_UMP BASE_MEM_IMPORT_TYPE_UMP
194 #define BASE_TMEM_IMPORT_TYPE_UMM BASE_MEM_IMPORT_TYPE_UMM
197 * @brief Invalid memory handle type.
198 * Return value from functions returning @a base_mem_handle on error.
200 #define BASE_MEM_INVALID_HANDLE (0ull << 12)
201 #define BASE_MEM_MMU_DUMP_HANDLE (1ull << 12)
202 #define BASE_MEM_TRACE_BUFFER_HANDLE (2ull << 12)
203 #define BASE_MEM_MAP_TRACKING_HANDLE (3ull << 12)
204 #define BASE_MEM_WRITE_ALLOC_PAGES_HANDLE (4ull << 12)
205 /* reserved handles ..-64<<PAGE_SHIFT> for future special handles */
206 #define BASE_MEM_COOKIE_BASE (64ul << 12)
207 #define BASE_MEM_FIRST_FREE_ADDRESS ((BITS_PER_LONG << 12) + \
208 BASE_MEM_COOKIE_BASE)
210 /* Bit mask of cookies used for for memory allocation setup */
211 #define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */
215 * @brief Result codes of changing the size of the backing store allocated to a tmem region
217 typedef enum base_backing_threshold_status {
218 BASE_BACKING_THRESHOLD_OK = 0, /**< Resize successful */
219 BASE_BACKING_THRESHOLD_ERROR_NOT_GROWABLE = -1, /**< Not a growable tmem object */
220 BASE_BACKING_THRESHOLD_ERROR_OOM = -2, /**< Increase failed due to an out-of-memory condition */
221 BASE_BACKING_THRESHOLD_ERROR_MAPPED = -3, /**< Resize attempted on buffer while it was mapped, which is not permitted */
222 BASE_BACKING_THRESHOLD_ERROR_INVALID_ARGUMENTS = -4 /**< Invalid arguments (not tmem, illegal size request, etc.) */
223 } base_backing_threshold_status;
226 * @addtogroup base_user_api_memory_defered User-side Base Defered Memory Coherency APIs
231 * @brief a basic memory operation (sync-set).
233 * The content of this structure is private, and should only be used
236 typedef struct base_syncset {
237 struct basep_syncset basep_sset;
240 /** @} end group base_user_api_memory_defered */
243 * Handle to represent imported memory object.
244 * Simple opague handle to imported memory, can't be used
245 * with anything but base_external_resource_init to bind to an atom.
247 typedef struct base_import_handle {
251 } base_import_handle;
253 /** @} end group base_user_api_memory */
256 * @addtogroup base_user_api_job_dispatch User-side Base Job Dispatcher APIs
260 typedef int platform_fence_type;
261 #define INVALID_PLATFORM_FENCE ((platform_fence_type)-1)
264 * Base stream handle.
266 * References an underlying base stream object.
268 typedef struct base_stream {
277 * References an underlying base fence object.
279 typedef struct base_fence {
287 * @brief Per-job data
289 * This structure is used to store per-job data, and is completly unused
290 * by the Base driver. It can be used to store things such as callback
291 * function pointer, data to handle job completion. It is guaranteed to be
292 * untouched by the Base driver.
294 typedef struct base_jd_udata {
295 u64 blob[2]; /**< per-job data array */
299 * @brief Memory aliasing info
301 * Describes a memory handle to be aliased.
302 * A subset of the handle can be chosen for aliasing, given an offset and a
304 * A special handle BASE_MEM_WRITE_ALLOC_PAGES_HANDLE is used to represent a
305 * region where a special page is mapped with a write-alloc cache setup,
306 * typically used when the write result of the GPU isn't needed, but the GPU
309 * Offset and length are specified in pages.
310 * Offset must be within the size of the handle.
311 * Offset+length must not overrun the size of the handle.
313 * @handle Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
314 * @offset Offset within the handle to start aliasing from, in pages.
315 * Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
316 * @length Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
317 * specifies the number of times the special page is needed.
319 struct base_mem_aliasing_info {
320 base_mem_handle handle;
326 * @brief Job dependency type.
328 * A flags field will be inserted into the atom structure to specify whether a dependency is a data or
329 * ordering dependency (by putting it before/after 'core_req' in the structure it should be possible to add without
330 * changing the structure size).
331 * When the flag is set for a particular dependency to signal that it is an ordering only dependency then
332 * errors will not be propagated.
334 typedef u8 base_jd_dep_type;
337 #define BASE_JD_DEP_TYPE_INVALID (0) /**< Invalid dependency */
338 #define BASE_JD_DEP_TYPE_DATA (1U << 0) /**< Data dependency */
339 #define BASE_JD_DEP_TYPE_ORDER (1U << 1) /**< Order dependency */
342 * @brief Job chain hardware requirements.
344 * A job chain must specify what GPU features it needs to allow the
345 * driver to schedule the job correctly. By not specifying the
346 * correct settings can/will cause an early job termination. Multiple
347 * values can be ORed together to specify multiple requirements.
348 * Special case is ::BASE_JD_REQ_DEP, which is used to express complex
349 * dependencies, and that doesn't execute anything on the hardware.
351 typedef u16 base_jd_core_req;
353 /* Requirements that come from the HW */
354 #define BASE_JD_REQ_DEP 0 /**< No requirement, dependency only */
355 #define BASE_JD_REQ_FS (1U << 0) /**< Requires fragment shaders */
357 * Requires compute shaders
358 * This covers any of the following Midgard Job types:
359 * - Vertex Shader Job
360 * - Geometry Shader Job
361 * - An actual Compute Shader Job
363 * Compare this with @ref BASE_JD_REQ_ONLY_COMPUTE, which specifies that the
364 * job is specifically just the "Compute Shader" job type, and not the "Vertex
365 * Shader" nor the "Geometry Shader" job type.
367 #define BASE_JD_REQ_CS (1U << 1)
368 #define BASE_JD_REQ_T (1U << 2) /**< Requires tiling */
369 #define BASE_JD_REQ_CF (1U << 3) /**< Requires cache flushes */
370 #define BASE_JD_REQ_V (1U << 4) /**< Requires value writeback */
372 /* SW-only requirements - the HW does not expose these as part of the job slot capabilities */
374 /* Requires fragment job with AFBC encoding */
375 #define BASE_JD_REQ_FS_AFBC (1U << 13)
378 * SW Only requirement: the job chain requires a coherent core group. We don't
379 * mind which coherent core group is used.
381 #define BASE_JD_REQ_COHERENT_GROUP (1U << 6)
384 * SW Only requirement: The performance counters should be enabled only when
385 * they are needed, to reduce power consumption.
388 #define BASE_JD_REQ_PERMON (1U << 7)
391 * SW Only requirement: External resources are referenced by this atom.
392 * When external resources are referenced no syncsets can be bundled with the atom
393 * but should instead be part of a NULL jobs inserted into the dependency tree.
394 * The first pre_dep object must be configured for the external resouces to use,
395 * the second pre_dep object can be used to create other dependencies.
397 #define BASE_JD_REQ_EXTERNAL_RESOURCES (1U << 8)
400 * SW Only requirement: Software defined job. Jobs with this bit set will not be submitted
401 * to the hardware but will cause some action to happen within the driver
403 #define BASE_JD_REQ_SOFT_JOB (1U << 9)
405 #define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1)
406 #define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2)
407 #define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3)
410 * SW Only requirement : Replay job.
412 * If the preceeding job fails, the replay job will cause the jobs specified in
413 * the list of base_jd_replay_payload pointed to by the jc pointer to be
416 * A replay job will only cause jobs to be replayed up to BASEP_JD_REPLAY_LIMIT
417 * times. If a job fails more than BASEP_JD_REPLAY_LIMIT times then the replay
418 * job is failed, as well as any following dependencies.
420 * The replayed jobs will require a number of atom IDs. If there are not enough
421 * free atom IDs then the replay job will fail.
423 * If the preceeding job does not fail, then the replay job is returned as
426 * The replayed jobs will never be returned to userspace. The preceeding failed
427 * job will be returned to userspace as failed; the status of this job should
428 * be ignored. Completion should be determined by the status of the replay soft
431 * In order for the jobs to be replayed, the job headers will have to be
432 * modified. The Status field will be reset to NOT_STARTED. If the Job Type
433 * field indicates a Vertex Shader Job then it will be changed to Null Job.
435 * The replayed jobs have the following assumptions :
437 * - No external resources. Any required external resources will be held by the
439 * - Pre-dependencies are created based on job order.
440 * - Atom numbers are automatically assigned.
441 * - device_nr is set to 0. This is not relevant as
442 * BASE_JD_REQ_SPECIFIC_COHERENT_GROUP should not be set.
443 * - Priority is inherited from the replay job.
445 #define BASE_JD_REQ_SOFT_REPLAY (BASE_JD_REQ_SOFT_JOB | 0x4)
448 * HW Requirement: Requires Compute shaders (but not Vertex or Geometry Shaders)
450 * This indicates that the Job Chain contains Midgard Jobs of the 'Compute Shaders' type.
452 * In contrast to @ref BASE_JD_REQ_CS, this does \b not indicate that the Job
453 * Chain contains 'Geometry Shader' or 'Vertex Shader' jobs.
455 * @note This is a more flexible variant of the @ref BASE_CONTEXT_HINT_ONLY_COMPUTE flag,
456 * allowing specific jobs to be marked as 'Only Compute' instead of the entire context
458 #define BASE_JD_REQ_ONLY_COMPUTE (1U << 10)
461 * HW Requirement: Use the base_jd_atom::device_nr field to specify a
462 * particular core group
464 * If both BASE_JD_REQ_COHERENT_GROUP and this flag are set, this flag takes priority
466 * This is only guaranteed to work for BASE_JD_REQ_ONLY_COMPUTE atoms.
468 * If the core availability policy is keeping the required core group turned off, then
469 * the job will fail with a BASE_JD_EVENT_PM_EVENT error code.
471 #define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP (1U << 11)
474 * SW Flag: If this bit is set then the successful completion of this atom
475 * will not cause an event to be sent to userspace
477 #define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE (1U << 12)
480 * SW Flag: If this bit is set then completion of this atom will not cause an
481 * event to be sent to userspace, whether successful or not.
483 #define BASEP_JD_REQ_EVENT_NEVER (1U << 14)
486 * These requirement bits are currently unused in base_jd_core_req (currently a u16)
489 #define BASEP_JD_REQ_RESERVED_BIT5 (1U << 5)
490 #define BASEP_JD_REQ_RESERVED_BIT15 (1U << 15)
493 * Mask of all the currently unused requirement bits in base_jd_core_req.
496 #define BASEP_JD_REQ_RESERVED (BASEP_JD_REQ_RESERVED_BIT5 | \
497 BASEP_JD_REQ_RESERVED_BIT15)
500 * Mask of all bits in base_jd_core_req that control the type of the atom.
502 * This allows dependency only atoms to have flags set
504 #define BASEP_JD_REQ_ATOM_TYPE (~(BASEP_JD_REQ_RESERVED | BASE_JD_REQ_EVENT_ONLY_ON_FAILURE |\
505 BASE_JD_REQ_EXTERNAL_RESOURCES | BASEP_JD_REQ_EVENT_NEVER))
508 * @brief States to model state machine processed by kbasep_js_job_check_ref_cores(), which
509 * handles retaining cores for power management and affinity management.
511 * The state @ref KBASE_ATOM_COREREF_STATE_RECHECK_AFFINITY prevents an attack
512 * where lots of atoms could be submitted before powerup, and each has an
513 * affinity chosen that causes other atoms to have an affinity
514 * violation. Whilst the affinity was not causing violations at the time it
515 * was chosen, it could cause violations thereafter. For example, 1000 jobs
516 * could have had their affinity chosen during the powerup time, so any of
517 * those 1000 jobs could cause an affinity violation later on.
519 * The attack would otherwise occur because other atoms/contexts have to wait for:
520 * -# the currently running atoms (which are causing the violation) to
522 * -# and, the atoms that had their affinity chosen during powerup to
523 * finish. These are run preferrentially because they don't cause a
524 * violation, but instead continue to cause the violation in others.
525 * -# or, the attacker is scheduled out (which might not happen for just 2
528 * By re-choosing the affinity (which is designed to avoid violations at the
529 * time it's chosen), we break condition (2) of the wait, which minimizes the
530 * problem to just waiting for current jobs to finish (which can be bounded if
531 * the Job Scheduling Policy has a timer).
533 enum kbase_atom_coreref_state {
534 /** Starting state: No affinity chosen, and cores must be requested. kbase_jd_atom::affinity==0 */
535 KBASE_ATOM_COREREF_STATE_NO_CORES_REQUESTED,
536 /** Cores requested, but waiting for them to be powered. Requested cores given by kbase_jd_atom::affinity */
537 KBASE_ATOM_COREREF_STATE_WAITING_FOR_REQUESTED_CORES,
538 /** Cores given by kbase_jd_atom::affinity are powered, but affinity might be out-of-date, so must recheck */
539 KBASE_ATOM_COREREF_STATE_RECHECK_AFFINITY,
540 /** Cores given by kbase_jd_atom::affinity are powered, and affinity is up-to-date, but must check for violations */
541 KBASE_ATOM_COREREF_STATE_CHECK_AFFINITY_VIOLATIONS,
542 /** Cores are powered, kbase_jd_atom::affinity up-to-date, no affinity violations: atom can be submitted to HW */
543 KBASE_ATOM_COREREF_STATE_READY
546 enum kbase_jd_atom_state {
547 /** Atom is not used */
548 KBASE_JD_ATOM_STATE_UNUSED,
549 /** Atom is queued in JD */
550 KBASE_JD_ATOM_STATE_QUEUED,
551 /** Atom has been given to JS (is runnable/running) */
552 KBASE_JD_ATOM_STATE_IN_JS,
553 /** Atom has been completed, but not yet handed back to userspace */
554 KBASE_JD_ATOM_STATE_COMPLETED
557 typedef u8 base_atom_id; /**< Type big enough to store an atom number in */
559 struct base_dependency {
560 base_atom_id atom_id; /**< An atom number */
561 base_jd_dep_type dependency_type; /**< Dependency type */
564 typedef struct base_jd_atom_v2 {
565 mali_addr64 jc; /**< job-chain GPU address */
566 struct base_jd_udata udata; /**< user data */
567 kbase_pointer extres_list; /**< list of external resources */
568 u16 nr_extres; /**< nr of external resources */
569 base_jd_core_req core_req; /**< core requirements */
570 const struct base_dependency pre_dep[2]; /**< pre-dependencies, one need to use SETTER function to assign this field,
571 this is done in order to reduce possibility of improper assigment of a dependency field */
572 base_atom_id atom_number; /**< unique number to identify the atom */
573 s8 prio; /**< priority - smaller is higher priority */
574 u8 device_nr; /**< coregroup when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP specified */
578 #ifdef BASE_LEGACY_UK6_SUPPORT
579 struct base_jd_atom_v2_uk6 {
580 mali_addr64 jc; /**< job-chain GPU address */
581 struct base_jd_udata udata; /**< user data */
582 kbase_pointer extres_list; /**< list of external resources */
583 u16 nr_extres; /**< nr of external resources */
584 base_jd_core_req core_req; /**< core requirements */
585 base_atom_id pre_dep[2]; /**< pre-dependencies */
586 base_atom_id atom_number; /**< unique number to identify the atom */
587 s8 prio; /**< priority - smaller is higher priority */
588 u8 device_nr; /**< coregroup when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP specified */
593 typedef enum base_external_resource_access {
594 BASE_EXT_RES_ACCESS_SHARED,
595 BASE_EXT_RES_ACCESS_EXCLUSIVE
596 } base_external_resource_access;
598 typedef struct base_external_resource {
600 } base_external_resource;
603 * @brief Setter for a dependency structure
605 * @param[in] dep The kbase jd atom dependency to be initialized.
606 * @param id The atom_id to be assigned.
607 * @param dep_type The dep_type to be assigned.
610 static INLINE void base_jd_atom_dep_set(const struct base_dependency* const_dep, base_atom_id id, base_jd_dep_type dep_type)
612 struct base_dependency* dep;
614 LOCAL_ASSERT(const_dep != NULL);
615 /* make sure we don't set not allowed combinations of atom_id/dependency_type */
616 LOCAL_ASSERT( ( id == 0 && dep_type == BASE_JD_DEP_TYPE_INVALID) ||
617 (id > 0 && dep_type != BASE_JD_DEP_TYPE_INVALID) );
619 dep = REINTERPRET_CAST(struct base_dependency*)const_dep;
622 dep->dependency_type = dep_type;
626 * @brief Make a copy of a dependency structure
628 * @param[in,out] dep The kbase jd atom dependency to be written.
629 * @param[in] from The dependency to make a copy from.
632 static INLINE void base_jd_atom_dep_copy(const struct base_dependency* const_dep, const struct base_dependency* from)
634 LOCAL_ASSERT(const_dep != NULL);
636 base_jd_atom_dep_set(const_dep, from->atom_id, from->dependency_type);
640 * @brief Soft-atom fence trigger setup.
642 * Sets up an atom to be a SW-only atom signaling a fence
643 * when it reaches the run state.
645 * Using the existing base dependency system the fence can
646 * be set to trigger when a GPU job has finished.
648 * The base fence object must not be terminated until the atom
649 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
651 * @a fence must be a valid fence set up with @a base_fence_init.
652 * Calling this function with a uninitialized fence results in undefined behavior.
654 * @param[out] atom A pre-allocated atom to configure as a fence trigger SW atom
655 * @param[in] fence The base fence object to trigger.
657 static INLINE void base_jd_fence_trigger_setup_v2(struct base_jd_atom_v2 *atom, struct base_fence *fence)
661 LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
662 LOCAL_ASSERT(fence->basep.stream_fd >= 0);
663 atom->jc = (uintptr_t) fence;
664 atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
668 * @brief Soft-atom fence wait setup.
670 * Sets up an atom to be a SW-only atom waiting on a fence.
671 * When the fence becomes triggered the atom becomes runnable
672 * and completes immediately.
674 * Using the existing base dependency system the fence can
675 * be set to block a GPU job until it has been triggered.
677 * The base fence object must not be terminated until the atom
678 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
680 * @a fence must be a valid fence set up with @a base_fence_init or @a base_fence_import.
681 * Calling this function with a uninitialized fence results in undefined behavior.
683 * @param[out] atom A pre-allocated atom to configure as a fence wait SW atom
684 * @param[in] fence The base fence object to wait on
686 static INLINE void base_jd_fence_wait_setup_v2(struct base_jd_atom_v2 *atom, struct base_fence *fence)
690 LOCAL_ASSERT(fence->basep.fd >= 0);
691 atom->jc = (uintptr_t) fence;
692 atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
696 * @brief External resource info initialization.
698 * Sets up a external resource object to reference
699 * a memory allocation and the type of access requested.
701 * @param[in] res The resource object to initialize
702 * @param handle The handle to the imported memory object
703 * @param access The type of access requested
705 static INLINE void base_external_resource_init(struct base_external_resource * res, struct base_import_handle handle, base_external_resource_access access)
708 address = handle.basep.handle;
710 LOCAL_ASSERT(res != NULL);
711 LOCAL_ASSERT(0 == (address & LOCAL_PAGE_LSB));
712 LOCAL_ASSERT(access == BASE_EXT_RES_ACCESS_SHARED || access == BASE_EXT_RES_ACCESS_EXCLUSIVE);
714 res->ext_resource = address | (access & LOCAL_PAGE_LSB);
718 * @brief Job chain event code bits
719 * Defines the bits used to create ::base_jd_event_code
722 BASE_JD_SW_EVENT_KERNEL = (1u << 15), /**< Kernel side event */
723 BASE_JD_SW_EVENT = (1u << 14), /**< SW defined event */
724 BASE_JD_SW_EVENT_SUCCESS = (1u << 13), /**< Event idicates success (SW events only) */
725 BASE_JD_SW_EVENT_JOB = (0u << 11), /**< Job related event */
726 BASE_JD_SW_EVENT_BAG = (1u << 11), /**< Bag related event */
727 BASE_JD_SW_EVENT_INFO = (2u << 11), /**< Misc/info event */
728 BASE_JD_SW_EVENT_RESERVED = (3u << 11), /**< Reserved event type */
729 BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11) /**< Mask to extract the type from an event code */
733 * @brief Job chain event codes
735 * HW and low-level SW events are represented by event codes.
736 * The status of jobs which succeeded are also represented by
737 * an event code (see ::BASE_JD_EVENT_DONE).
738 * Events are usually reported as part of a ::base_jd_event.
740 * The event codes are encoded in the following way:
743 * @li 13 - SW success (only valid if the SW bit is set)
744 * @li 14 - SW event (HW event if not set)
745 * @li 15 - Kernel event (should never be seen in userspace)
747 * Events are split up into ranges as follows:
748 * - BASE_JD_EVENT_RANGE_\<description\>_START
749 * - BASE_JD_EVENT_RANGE_\<description\>_END
751 * \a code is in \<description\>'s range when:
752 * - <tt>BASE_JD_EVENT_RANGE_\<description\>_START <= code < BASE_JD_EVENT_RANGE_\<description\>_END </tt>
754 * Ranges can be asserted for adjacency by testing that the END of the previous
755 * is equal to the START of the next. This is useful for optimizing some tests
758 * A limitation is that the last member of this enum must explicitly be handled
759 * (with an assert-unreachable statement) in switch statements that use
760 * variables of this type. Otherwise, the compiler warns that we have not
761 * handled that enum value.
763 typedef enum base_jd_event_code {
764 /* HW defined exceptions */
766 /** Start of HW Non-fault status codes
768 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
769 * because the job was hard-stopped
771 BASE_JD_EVENT_RANGE_HW_NONFAULT_START = 0,
773 /* non-fatal exceptions */
774 BASE_JD_EVENT_NOT_STARTED = 0x00, /**< Can't be seen by userspace, treated as 'previous job done' */
775 BASE_JD_EVENT_DONE = 0x01,
776 BASE_JD_EVENT_STOPPED = 0x03, /**< Can't be seen by userspace, becomes TERMINATED, DONE or JOB_CANCELLED */
777 BASE_JD_EVENT_TERMINATED = 0x04, /**< This is actually a fault status code - the job was hard stopped */
778 BASE_JD_EVENT_ACTIVE = 0x08, /**< Can't be seen by userspace, jobs only returned on complete/fail/cancel */
780 /** End of HW Non-fault status codes
782 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
783 * because the job was hard-stopped
785 BASE_JD_EVENT_RANGE_HW_NONFAULT_END = 0x40,
787 /** Start of HW fault and SW Error status codes */
788 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START = 0x40,
791 BASE_JD_EVENT_JOB_CONFIG_FAULT = 0x40,
792 BASE_JD_EVENT_JOB_POWER_FAULT = 0x41,
793 BASE_JD_EVENT_JOB_READ_FAULT = 0x42,
794 BASE_JD_EVENT_JOB_WRITE_FAULT = 0x43,
795 BASE_JD_EVENT_JOB_AFFINITY_FAULT = 0x44,
796 BASE_JD_EVENT_JOB_BUS_FAULT = 0x48,
797 BASE_JD_EVENT_INSTR_INVALID_PC = 0x50,
798 BASE_JD_EVENT_INSTR_INVALID_ENC = 0x51,
799 BASE_JD_EVENT_INSTR_TYPE_MISMATCH = 0x52,
800 BASE_JD_EVENT_INSTR_OPERAND_FAULT = 0x53,
801 BASE_JD_EVENT_INSTR_TLS_FAULT = 0x54,
802 BASE_JD_EVENT_INSTR_BARRIER_FAULT = 0x55,
803 BASE_JD_EVENT_INSTR_ALIGN_FAULT = 0x56,
804 BASE_JD_EVENT_DATA_INVALID_FAULT = 0x58,
805 BASE_JD_EVENT_TILE_RANGE_FAULT = 0x59,
806 BASE_JD_EVENT_STATE_FAULT = 0x5A,
807 BASE_JD_EVENT_OUT_OF_MEMORY = 0x60,
808 BASE_JD_EVENT_UNKNOWN = 0x7F,
811 BASE_JD_EVENT_DELAYED_BUS_FAULT = 0x80,
812 BASE_JD_EVENT_SHAREABILITY_FAULT = 0x88,
815 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1 = 0xC1,
816 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2 = 0xC2,
817 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3 = 0xC3,
818 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4 = 0xC4,
819 BASE_JD_EVENT_PERMISSION_FAULT = 0xC8,
820 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1 = 0xD1,
821 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2 = 0xD2,
822 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3 = 0xD3,
823 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4 = 0xD4,
824 BASE_JD_EVENT_ACCESS_FLAG = 0xD8,
826 /* SW defined exceptions */
827 BASE_JD_EVENT_MEM_GROWTH_FAILED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
828 BASE_JD_EVENT_TIMED_OUT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001,
829 BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
830 BASE_JD_EVENT_JOB_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
831 BASE_JD_EVENT_PM_EVENT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004,
832 BASE_JD_EVENT_FORCE_REPLAY = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x005,
834 BASE_JD_EVENT_BAG_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003,
836 /** End of HW fault and SW Error status codes */
837 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
839 /** Start of SW Success status codes */
840 BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 0x000,
842 BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000,
843 BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_BAG | 0x000,
844 BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000,
846 /** End of SW Success status codes */
847 BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
849 /** Start of Kernel-only status codes. Such codes are never returned to user-space */
850 BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | 0x000,
851 BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000,
853 /** End of Kernel-only status codes. */
854 BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF
855 } base_jd_event_code;
858 * @brief Event reporting structure
860 * This structure is used by the kernel driver to report information
861 * about GPU events. The can either be HW-specific events or low-level
862 * SW events, such as job-chain completion.
864 * The event code contains an event type field which can be extracted
865 * by ANDing with ::BASE_JD_SW_EVENT_TYPE_MASK.
867 * Based on the event type base_jd_event::data holds:
868 * @li ::BASE_JD_SW_EVENT_JOB : the offset in the ring-buffer for the completed
870 * @li ::BASE_JD_SW_EVENT_BAG : The address of the ::base_jd_bag that has
871 * been completed (ie all contained job-chains have been completed).
872 * @li ::BASE_JD_SW_EVENT_INFO : base_jd_event::data not used
874 typedef struct base_jd_event_v2 {
875 base_jd_event_code event_code; /**< event code */
876 base_atom_id atom_number; /**< the atom number that has completed */
877 struct base_jd_udata udata; /**< user data */
881 * Padding required to ensure that the @ref struct base_dump_cpu_gpu_counters structure fills
885 #define BASE_CPU_GPU_CACHE_LINE_PADDING (36)
889 * @brief Structure for BASE_JD_REQ_SOFT_DUMP_CPU_GPU_COUNTERS jobs.
891 * This structure is stored into the memory pointed to by the @c jc field of @ref base_jd_atom.
893 * This structure must be padded to ensure that it will occupy whole cache lines. This is to avoid
894 * cases where access to pages containing the structure is shared between cached and un-cached
895 * memory regions, which would cause memory corruption. Here we set the structure size to be 64 bytes
896 * which is the cache line for ARM A15 processors.
899 typedef struct base_dump_cpu_gpu_counters {
904 u8 padding[BASE_CPU_GPU_CACHE_LINE_PADDING];
905 } base_dump_cpu_gpu_counters;
909 /** @} end group base_user_api_job_dispatch */
913 * The following typedefs should be removed when a midg types header is added.
914 * See MIDCOM-1657 for details.
916 typedef u32 midg_product_id;
917 typedef u32 midg_cache_features;
918 typedef u32 midg_tiler_features;
919 typedef u32 midg_mem_features;
920 typedef u32 midg_mmu_features;
921 typedef u32 midg_js_features;
922 typedef u32 midg_as_present;
923 typedef u32 midg_js_present;
925 #define MIDG_MAX_JOB_SLOTS 16
928 #include <midg/mali_midg.h>
932 * @page page_base_user_api_gpuprops User-side Base GPU Property Query API
934 * The User-side Base GPU Property Query API encapsulates two
937 * - @ref base_user_api_gpuprops_dyn "Dynamic GPU Properties"
938 * - @ref base_plat_config_gpuprops "Base Platform Config GPU Properties"
940 * There is a related third module outside of Base, which is owned by the MIDG
942 * - @ref midg_gpuprops_static "Midgard Compile-time GPU Properties"
944 * Base only deals with properties that vary between different Midgard
945 * implementations - the Dynamic GPU properties and the Platform Config
948 * For properties that are constant for the Midgard Architecture, refer to the
949 * MIDG module. However, we will discuss their relevance here <b>just to
950 * provide background information.</b>
952 * @section sec_base_user_api_gpuprops_about About the GPU Properties in Base and MIDG modules
954 * The compile-time properties (Platform Config, Midgard Compile-time
955 * properties) are exposed as pre-processor macros.
957 * Complementing the compile-time properties are the Dynamic GPU
958 * Properties, which act as a conduit for the Midgard Configuration
961 * In general, the dynamic properties are present to verify that the platform
962 * has been configured correctly with the right set of Platform Config
963 * Compile-time Properties.
965 * As a consistant guide across the entire DDK, the choice for dynamic or
966 * compile-time should consider the following, in order:
967 * -# Can the code be written so that it doesn't need to know the
968 * implementation limits at all?
969 * -# If you need the limits, get the information from the Dynamic Property
970 * lookup. This should be done once as you fetch the context, and then cached
971 * as part of the context data structure, so it's cheap to access.
972 * -# If there's a clear and arguable inefficiency in using Dynamic Properties,
973 * then use a Compile-Time Property (Platform Config, or Midgard Compile-time
974 * property). Examples of where this might be sensible follow:
975 * - Part of a critical inner-loop
976 * - Frequent re-use throughout the driver, causing significant extra load
977 * instructions or control flow that would be worthwhile optimizing out.
979 * We cannot provide an exhaustive set of examples, neither can we provide a
980 * rule for every possible situation. Use common sense, and think about: what
981 * the rest of the driver will be doing; how the compiler might represent the
982 * value if it is a compile-time constant; whether an OEM shipping multiple
983 * devices would benefit much more from a single DDK binary, instead of
984 * insignificant micro-optimizations.
986 * @section sec_base_user_api_gpuprops_dyn Dynamic GPU Properties
988 * Dynamic GPU properties are presented in two sets:
989 * -# the commonly used properties in @ref base_gpu_props, which have been
990 * unpacked from GPU register bitfields.
991 * -# The full set of raw, unprocessed properties in @ref midg_raw_gpu_props
992 * (also a member of @ref base_gpu_props). All of these are presented in
993 * the packed form, as presented by the GPU registers themselves.
995 * @usecase The raw properties in @ref midg_raw_gpu_props are necessary to
996 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
997 * behaving differently?". In this case, all information about the
998 * configuration is potentially useful, but it <b>does not need to be processed
999 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1000 * Tools software on the host PC.
1002 * The properties returned extend the Midgard Configuration Discovery
1003 * registers. For example, GPU clock speed is not specified in the Midgard
1004 * Architecture, but is <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1006 * The GPU properties are obtained by a call to
1007 * _mali_base_get_gpu_props(). This simply returns a pointer to a const
1008 * base_gpu_props structure. It is constant for the life of a base
1009 * context. Multiple calls to _mali_base_get_gpu_props() to a base context
1010 * return the same pointer to a constant structure. This avoids cache pollution
1011 * of the common data.
1013 * This pointer must not be freed, because it does not point to the start of a
1014 * region allocated by the memory allocator; instead, just close the @ref
1018 * @section sec_base_user_api_gpuprops_config Platform Config Compile-time Properties
1020 * The Platform Config File sets up gpu properties that are specific to a
1021 * certain platform. Properties that are 'Implementation Defined' in the
1022 * Midgard Architecture spec are placed here.
1024 * @note Reference configurations are provided for Midgard Implementations, such as
1025 * the Mali-T600 family. The customer need not repeat this information, and can select one of
1026 * these reference configurations. For example, VA_BITS, PA_BITS and the
1027 * maximum number of samples per pixel might vary between Midgard Implementations, but
1028 * \b not for platforms using the Mali-T604. This information is placed in
1029 * the reference configuration files.
1031 * The System Integrator creates the following structure:
1033 * - platform_XYZ/plat
1034 * - platform_XYZ/plat/plat_config.h
1036 * They then edit plat_config.h, using the example plat_config.h files as a
1039 * At the very least, the customer must set @ref CONFIG_GPU_CORE_TYPE, and will
1040 * receive a helpful \#error message if they do not do this correctly. This
1041 * selects the Reference Configuration for the Midgard Implementation. The rationale
1042 * behind this decision (against asking the customer to write \#include
1043 * <gpus/mali_t600.h> in their plat_config.h) is as follows:
1044 * - This mechanism 'looks' like a regular config file (such as Linux's
1046 * - It is difficult to get wrong in a way that will produce strange build
1048 * - They need not know where the mali_t600.h, other_midg_gpu.h etc. files are stored - and
1049 * so they won't accidentally pick another file with 'mali_t600' in its name
1050 * - When the build doesn't work, the System Integrator may think the DDK is
1051 * doesn't work, and attempt to fix it themselves:
1052 * - For the @ref CONFIG_GPU_CORE_TYPE mechanism, the only way to get past the
1053 * error is to set @ref CONFIG_GPU_CORE_TYPE, and this is what the \#error tells
1055 * - For a \#include mechanism, checks must still be made elsewhere, which the
1056 * System Integrator may try working around by setting \#defines (such as
1057 * VA_BITS) themselves in their plat_config.h. In the worst case, they may
1058 * set the prevention-mechanism \#define of
1059 * "A_CORRECT_MIDGARD_CORE_WAS_CHOSEN".
1060 * - In this case, they would believe they are on the right track, because
1061 * the build progresses with their fix, but with errors elsewhere.
1063 * However, there is nothing to prevent the customer using \#include to organize
1064 * their own configurations files hierarchically.
1066 * The mechanism for the header file processing is as follows:
1069 digraph plat_config_mechanism {
1078 rank = same; ordering = out;
1080 "midg/midg_gpu_props.h";
1081 "base/midg_gpus/mali_t600.h";
1082 "base/midg_gpus/other_midg_gpu.h";
1084 { rank = same; "plat/plat_config.h"; }
1087 "midg/midg.h" [ shape=box ];
1088 gpu_chooser [ label="" style="invisible" width=0 height=0 fixedsize=true ];
1089 select_gpu [ label="Mali-T600 | Other\n(select_gpu.h)" shape=polygon,sides=4,distortion=0.25 width=3.3 height=0.99 fixedsize=true ] ;
1092 { rank = same; "plat/plat_config.h"; }
1093 { rank = same; "mali_base.h"; }
1095 "mali_base.h" -> "midg/midg.h" -> "midg/midg_gpu_props.h";
1096 "mali_base.h" -> "plat/plat_config.h" ;
1097 "mali_base.h" -> select_gpu ;
1099 "plat/plat_config.h" -> gpu_chooser [style="dotted,bold" dir=none weight=4] ;
1100 gpu_chooser -> select_gpu [style="dotted,bold"] ;
1102 select_gpu -> "base/midg_gpus/mali_t600.h" ;
1103 select_gpu -> "base/midg_gpus/other_midg_gpu.h" ;
1108 * @section sec_base_user_api_gpuprops_kernel Kernel Operation
1110 * During Base Context Create time, user-side makes a single kernel call:
1111 * - A call to fill user memory with GPU information structures
1113 * The kernel-side will fill the provided the entire processed @ref base_gpu_props
1114 * structure, because this information is required in both
1115 * user and kernel side; it does not make sense to decode it twice.
1117 * Coherency groups must be derived from the bitmasks, but this can be done
1118 * kernel side, and just once at kernel startup: Coherency groups must already
1119 * be known kernel-side, to support chains that specify a 'Only Coherent Group'
1120 * SW requirement, or 'Only Coherent Group with Tiler' SW requirement.
1122 * @section sec_base_user_api_gpuprops_cocalc Coherency Group calculation
1123 * Creation of the coherent group data is done at device-driver startup, and so
1124 * is one-time. This will most likely involve a loop with CLZ, shifting, and
1125 * bit clearing on the L2_PRESENT or L3_PRESENT masks, depending on whether the
1126 * system is L2 or L2+L3 Coherent. The number of shader cores is done by a
1127 * population count, since faulty cores may be disabled during production,
1128 * producing a non-contiguous mask.
1130 * The memory requirements for this algoirthm can be determined either by a u64
1131 * population count on the L2/L3_PRESENT masks (a LUT helper already is
1132 * requried for the above), or simple assumption that there can be no more than
1133 * 16 coherent groups, since core groups are typically 4 cores.
1137 * @addtogroup base_user_api_gpuprops User-side Base GPU Property Query APIs
1142 * @addtogroup base_user_api_gpuprops_dyn Dynamic HW Properties
1146 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
1148 #define BASE_MAX_COHERENT_GROUPS 16
1150 struct mali_base_gpu_core_props {
1152 * Product specific value.
1154 midg_product_id product_id;
1157 * Status of the GPU release.
1158 * No defined values, but starts at 0 and increases by one for each release
1159 * status (alpha, beta, EAC, etc.).
1160 * 4 bit values (0-15).
1165 * Minor release number of the GPU. "P" part of an "RnPn" release number.
1166 * 8 bit values (0-255).
1171 * Major release number of the GPU. "R" part of an "RnPn" release number.
1172 * 4 bit values (0-15).
1179 * @usecase GPU clock speed is not specified in the Midgard Architecture, but is
1180 * <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1185 * @usecase GPU clock max/min speed is required for computing best/worst case
1186 * in tasks as job scheduling ant irq_throttling. (It is not specified in the
1187 * Midgard Architecture).
1189 u32 gpu_freq_khz_max;
1190 u32 gpu_freq_khz_min;
1193 * Size of the shader program counter, in bits.
1195 u32 log2_program_counter_size;
1198 * TEXTURE_FEATURES_x registers, as exposed by the GPU. This is a
1199 * bitpattern where a set bit indicates that the format is supported.
1201 * Before using a texture format, it is recommended that the corresponding
1204 u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
1207 * Theoretical maximum memory available to the GPU. It is unlikely that a
1208 * client will be able to allocate all of this memory for their own
1209 * purposes, but this at least provides an upper bound on the memory
1210 * available to the GPU.
1212 * This is required for OpenCL's clGetDeviceInfo() call when
1213 * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
1214 * client will not be expecting to allocate anywhere near this value.
1216 u64 gpu_available_memory_size;
1221 * More information is possible - but associativity and bus width are not
1222 * required by upper-level apis.
1224 struct mali_base_gpu_l2_cache_props {
1227 u8 num_l2_slices; /* Number of L2C slices. 1 or higher */
1231 struct mali_base_gpu_l3_cache_props {
1237 struct mali_base_gpu_tiler_props {
1238 u32 bin_size_bytes; /* Max is 4*2^15 */
1239 u32 max_active_levels; /* Max is 2^15 */
1243 * GPU threading system details.
1245 struct mali_base_gpu_thread_props {
1246 u32 max_threads; /* Max. number of threads per core */
1247 u32 max_workgroup_size; /* Max. number of threads per workgroup */
1248 u32 max_barrier_size; /* Max. number of threads that can synchronize on a simple barrier */
1249 u16 max_registers; /* Total size [1..65535] of the register file available per core. */
1250 u8 max_task_queue; /* Max. tasks [1..255] which may be sent to a core before it becomes blocked. */
1251 u8 max_thread_group_split; /* Max. allowed value [1..15] of the Thread Group Split field. */
1252 u8 impl_tech; /* 0 = Not specified, 1 = Silicon, 2 = FPGA, 3 = SW Model/Emulation */
1257 * @brief descriptor for a coherent group
1259 * \c core_mask exposes all cores in that coherent group, and \c num_cores
1260 * provides a cached population-count for that mask.
1262 * @note Whilst all cores are exposed in the mask, not all may be available to
1263 * the application, depending on the Kernel Job Scheduler policy. Therefore,
1264 * the application should not further restrict the core mask itself, as it may
1265 * result in an empty core mask. However, it can guarentee that there will be
1266 * at least one core available for each core group exposed .
1268 * @usecase Chains marked at certain user-side priorities (e.g. the Long-running
1269 * (batch) priority ) can be prevented from running on entire core groups by the
1270 * Kernel Chain Scheduler policy.
1272 * @note if u64s must be 8-byte aligned, then this structure has 32-bits of wastage.
1274 struct mali_base_gpu_coherent_group {
1275 u64 core_mask; /**< Core restriction mask required for the group */
1276 u16 num_cores; /**< Number of cores in the group */
1281 * @brief Coherency group information
1283 * Note that the sizes of the members could be reduced. However, the \c group
1284 * member might be 8-byte aligned to ensure the u64 core_mask is 8-byte
1285 * aligned, thus leading to wastage if the other members sizes were reduced.
1287 * The groups are sorted by core mask. The core masks are non-repeating and do
1290 struct mali_base_gpu_coherent_group_info {
1294 * Number of core groups (coherent or not) in the GPU. Equivalent to the number of L2 Caches.
1296 * The GPU Counter dumping writes 2048 bytes per core group, regardless of
1297 * whether the core groups are coherent or not. Hence this member is needed
1298 * to calculate how much memory is required for dumping.
1300 * @note Do not use it to work out how many valid elements are in the
1301 * group[] member. Use num_groups instead.
1303 u32 num_core_groups;
1306 * Coherency features of the memory, accessed by @ref midg_mem_features
1309 midg_mem_features coherency;
1314 * Descriptors of coherent groups
1316 struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
1320 * A complete description of the GPU's Hardware Configuration Discovery
1323 * The information is presented inefficiently for access. For frequent access,
1324 * the values should be better expressed in an unpacked form in the
1325 * base_gpu_props structure.
1327 * @usecase The raw properties in @ref midg_raw_gpu_props are necessary to
1328 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
1329 * behaving differently?". In this case, all information about the
1330 * configuration is potentially useful, but it <b>does not need to be processed
1331 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1332 * Tools software on the host PC.
1335 struct midg_raw_gpu_props {
1341 midg_cache_features l2_features;
1342 midg_cache_features l3_features;
1343 midg_mem_features mem_features;
1344 midg_mmu_features mmu_features;
1346 midg_as_present as_present;
1349 midg_js_features js_features[MIDG_MAX_JOB_SLOTS];
1350 midg_tiler_features tiler_features;
1351 u32 texture_features[3];
1355 u32 thread_max_threads;
1356 u32 thread_max_workgroup_size;
1357 u32 thread_max_barrier_size;
1358 u32 thread_features;
1364 * Return structure for _mali_base_get_gpu_props().
1366 * NOTE: the raw_props member in this datastructure contains the register
1367 * values from which the value of the other members are derived. The derived
1368 * members exist to allow for efficient access and/or shielding the details
1369 * of the layout of the registers.
1372 typedef struct mali_base_gpu_props {
1373 struct mali_base_gpu_core_props core_props;
1374 struct mali_base_gpu_l2_cache_props l2_props;
1375 struct mali_base_gpu_l3_cache_props l3_props;
1376 struct mali_base_gpu_tiler_props tiler_props;
1377 struct mali_base_gpu_thread_props thread_props;
1379 /** This member is large, likely to be 128 bytes */
1380 struct midg_raw_gpu_props raw_props;
1382 /** This must be last member of the structure */
1383 struct mali_base_gpu_coherent_group_info coherency_info;
1386 /** @} end group base_user_api_gpuprops_dyn */
1388 /** @} end group base_user_api_gpuprops */
1391 * @addtogroup base_user_api_core User-side Base core APIs
1396 * \enum base_context_create_flags
1398 * Flags to pass to ::base_context_init.
1399 * Flags can be ORed together to enable multiple things.
1401 * These share the same space as @ref basep_context_private_flags, and so must
1402 * not collide with them.
1404 enum base_context_create_flags {
1406 BASE_CONTEXT_CREATE_FLAG_NONE = 0,
1408 /** Base context is embedded in a cctx object (flag used for CINSTR software counter macros) */
1409 BASE_CONTEXT_CCTX_EMBEDDED = (1u << 0),
1411 /** Base context is a 'System Monitor' context for Hardware counters.
1413 * One important side effect of this is that job submission is disabled. */
1414 BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED = (1u << 1),
1416 /** Base context flag indicating a 'hint' that this context uses Compute
1419 * Specifially, this means that it only sends atoms that <b>do not</b>
1420 * contain the following @ref base_jd_core_req :
1424 * Violation of these requirements will cause the Job-Chains to be rejected.
1426 * In addition, it is inadvisable for the atom's Job-Chains to contain Jobs
1427 * of the following @ref midg_job_type (whilst it may work now, it may not
1429 * - @ref MIDG_JOB_VERTEX
1430 * - @ref MIDG_JOB_GEOMETRY
1432 * @note An alternative to using this is to specify the BASE_JD_REQ_ONLY_COMPUTE
1433 * requirement in atoms.
1435 BASE_CONTEXT_HINT_ONLY_COMPUTE = (1u << 2)
1439 * Bitpattern describing the ::base_context_create_flags that can be passed to base_context_init()
1441 #define BASE_CONTEXT_CREATE_ALLOWED_FLAGS \
1442 (((u32)BASE_CONTEXT_CCTX_EMBEDDED) | \
1443 ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED) | \
1444 ((u32)BASE_CONTEXT_HINT_ONLY_COMPUTE))
1447 * Bitpattern describing the ::base_context_create_flags that can be passed to the kernel
1449 #define BASE_CONTEXT_CREATE_KERNEL_FLAGS \
1450 (((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED) | \
1451 ((u32)BASE_CONTEXT_HINT_ONLY_COMPUTE))
1454 * Private flags used on the base context
1456 * These start at bit 31, and run down to zero.
1458 * They share the same space as @ref base_context_create_flags, and so must
1459 * not collide with them.
1461 enum basep_context_private_flags {
1462 /** Private flag tracking whether job descriptor dumping is disabled */
1463 BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED = (1 << 31)
1466 /** @} end group base_user_api_core */
1468 /** @} end group base_user_api */
1471 * @addtogroup base_plat_config_gpuprops Base Platform Config GPU Properties
1474 * C Pre-processor macros are exposed here to do with Platform
1478 * - GPU Properties that are constant on a particular Midgard Family
1479 * Implementation e.g. Maximum samples per pixel on Mali-T600.
1480 * - General platform config for the GPU, such as the GPU major and minor
1484 /** @} end group base_plat_config_gpuprops */
1487 * @addtogroup base_api Base APIs
1492 * @brief The payload for a replay job. This must be in GPU memory.
1494 typedef struct base_jd_replay_payload {
1496 * Pointer to the first entry in the base_jd_replay_jc list. These
1497 * will be replayed in @b reverse order (so that extra ones can be added
1498 * to the head in future soft jobs without affecting this soft job)
1500 mali_addr64 tiler_jc_list;
1503 * Pointer to the fragment job chain.
1505 mali_addr64 fragment_jc;
1508 * Pointer to the tiler heap free FBD field to be modified.
1510 mali_addr64 tiler_heap_free;
1513 * Hierarchy mask for the replayed fragment jobs. May be zero.
1515 u16 fragment_hierarchy_mask;
1518 * Hierarchy mask for the replayed tiler jobs. May be zero.
1520 u16 tiler_hierarchy_mask;
1523 * Default weight to be used for hierarchy levels not in the original
1526 u32 hierarchy_default_weight;
1529 * Core requirements for the tiler job chain
1531 base_jd_core_req tiler_core_req;
1534 * Core requirements for the fragment job chain
1536 base_jd_core_req fragment_core_req;
1539 } base_jd_replay_payload;
1542 * @brief An entry in the linked list of job chains to be replayed. This must
1545 typedef struct base_jd_replay_jc {
1547 * Pointer to next entry in the list. A setting of NULL indicates the
1553 * Pointer to the job chain.
1557 } base_jd_replay_jc;
1559 /* Maximum number of jobs allowed in a fragment chain in the payload of a
1561 #define BASE_JD_REPLAY_F_CHAIN_JOB_LIMIT 256
1563 /** @} end group base_api */
1565 typedef struct base_profiling_controls {
1566 u32 profiling_controls[FBDUMP_CONTROL_MAX];
1567 } base_profiling_controls;
1569 #endif /* _BASE_KERNEL_H_ */